mmc.c 68 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2008, Freescale Semiconductor, Inc
  4. * Andy Fleming
  5. *
  6. * Based vaguely on the Linux code
  7. */
  8. #include <config.h>
  9. #include <common.h>
  10. #include <blk.h>
  11. #include <command.h>
  12. #include <dm.h>
  13. #include <dm/device-internal.h>
  14. #include <errno.h>
  15. #include <mmc.h>
  16. #include <part.h>
  17. #include <power/regulator.h>
  18. #include <malloc.h>
  19. #include <memalign.h>
  20. #include <linux/list.h>
  21. #include <div64.h>
  22. #include "mmc_private.h"
  23. #define DEFAULT_CMD6_TIMEOUT_MS 500
  24. static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
  25. #if !CONFIG_IS_ENABLED(DM_MMC)
  26. static int mmc_wait_dat0(struct mmc *mmc, int state, int timeout_us)
  27. {
  28. return -ENOSYS;
  29. }
  30. __weak int board_mmc_getwp(struct mmc *mmc)
  31. {
  32. return -1;
  33. }
  34. int mmc_getwp(struct mmc *mmc)
  35. {
  36. int wp;
  37. wp = board_mmc_getwp(mmc);
  38. if (wp < 0) {
  39. if (mmc->cfg->ops->getwp)
  40. wp = mmc->cfg->ops->getwp(mmc);
  41. else
  42. wp = 0;
  43. }
  44. return wp;
  45. }
  46. __weak int board_mmc_getcd(struct mmc *mmc)
  47. {
  48. return -1;
  49. }
  50. #endif
  51. #ifdef CONFIG_MMC_TRACE
  52. void mmmc_trace_before_send(struct mmc *mmc, struct mmc_cmd *cmd)
  53. {
  54. printf("CMD_SEND:%d\n", cmd->cmdidx);
  55. printf("\t\tARG\t\t\t 0x%08x\n", cmd->cmdarg);
  56. }
  57. void mmmc_trace_after_send(struct mmc *mmc, struct mmc_cmd *cmd, int ret)
  58. {
  59. int i;
  60. u8 *ptr;
  61. if (ret) {
  62. printf("\t\tRET\t\t\t %d\n", ret);
  63. } else {
  64. switch (cmd->resp_type) {
  65. case MMC_RSP_NONE:
  66. printf("\t\tMMC_RSP_NONE\n");
  67. break;
  68. case MMC_RSP_R1:
  69. printf("\t\tMMC_RSP_R1,5,6,7 \t 0x%08x \n",
  70. cmd->response[0]);
  71. break;
  72. case MMC_RSP_R1b:
  73. printf("\t\tMMC_RSP_R1b\t\t 0x%08x \n",
  74. cmd->response[0]);
  75. break;
  76. case MMC_RSP_R2:
  77. printf("\t\tMMC_RSP_R2\t\t 0x%08x \n",
  78. cmd->response[0]);
  79. printf("\t\t \t\t 0x%08x \n",
  80. cmd->response[1]);
  81. printf("\t\t \t\t 0x%08x \n",
  82. cmd->response[2]);
  83. printf("\t\t \t\t 0x%08x \n",
  84. cmd->response[3]);
  85. printf("\n");
  86. printf("\t\t\t\t\tDUMPING DATA\n");
  87. for (i = 0; i < 4; i++) {
  88. int j;
  89. printf("\t\t\t\t\t%03d - ", i*4);
  90. ptr = (u8 *)&cmd->response[i];
  91. ptr += 3;
  92. for (j = 0; j < 4; j++)
  93. printf("%02x ", *ptr--);
  94. printf("\n");
  95. }
  96. break;
  97. case MMC_RSP_R3:
  98. printf("\t\tMMC_RSP_R3,4\t\t 0x%08x \n",
  99. cmd->response[0]);
  100. break;
  101. default:
  102. printf("\t\tERROR MMC rsp not supported\n");
  103. break;
  104. }
  105. }
  106. }
  107. void mmc_trace_state(struct mmc *mmc, struct mmc_cmd *cmd)
  108. {
  109. int status;
  110. status = (cmd->response[0] & MMC_STATUS_CURR_STATE) >> 9;
  111. printf("CURR STATE:%d\n", status);
  112. }
  113. #endif
  114. #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
  115. const char *mmc_mode_name(enum bus_mode mode)
  116. {
  117. static const char *const names[] = {
  118. [MMC_LEGACY] = "MMC legacy",
  119. [MMC_HS] = "MMC High Speed (26MHz)",
  120. [SD_HS] = "SD High Speed (50MHz)",
  121. [UHS_SDR12] = "UHS SDR12 (25MHz)",
  122. [UHS_SDR25] = "UHS SDR25 (50MHz)",
  123. [UHS_SDR50] = "UHS SDR50 (100MHz)",
  124. [UHS_SDR104] = "UHS SDR104 (208MHz)",
  125. [UHS_DDR50] = "UHS DDR50 (50MHz)",
  126. [MMC_HS_52] = "MMC High Speed (52MHz)",
  127. [MMC_DDR_52] = "MMC DDR52 (52MHz)",
  128. [MMC_HS_200] = "HS200 (200MHz)",
  129. [MMC_HS_400] = "HS400 (200MHz)",
  130. [MMC_HS_400_ES] = "HS400ES (200MHz)",
  131. };
  132. if (mode >= MMC_MODES_END)
  133. return "Unknown mode";
  134. else
  135. return names[mode];
  136. }
  137. #endif
  138. static uint mmc_mode2freq(struct mmc *mmc, enum bus_mode mode)
  139. {
  140. static const int freqs[] = {
  141. [MMC_LEGACY] = 25000000,
  142. [MMC_HS] = 26000000,
  143. [SD_HS] = 50000000,
  144. [MMC_HS_52] = 52000000,
  145. [MMC_DDR_52] = 52000000,
  146. [UHS_SDR12] = 25000000,
  147. [UHS_SDR25] = 50000000,
  148. [UHS_SDR50] = 100000000,
  149. [UHS_DDR50] = 50000000,
  150. [UHS_SDR104] = 208000000,
  151. [MMC_HS_200] = 200000000,
  152. [MMC_HS_400] = 200000000,
  153. [MMC_HS_400_ES] = 200000000,
  154. };
  155. if (mode == MMC_LEGACY)
  156. return mmc->legacy_speed;
  157. else if (mode >= MMC_MODES_END)
  158. return 0;
  159. else
  160. return freqs[mode];
  161. }
  162. static int mmc_select_mode(struct mmc *mmc, enum bus_mode mode)
  163. {
  164. mmc->selected_mode = mode;
  165. mmc->tran_speed = mmc_mode2freq(mmc, mode);
  166. mmc->ddr_mode = mmc_is_mode_ddr(mode);
  167. pr_debug("selecting mode %s (freq : %d MHz)\n", mmc_mode_name(mode),
  168. mmc->tran_speed / 1000000);
  169. return 0;
  170. }
  171. #if !CONFIG_IS_ENABLED(DM_MMC)
  172. int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  173. {
  174. int ret;
  175. mmmc_trace_before_send(mmc, cmd);
  176. ret = mmc->cfg->ops->send_cmd(mmc, cmd, data);
  177. mmmc_trace_after_send(mmc, cmd, ret);
  178. return ret;
  179. }
  180. #endif
  181. int mmc_send_status(struct mmc *mmc, unsigned int *status)
  182. {
  183. struct mmc_cmd cmd;
  184. int err, retries = 5;
  185. cmd.cmdidx = MMC_CMD_SEND_STATUS;
  186. cmd.resp_type = MMC_RSP_R1;
  187. if (!mmc_host_is_spi(mmc))
  188. cmd.cmdarg = mmc->rca << 16;
  189. while (retries--) {
  190. err = mmc_send_cmd(mmc, &cmd, NULL);
  191. if (!err) {
  192. mmc_trace_state(mmc, &cmd);
  193. *status = cmd.response[0];
  194. return 0;
  195. }
  196. }
  197. mmc_trace_state(mmc, &cmd);
  198. return -ECOMM;
  199. }
  200. int mmc_poll_for_busy(struct mmc *mmc, int timeout_ms)
  201. {
  202. unsigned int status;
  203. int err;
  204. err = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
  205. if (err != -ENOSYS)
  206. return err;
  207. while (1) {
  208. err = mmc_send_status(mmc, &status);
  209. if (err)
  210. return err;
  211. if ((status & MMC_STATUS_RDY_FOR_DATA) &&
  212. (status & MMC_STATUS_CURR_STATE) !=
  213. MMC_STATE_PRG)
  214. break;
  215. if (status & MMC_STATUS_MASK) {
  216. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  217. pr_err("Status Error: 0x%08x\n", status);
  218. #endif
  219. return -ECOMM;
  220. }
  221. if (timeout_ms-- <= 0)
  222. break;
  223. udelay(1000);
  224. }
  225. if (timeout_ms <= 0) {
  226. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  227. pr_err("Timeout waiting card ready\n");
  228. #endif
  229. return -ETIMEDOUT;
  230. }
  231. return 0;
  232. }
  233. int mmc_set_blocklen(struct mmc *mmc, int len)
  234. {
  235. struct mmc_cmd cmd;
  236. int err;
  237. if (mmc->ddr_mode)
  238. return 0;
  239. cmd.cmdidx = MMC_CMD_SET_BLOCKLEN;
  240. cmd.resp_type = MMC_RSP_R1;
  241. cmd.cmdarg = len;
  242. err = mmc_send_cmd(mmc, &cmd, NULL);
  243. #ifdef CONFIG_MMC_QUIRKS
  244. if (err && (mmc->quirks & MMC_QUIRK_RETRY_SET_BLOCKLEN)) {
  245. int retries = 4;
  246. /*
  247. * It has been seen that SET_BLOCKLEN may fail on the first
  248. * attempt, let's try a few more time
  249. */
  250. do {
  251. err = mmc_send_cmd(mmc, &cmd, NULL);
  252. if (!err)
  253. break;
  254. } while (retries--);
  255. }
  256. #endif
  257. return err;
  258. }
  259. #ifdef MMC_SUPPORTS_TUNING
  260. static const u8 tuning_blk_pattern_4bit[] = {
  261. 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
  262. 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
  263. 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
  264. 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
  265. 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
  266. 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
  267. 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
  268. 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
  269. };
  270. static const u8 tuning_blk_pattern_8bit[] = {
  271. 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
  272. 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
  273. 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
  274. 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
  275. 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
  276. 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
  277. 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
  278. 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
  279. 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
  280. 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
  281. 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
  282. 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
  283. 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
  284. 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
  285. 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
  286. 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
  287. };
  288. int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error)
  289. {
  290. struct mmc_cmd cmd;
  291. struct mmc_data data;
  292. const u8 *tuning_block_pattern;
  293. int size, err;
  294. if (mmc->bus_width == 8) {
  295. tuning_block_pattern = tuning_blk_pattern_8bit;
  296. size = sizeof(tuning_blk_pattern_8bit);
  297. } else if (mmc->bus_width == 4) {
  298. tuning_block_pattern = tuning_blk_pattern_4bit;
  299. size = sizeof(tuning_blk_pattern_4bit);
  300. } else {
  301. return -EINVAL;
  302. }
  303. ALLOC_CACHE_ALIGN_BUFFER(u8, data_buf, size);
  304. cmd.cmdidx = opcode;
  305. cmd.cmdarg = 0;
  306. cmd.resp_type = MMC_RSP_R1;
  307. data.dest = (void *)data_buf;
  308. data.blocks = 1;
  309. data.blocksize = size;
  310. data.flags = MMC_DATA_READ;
  311. err = mmc_send_cmd(mmc, &cmd, &data);
  312. if (err)
  313. return err;
  314. if (memcmp(data_buf, tuning_block_pattern, size))
  315. return -EIO;
  316. return 0;
  317. }
  318. #endif
  319. static int mmc_read_blocks(struct mmc *mmc, void *dst, lbaint_t start,
  320. lbaint_t blkcnt)
  321. {
  322. struct mmc_cmd cmd;
  323. struct mmc_data data;
  324. if (blkcnt > 1)
  325. cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
  326. else
  327. cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
  328. if (mmc->high_capacity)
  329. cmd.cmdarg = start;
  330. else
  331. cmd.cmdarg = start * mmc->read_bl_len;
  332. cmd.resp_type = MMC_RSP_R1;
  333. data.dest = dst;
  334. data.blocks = blkcnt;
  335. data.blocksize = mmc->read_bl_len;
  336. data.flags = MMC_DATA_READ;
  337. if (mmc_send_cmd(mmc, &cmd, &data))
  338. return 0;
  339. if (blkcnt > 1) {
  340. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  341. cmd.cmdarg = 0;
  342. cmd.resp_type = MMC_RSP_R1b;
  343. if (mmc_send_cmd(mmc, &cmd, NULL)) {
  344. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  345. pr_err("mmc fail to send stop cmd\n");
  346. #endif
  347. return 0;
  348. }
  349. }
  350. return blkcnt;
  351. }
  352. #if !CONFIG_IS_ENABLED(DM_MMC)
  353. static int mmc_get_b_max(struct mmc *mmc, void *dst, lbaint_t blkcnt)
  354. {
  355. if (mmc->cfg->ops->get_b_max)
  356. return mmc->cfg->ops->get_b_max(mmc, dst, blkcnt);
  357. else
  358. return mmc->cfg->b_max;
  359. }
  360. #endif
  361. #if CONFIG_IS_ENABLED(BLK)
  362. ulong mmc_bread(struct udevice *dev, lbaint_t start, lbaint_t blkcnt, void *dst)
  363. #else
  364. ulong mmc_bread(struct blk_desc *block_dev, lbaint_t start, lbaint_t blkcnt,
  365. void *dst)
  366. #endif
  367. {
  368. #if CONFIG_IS_ENABLED(BLK)
  369. struct blk_desc *block_dev = dev_get_uclass_platdata(dev);
  370. #endif
  371. int dev_num = block_dev->devnum;
  372. int err;
  373. lbaint_t cur, blocks_todo = blkcnt;
  374. uint b_max;
  375. if (blkcnt == 0)
  376. return 0;
  377. struct mmc *mmc = find_mmc_device(dev_num);
  378. if (!mmc)
  379. return 0;
  380. if (CONFIG_IS_ENABLED(MMC_TINY))
  381. err = mmc_switch_part(mmc, block_dev->hwpart);
  382. else
  383. err = blk_dselect_hwpart(block_dev, block_dev->hwpart);
  384. if (err < 0)
  385. return 0;
  386. if ((start + blkcnt) > block_dev->lba) {
  387. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  388. pr_err("MMC: block number 0x" LBAF " exceeds max(0x" LBAF ")\n",
  389. start + blkcnt, block_dev->lba);
  390. #endif
  391. return 0;
  392. }
  393. if (mmc_set_blocklen(mmc, mmc->read_bl_len)) {
  394. pr_debug("%s: Failed to set blocklen\n", __func__);
  395. return 0;
  396. }
  397. b_max = mmc_get_b_max(mmc, dst, blkcnt);
  398. do {
  399. cur = (blocks_todo > b_max) ? b_max : blocks_todo;
  400. if (mmc_read_blocks(mmc, dst, start, cur) != cur) {
  401. pr_debug("%s: Failed to read blocks\n", __func__);
  402. return 0;
  403. }
  404. blocks_todo -= cur;
  405. start += cur;
  406. dst += cur * mmc->read_bl_len;
  407. } while (blocks_todo > 0);
  408. return blkcnt;
  409. }
  410. static int mmc_go_idle(struct mmc *mmc)
  411. {
  412. struct mmc_cmd cmd;
  413. int err;
  414. udelay(1000);
  415. cmd.cmdidx = MMC_CMD_GO_IDLE_STATE;
  416. cmd.cmdarg = 0;
  417. cmd.resp_type = MMC_RSP_NONE;
  418. err = mmc_send_cmd(mmc, &cmd, NULL);
  419. if (err)
  420. return err;
  421. udelay(2000);
  422. return 0;
  423. }
  424. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  425. static int mmc_switch_voltage(struct mmc *mmc, int signal_voltage)
  426. {
  427. struct mmc_cmd cmd;
  428. int err = 0;
  429. /*
  430. * Send CMD11 only if the request is to switch the card to
  431. * 1.8V signalling.
  432. */
  433. if (signal_voltage == MMC_SIGNAL_VOLTAGE_330)
  434. return mmc_set_signal_voltage(mmc, signal_voltage);
  435. cmd.cmdidx = SD_CMD_SWITCH_UHS18V;
  436. cmd.cmdarg = 0;
  437. cmd.resp_type = MMC_RSP_R1;
  438. err = mmc_send_cmd(mmc, &cmd, NULL);
  439. if (err)
  440. return err;
  441. if (!mmc_host_is_spi(mmc) && (cmd.response[0] & MMC_STATUS_ERROR))
  442. return -EIO;
  443. /*
  444. * The card should drive cmd and dat[0:3] low immediately
  445. * after the response of cmd11, but wait 100 us to be sure
  446. */
  447. err = mmc_wait_dat0(mmc, 0, 100);
  448. if (err == -ENOSYS)
  449. udelay(100);
  450. else if (err)
  451. return -ETIMEDOUT;
  452. /*
  453. * During a signal voltage level switch, the clock must be gated
  454. * for 5 ms according to the SD spec
  455. */
  456. mmc_set_clock(mmc, mmc->clock, MMC_CLK_DISABLE);
  457. err = mmc_set_signal_voltage(mmc, signal_voltage);
  458. if (err)
  459. return err;
  460. /* Keep clock gated for at least 10 ms, though spec only says 5 ms */
  461. mdelay(10);
  462. mmc_set_clock(mmc, mmc->clock, MMC_CLK_ENABLE);
  463. /*
  464. * Failure to switch is indicated by the card holding
  465. * dat[0:3] low. Wait for at least 1 ms according to spec
  466. */
  467. err = mmc_wait_dat0(mmc, 1, 1000);
  468. if (err == -ENOSYS)
  469. udelay(1000);
  470. else if (err)
  471. return -ETIMEDOUT;
  472. return 0;
  473. }
  474. #endif
  475. static int sd_send_op_cond(struct mmc *mmc, bool uhs_en)
  476. {
  477. int timeout = 1000;
  478. int err;
  479. struct mmc_cmd cmd;
  480. while (1) {
  481. cmd.cmdidx = MMC_CMD_APP_CMD;
  482. cmd.resp_type = MMC_RSP_R1;
  483. cmd.cmdarg = 0;
  484. err = mmc_send_cmd(mmc, &cmd, NULL);
  485. if (err)
  486. return err;
  487. cmd.cmdidx = SD_CMD_APP_SEND_OP_COND;
  488. cmd.resp_type = MMC_RSP_R3;
  489. /*
  490. * Most cards do not answer if some reserved bits
  491. * in the ocr are set. However, Some controller
  492. * can set bit 7 (reserved for low voltages), but
  493. * how to manage low voltages SD card is not yet
  494. * specified.
  495. */
  496. cmd.cmdarg = mmc_host_is_spi(mmc) ? 0 :
  497. (mmc->cfg->voltages & 0xff8000);
  498. if (mmc->version == SD_VERSION_2)
  499. cmd.cmdarg |= OCR_HCS;
  500. if (uhs_en)
  501. cmd.cmdarg |= OCR_S18R;
  502. err = mmc_send_cmd(mmc, &cmd, NULL);
  503. if (err)
  504. return err;
  505. if (cmd.response[0] & OCR_BUSY)
  506. break;
  507. if (timeout-- <= 0)
  508. return -EOPNOTSUPP;
  509. udelay(1000);
  510. }
  511. if (mmc->version != SD_VERSION_2)
  512. mmc->version = SD_VERSION_1_0;
  513. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  514. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  515. cmd.resp_type = MMC_RSP_R3;
  516. cmd.cmdarg = 0;
  517. err = mmc_send_cmd(mmc, &cmd, NULL);
  518. if (err)
  519. return err;
  520. }
  521. mmc->ocr = cmd.response[0];
  522. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  523. if (uhs_en && !(mmc_host_is_spi(mmc)) && (cmd.response[0] & 0x41000000)
  524. == 0x41000000) {
  525. err = mmc_switch_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
  526. if (err)
  527. return err;
  528. }
  529. #endif
  530. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  531. mmc->rca = 0;
  532. return 0;
  533. }
  534. static int mmc_send_op_cond_iter(struct mmc *mmc, int use_arg)
  535. {
  536. struct mmc_cmd cmd;
  537. int err;
  538. cmd.cmdidx = MMC_CMD_SEND_OP_COND;
  539. cmd.resp_type = MMC_RSP_R3;
  540. cmd.cmdarg = 0;
  541. if (use_arg && !mmc_host_is_spi(mmc))
  542. cmd.cmdarg = OCR_HCS |
  543. (mmc->cfg->voltages &
  544. (mmc->ocr & OCR_VOLTAGE_MASK)) |
  545. (mmc->ocr & OCR_ACCESS_MODE);
  546. err = mmc_send_cmd(mmc, &cmd, NULL);
  547. if (err)
  548. return err;
  549. mmc->ocr = cmd.response[0];
  550. return 0;
  551. }
  552. static int mmc_send_op_cond(struct mmc *mmc)
  553. {
  554. int err, i;
  555. /* Some cards seem to need this */
  556. mmc_go_idle(mmc);
  557. /* Asking to the card its capabilities */
  558. for (i = 0; i < 2; i++) {
  559. err = mmc_send_op_cond_iter(mmc, i != 0);
  560. if (err)
  561. return err;
  562. /* exit if not busy (flag seems to be inverted) */
  563. if (mmc->ocr & OCR_BUSY)
  564. break;
  565. }
  566. mmc->op_cond_pending = 1;
  567. return 0;
  568. }
  569. static int mmc_complete_op_cond(struct mmc *mmc)
  570. {
  571. struct mmc_cmd cmd;
  572. int timeout = 1000;
  573. ulong start;
  574. int err;
  575. mmc->op_cond_pending = 0;
  576. if (!(mmc->ocr & OCR_BUSY)) {
  577. /* Some cards seem to need this */
  578. mmc_go_idle(mmc);
  579. start = get_timer(0);
  580. while (1) {
  581. err = mmc_send_op_cond_iter(mmc, 1);
  582. if (err)
  583. return err;
  584. if (mmc->ocr & OCR_BUSY)
  585. break;
  586. if (get_timer(start) > timeout)
  587. return -EOPNOTSUPP;
  588. udelay(100);
  589. }
  590. }
  591. if (mmc_host_is_spi(mmc)) { /* read OCR for spi */
  592. cmd.cmdidx = MMC_CMD_SPI_READ_OCR;
  593. cmd.resp_type = MMC_RSP_R3;
  594. cmd.cmdarg = 0;
  595. err = mmc_send_cmd(mmc, &cmd, NULL);
  596. if (err)
  597. return err;
  598. mmc->ocr = cmd.response[0];
  599. }
  600. mmc->version = MMC_VERSION_UNKNOWN;
  601. mmc->high_capacity = ((mmc->ocr & OCR_HCS) == OCR_HCS);
  602. mmc->rca = 1;
  603. return 0;
  604. }
  605. int mmc_send_ext_csd(struct mmc *mmc, u8 *ext_csd)
  606. {
  607. struct mmc_cmd cmd;
  608. struct mmc_data data;
  609. int err;
  610. /* Get the Card Status Register */
  611. cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
  612. cmd.resp_type = MMC_RSP_R1;
  613. cmd.cmdarg = 0;
  614. data.dest = (char *)ext_csd;
  615. data.blocks = 1;
  616. data.blocksize = MMC_MAX_BLOCK_LEN;
  617. data.flags = MMC_DATA_READ;
  618. err = mmc_send_cmd(mmc, &cmd, &data);
  619. return err;
  620. }
  621. static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
  622. bool send_status)
  623. {
  624. unsigned int status, start;
  625. struct mmc_cmd cmd;
  626. int timeout_ms = DEFAULT_CMD6_TIMEOUT_MS;
  627. bool is_part_switch = (set == EXT_CSD_CMD_SET_NORMAL) &&
  628. (index == EXT_CSD_PART_CONF);
  629. int retries = 3;
  630. int ret;
  631. if (mmc->gen_cmd6_time)
  632. timeout_ms = mmc->gen_cmd6_time * 10;
  633. if (is_part_switch && mmc->part_switch_time)
  634. timeout_ms = mmc->part_switch_time * 10;
  635. cmd.cmdidx = MMC_CMD_SWITCH;
  636. cmd.resp_type = MMC_RSP_R1b;
  637. cmd.cmdarg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
  638. (index << 16) |
  639. (value << 8);
  640. do {
  641. ret = mmc_send_cmd(mmc, &cmd, NULL);
  642. } while (ret && retries-- > 0);
  643. if (ret)
  644. return ret;
  645. start = get_timer(0);
  646. /* poll dat0 for rdy/buys status */
  647. ret = mmc_wait_dat0(mmc, 1, timeout_ms * 1000);
  648. if (ret && ret != -ENOSYS)
  649. return ret;
  650. /*
  651. * In cases when not allowed to poll by using CMD13 or because we aren't
  652. * capable of polling by using mmc_wait_dat0, then rely on waiting the
  653. * stated timeout to be sufficient.
  654. */
  655. if (ret == -ENOSYS && !send_status)
  656. mdelay(timeout_ms);
  657. /* Finally wait until the card is ready or indicates a failure
  658. * to switch. It doesn't hurt to use CMD13 here even if send_status
  659. * is false, because by now (after 'timeout_ms' ms) the bus should be
  660. * reliable.
  661. */
  662. do {
  663. ret = mmc_send_status(mmc, &status);
  664. if (!ret && (status & MMC_STATUS_SWITCH_ERROR)) {
  665. pr_debug("switch failed %d/%d/0x%x !\n", set, index,
  666. value);
  667. return -EIO;
  668. }
  669. if (!ret && (status & MMC_STATUS_RDY_FOR_DATA))
  670. return 0;
  671. udelay(100);
  672. } while (get_timer(start) < timeout_ms);
  673. return -ETIMEDOUT;
  674. }
  675. int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value)
  676. {
  677. return __mmc_switch(mmc, set, index, value, true);
  678. }
  679. int mmc_boot_wp(struct mmc *mmc)
  680. {
  681. return mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BOOT_WP, 1);
  682. }
  683. #if !CONFIG_IS_ENABLED(MMC_TINY)
  684. static int mmc_set_card_speed(struct mmc *mmc, enum bus_mode mode,
  685. bool hsdowngrade)
  686. {
  687. int err;
  688. int speed_bits;
  689. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  690. switch (mode) {
  691. case MMC_HS:
  692. case MMC_HS_52:
  693. case MMC_DDR_52:
  694. speed_bits = EXT_CSD_TIMING_HS;
  695. break;
  696. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  697. case MMC_HS_200:
  698. speed_bits = EXT_CSD_TIMING_HS200;
  699. break;
  700. #endif
  701. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  702. case MMC_HS_400:
  703. speed_bits = EXT_CSD_TIMING_HS400;
  704. break;
  705. #endif
  706. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  707. case MMC_HS_400_ES:
  708. speed_bits = EXT_CSD_TIMING_HS400;
  709. break;
  710. #endif
  711. case MMC_LEGACY:
  712. speed_bits = EXT_CSD_TIMING_LEGACY;
  713. break;
  714. default:
  715. return -EINVAL;
  716. }
  717. err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING,
  718. speed_bits, !hsdowngrade);
  719. if (err)
  720. return err;
  721. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  722. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  723. /*
  724. * In case the eMMC is in HS200/HS400 mode and we are downgrading
  725. * to HS mode, the card clock are still running much faster than
  726. * the supported HS mode clock, so we can not reliably read out
  727. * Extended CSD. Reconfigure the controller to run at HS mode.
  728. */
  729. if (hsdowngrade) {
  730. mmc_select_mode(mmc, MMC_HS);
  731. mmc_set_clock(mmc, mmc_mode2freq(mmc, MMC_HS), false);
  732. }
  733. #endif
  734. if ((mode == MMC_HS) || (mode == MMC_HS_52)) {
  735. /* Now check to see that it worked */
  736. err = mmc_send_ext_csd(mmc, test_csd);
  737. if (err)
  738. return err;
  739. /* No high-speed support */
  740. if (!test_csd[EXT_CSD_HS_TIMING])
  741. return -ENOTSUPP;
  742. }
  743. return 0;
  744. }
  745. static int mmc_get_capabilities(struct mmc *mmc)
  746. {
  747. u8 *ext_csd = mmc->ext_csd;
  748. char cardtype;
  749. mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
  750. if (mmc_host_is_spi(mmc))
  751. return 0;
  752. /* Only version 4 supports high-speed */
  753. if (mmc->version < MMC_VERSION_4)
  754. return 0;
  755. if (!ext_csd) {
  756. pr_err("No ext_csd found!\n"); /* this should enver happen */
  757. return -ENOTSUPP;
  758. }
  759. mmc->card_caps |= MMC_MODE_4BIT | MMC_MODE_8BIT;
  760. cardtype = ext_csd[EXT_CSD_CARD_TYPE];
  761. mmc->cardtype = cardtype;
  762. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  763. if (cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
  764. EXT_CSD_CARD_TYPE_HS200_1_8V)) {
  765. mmc->card_caps |= MMC_MODE_HS200;
  766. }
  767. #endif
  768. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
  769. CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  770. if (cardtype & (EXT_CSD_CARD_TYPE_HS400_1_2V |
  771. EXT_CSD_CARD_TYPE_HS400_1_8V)) {
  772. mmc->card_caps |= MMC_MODE_HS400;
  773. }
  774. #endif
  775. if (cardtype & EXT_CSD_CARD_TYPE_52) {
  776. if (cardtype & EXT_CSD_CARD_TYPE_DDR_52)
  777. mmc->card_caps |= MMC_MODE_DDR_52MHz;
  778. mmc->card_caps |= MMC_MODE_HS_52MHz;
  779. }
  780. if (cardtype & EXT_CSD_CARD_TYPE_26)
  781. mmc->card_caps |= MMC_MODE_HS;
  782. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  783. if (ext_csd[EXT_CSD_STROBE_SUPPORT] &&
  784. (mmc->card_caps & MMC_MODE_HS400)) {
  785. mmc->card_caps |= MMC_MODE_HS400_ES;
  786. }
  787. #endif
  788. return 0;
  789. }
  790. #endif
  791. static int mmc_set_capacity(struct mmc *mmc, int part_num)
  792. {
  793. switch (part_num) {
  794. case 0:
  795. mmc->capacity = mmc->capacity_user;
  796. break;
  797. case 1:
  798. case 2:
  799. mmc->capacity = mmc->capacity_boot;
  800. break;
  801. case 3:
  802. mmc->capacity = mmc->capacity_rpmb;
  803. break;
  804. case 4:
  805. case 5:
  806. case 6:
  807. case 7:
  808. mmc->capacity = mmc->capacity_gp[part_num - 4];
  809. break;
  810. default:
  811. return -1;
  812. }
  813. mmc_get_blk_desc(mmc)->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  814. return 0;
  815. }
  816. int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
  817. {
  818. int ret;
  819. int retry = 3;
  820. do {
  821. ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  822. EXT_CSD_PART_CONF,
  823. (mmc->part_config & ~PART_ACCESS_MASK)
  824. | (part_num & PART_ACCESS_MASK));
  825. } while (ret && retry--);
  826. /*
  827. * Set the capacity if the switch succeeded or was intended
  828. * to return to representing the raw device.
  829. */
  830. if ((ret == 0) || ((ret == -ENODEV) && (part_num == 0))) {
  831. ret = mmc_set_capacity(mmc, part_num);
  832. mmc_get_blk_desc(mmc)->hwpart = part_num;
  833. }
  834. return ret;
  835. }
  836. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  837. int mmc_hwpart_config(struct mmc *mmc,
  838. const struct mmc_hwpart_conf *conf,
  839. enum mmc_hwpart_conf_mode mode)
  840. {
  841. u8 part_attrs = 0;
  842. u32 enh_size_mult;
  843. u32 enh_start_addr;
  844. u32 gp_size_mult[4];
  845. u32 max_enh_size_mult;
  846. u32 tot_enh_size_mult = 0;
  847. u8 wr_rel_set;
  848. int i, pidx, err;
  849. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  850. if (mode < MMC_HWPART_CONF_CHECK || mode > MMC_HWPART_CONF_COMPLETE)
  851. return -EINVAL;
  852. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4_41)) {
  853. pr_err("eMMC >= 4.4 required for enhanced user data area\n");
  854. return -EMEDIUMTYPE;
  855. }
  856. if (!(mmc->part_support & PART_SUPPORT)) {
  857. pr_err("Card does not support partitioning\n");
  858. return -EMEDIUMTYPE;
  859. }
  860. if (!mmc->hc_wp_grp_size) {
  861. pr_err("Card does not define HC WP group size\n");
  862. return -EMEDIUMTYPE;
  863. }
  864. /* check partition alignment and total enhanced size */
  865. if (conf->user.enh_size) {
  866. if (conf->user.enh_size % mmc->hc_wp_grp_size ||
  867. conf->user.enh_start % mmc->hc_wp_grp_size) {
  868. pr_err("User data enhanced area not HC WP group "
  869. "size aligned\n");
  870. return -EINVAL;
  871. }
  872. part_attrs |= EXT_CSD_ENH_USR;
  873. enh_size_mult = conf->user.enh_size / mmc->hc_wp_grp_size;
  874. if (mmc->high_capacity) {
  875. enh_start_addr = conf->user.enh_start;
  876. } else {
  877. enh_start_addr = (conf->user.enh_start << 9);
  878. }
  879. } else {
  880. enh_size_mult = 0;
  881. enh_start_addr = 0;
  882. }
  883. tot_enh_size_mult += enh_size_mult;
  884. for (pidx = 0; pidx < 4; pidx++) {
  885. if (conf->gp_part[pidx].size % mmc->hc_wp_grp_size) {
  886. pr_err("GP%i partition not HC WP group size "
  887. "aligned\n", pidx+1);
  888. return -EINVAL;
  889. }
  890. gp_size_mult[pidx] = conf->gp_part[pidx].size / mmc->hc_wp_grp_size;
  891. if (conf->gp_part[pidx].size && conf->gp_part[pidx].enhanced) {
  892. part_attrs |= EXT_CSD_ENH_GP(pidx);
  893. tot_enh_size_mult += gp_size_mult[pidx];
  894. }
  895. }
  896. if (part_attrs && ! (mmc->part_support & ENHNCD_SUPPORT)) {
  897. pr_err("Card does not support enhanced attribute\n");
  898. return -EMEDIUMTYPE;
  899. }
  900. err = mmc_send_ext_csd(mmc, ext_csd);
  901. if (err)
  902. return err;
  903. max_enh_size_mult =
  904. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+2] << 16) +
  905. (ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT+1] << 8) +
  906. ext_csd[EXT_CSD_MAX_ENH_SIZE_MULT];
  907. if (tot_enh_size_mult > max_enh_size_mult) {
  908. pr_err("Total enhanced size exceeds maximum (%u > %u)\n",
  909. tot_enh_size_mult, max_enh_size_mult);
  910. return -EMEDIUMTYPE;
  911. }
  912. /* The default value of EXT_CSD_WR_REL_SET is device
  913. * dependent, the values can only be changed if the
  914. * EXT_CSD_HS_CTRL_REL bit is set. The values can be
  915. * changed only once and before partitioning is completed. */
  916. wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  917. if (conf->user.wr_rel_change) {
  918. if (conf->user.wr_rel_set)
  919. wr_rel_set |= EXT_CSD_WR_DATA_REL_USR;
  920. else
  921. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_USR;
  922. }
  923. for (pidx = 0; pidx < 4; pidx++) {
  924. if (conf->gp_part[pidx].wr_rel_change) {
  925. if (conf->gp_part[pidx].wr_rel_set)
  926. wr_rel_set |= EXT_CSD_WR_DATA_REL_GP(pidx);
  927. else
  928. wr_rel_set &= ~EXT_CSD_WR_DATA_REL_GP(pidx);
  929. }
  930. }
  931. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET] &&
  932. !(ext_csd[EXT_CSD_WR_REL_PARAM] & EXT_CSD_HS_CTRL_REL)) {
  933. puts("Card does not support host controlled partition write "
  934. "reliability settings\n");
  935. return -EMEDIUMTYPE;
  936. }
  937. if (ext_csd[EXT_CSD_PARTITION_SETTING] &
  938. EXT_CSD_PARTITION_SETTING_COMPLETED) {
  939. pr_err("Card already partitioned\n");
  940. return -EPERM;
  941. }
  942. if (mode == MMC_HWPART_CONF_CHECK)
  943. return 0;
  944. /* Partitioning requires high-capacity size definitions */
  945. if (!(ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01)) {
  946. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  947. EXT_CSD_ERASE_GROUP_DEF, 1);
  948. if (err)
  949. return err;
  950. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  951. #if CONFIG_IS_ENABLED(MMC_WRITE)
  952. /* update erase group size to be high-capacity */
  953. mmc->erase_grp_size =
  954. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  955. #endif
  956. }
  957. /* all OK, write the configuration */
  958. for (i = 0; i < 4; i++) {
  959. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  960. EXT_CSD_ENH_START_ADDR+i,
  961. (enh_start_addr >> (i*8)) & 0xFF);
  962. if (err)
  963. return err;
  964. }
  965. for (i = 0; i < 3; i++) {
  966. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  967. EXT_CSD_ENH_SIZE_MULT+i,
  968. (enh_size_mult >> (i*8)) & 0xFF);
  969. if (err)
  970. return err;
  971. }
  972. for (pidx = 0; pidx < 4; pidx++) {
  973. for (i = 0; i < 3; i++) {
  974. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  975. EXT_CSD_GP_SIZE_MULT+pidx*3+i,
  976. (gp_size_mult[pidx] >> (i*8)) & 0xFF);
  977. if (err)
  978. return err;
  979. }
  980. }
  981. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  982. EXT_CSD_PARTITIONS_ATTRIBUTE, part_attrs);
  983. if (err)
  984. return err;
  985. if (mode == MMC_HWPART_CONF_SET)
  986. return 0;
  987. /* The WR_REL_SET is a write-once register but shall be
  988. * written before setting PART_SETTING_COMPLETED. As it is
  989. * write-once we can only write it when completing the
  990. * partitioning. */
  991. if (wr_rel_set != ext_csd[EXT_CSD_WR_REL_SET]) {
  992. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  993. EXT_CSD_WR_REL_SET, wr_rel_set);
  994. if (err)
  995. return err;
  996. }
  997. /* Setting PART_SETTING_COMPLETED confirms the partition
  998. * configuration but it only becomes effective after power
  999. * cycle, so we do not adjust the partition related settings
  1000. * in the mmc struct. */
  1001. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1002. EXT_CSD_PARTITION_SETTING,
  1003. EXT_CSD_PARTITION_SETTING_COMPLETED);
  1004. if (err)
  1005. return err;
  1006. return 0;
  1007. }
  1008. #endif
  1009. #if !CONFIG_IS_ENABLED(DM_MMC)
  1010. int mmc_getcd(struct mmc *mmc)
  1011. {
  1012. int cd;
  1013. cd = board_mmc_getcd(mmc);
  1014. if (cd < 0) {
  1015. if (mmc->cfg->ops->getcd)
  1016. cd = mmc->cfg->ops->getcd(mmc);
  1017. else
  1018. cd = 1;
  1019. }
  1020. return cd;
  1021. }
  1022. #endif
  1023. #if !CONFIG_IS_ENABLED(MMC_TINY)
  1024. static int sd_switch(struct mmc *mmc, int mode, int group, u8 value, u8 *resp)
  1025. {
  1026. struct mmc_cmd cmd;
  1027. struct mmc_data data;
  1028. /* Switch the frequency */
  1029. cmd.cmdidx = SD_CMD_SWITCH_FUNC;
  1030. cmd.resp_type = MMC_RSP_R1;
  1031. cmd.cmdarg = (mode << 31) | 0xffffff;
  1032. cmd.cmdarg &= ~(0xf << (group * 4));
  1033. cmd.cmdarg |= value << (group * 4);
  1034. data.dest = (char *)resp;
  1035. data.blocksize = 64;
  1036. data.blocks = 1;
  1037. data.flags = MMC_DATA_READ;
  1038. return mmc_send_cmd(mmc, &cmd, &data);
  1039. }
  1040. static int sd_get_capabilities(struct mmc *mmc)
  1041. {
  1042. int err;
  1043. struct mmc_cmd cmd;
  1044. ALLOC_CACHE_ALIGN_BUFFER(__be32, scr, 2);
  1045. ALLOC_CACHE_ALIGN_BUFFER(__be32, switch_status, 16);
  1046. struct mmc_data data;
  1047. int timeout;
  1048. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1049. u32 sd3_bus_mode;
  1050. #endif
  1051. mmc->card_caps = MMC_MODE_1BIT | MMC_CAP(MMC_LEGACY);
  1052. if (mmc_host_is_spi(mmc))
  1053. return 0;
  1054. /* Read the SCR to find out if this card supports higher speeds */
  1055. cmd.cmdidx = MMC_CMD_APP_CMD;
  1056. cmd.resp_type = MMC_RSP_R1;
  1057. cmd.cmdarg = mmc->rca << 16;
  1058. err = mmc_send_cmd(mmc, &cmd, NULL);
  1059. if (err)
  1060. return err;
  1061. cmd.cmdidx = SD_CMD_APP_SEND_SCR;
  1062. cmd.resp_type = MMC_RSP_R1;
  1063. cmd.cmdarg = 0;
  1064. timeout = 3;
  1065. retry_scr:
  1066. data.dest = (char *)scr;
  1067. data.blocksize = 8;
  1068. data.blocks = 1;
  1069. data.flags = MMC_DATA_READ;
  1070. err = mmc_send_cmd(mmc, &cmd, &data);
  1071. if (err) {
  1072. if (timeout--)
  1073. goto retry_scr;
  1074. return err;
  1075. }
  1076. mmc->scr[0] = __be32_to_cpu(scr[0]);
  1077. mmc->scr[1] = __be32_to_cpu(scr[1]);
  1078. switch ((mmc->scr[0] >> 24) & 0xf) {
  1079. case 0:
  1080. mmc->version = SD_VERSION_1_0;
  1081. break;
  1082. case 1:
  1083. mmc->version = SD_VERSION_1_10;
  1084. break;
  1085. case 2:
  1086. mmc->version = SD_VERSION_2;
  1087. if ((mmc->scr[0] >> 15) & 0x1)
  1088. mmc->version = SD_VERSION_3;
  1089. break;
  1090. default:
  1091. mmc->version = SD_VERSION_1_0;
  1092. break;
  1093. }
  1094. if (mmc->scr[0] & SD_DATA_4BIT)
  1095. mmc->card_caps |= MMC_MODE_4BIT;
  1096. /* Version 1.0 doesn't support switching */
  1097. if (mmc->version == SD_VERSION_1_0)
  1098. return 0;
  1099. timeout = 4;
  1100. while (timeout--) {
  1101. err = sd_switch(mmc, SD_SWITCH_CHECK, 0, 1,
  1102. (u8 *)switch_status);
  1103. if (err)
  1104. return err;
  1105. /* The high-speed function is busy. Try again */
  1106. if (!(__be32_to_cpu(switch_status[7]) & SD_HIGHSPEED_BUSY))
  1107. break;
  1108. }
  1109. /* If high-speed isn't supported, we return */
  1110. if (__be32_to_cpu(switch_status[3]) & SD_HIGHSPEED_SUPPORTED)
  1111. mmc->card_caps |= MMC_CAP(SD_HS);
  1112. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1113. /* Version before 3.0 don't support UHS modes */
  1114. if (mmc->version < SD_VERSION_3)
  1115. return 0;
  1116. sd3_bus_mode = __be32_to_cpu(switch_status[3]) >> 16 & 0x1f;
  1117. if (sd3_bus_mode & SD_MODE_UHS_SDR104)
  1118. mmc->card_caps |= MMC_CAP(UHS_SDR104);
  1119. if (sd3_bus_mode & SD_MODE_UHS_SDR50)
  1120. mmc->card_caps |= MMC_CAP(UHS_SDR50);
  1121. if (sd3_bus_mode & SD_MODE_UHS_SDR25)
  1122. mmc->card_caps |= MMC_CAP(UHS_SDR25);
  1123. if (sd3_bus_mode & SD_MODE_UHS_SDR12)
  1124. mmc->card_caps |= MMC_CAP(UHS_SDR12);
  1125. if (sd3_bus_mode & SD_MODE_UHS_DDR50)
  1126. mmc->card_caps |= MMC_CAP(UHS_DDR50);
  1127. #endif
  1128. return 0;
  1129. }
  1130. static int sd_set_card_speed(struct mmc *mmc, enum bus_mode mode)
  1131. {
  1132. int err;
  1133. ALLOC_CACHE_ALIGN_BUFFER(uint, switch_status, 16);
  1134. int speed;
  1135. /* SD version 1.00 and 1.01 does not support CMD 6 */
  1136. if (mmc->version == SD_VERSION_1_0)
  1137. return 0;
  1138. switch (mode) {
  1139. case MMC_LEGACY:
  1140. speed = UHS_SDR12_BUS_SPEED;
  1141. break;
  1142. case SD_HS:
  1143. speed = HIGH_SPEED_BUS_SPEED;
  1144. break;
  1145. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1146. case UHS_SDR12:
  1147. speed = UHS_SDR12_BUS_SPEED;
  1148. break;
  1149. case UHS_SDR25:
  1150. speed = UHS_SDR25_BUS_SPEED;
  1151. break;
  1152. case UHS_SDR50:
  1153. speed = UHS_SDR50_BUS_SPEED;
  1154. break;
  1155. case UHS_DDR50:
  1156. speed = UHS_DDR50_BUS_SPEED;
  1157. break;
  1158. case UHS_SDR104:
  1159. speed = UHS_SDR104_BUS_SPEED;
  1160. break;
  1161. #endif
  1162. default:
  1163. return -EINVAL;
  1164. }
  1165. err = sd_switch(mmc, SD_SWITCH_SWITCH, 0, speed, (u8 *)switch_status);
  1166. if (err)
  1167. return err;
  1168. if (((__be32_to_cpu(switch_status[4]) >> 24) & 0xF) != speed)
  1169. return -ENOTSUPP;
  1170. return 0;
  1171. }
  1172. static int sd_select_bus_width(struct mmc *mmc, int w)
  1173. {
  1174. int err;
  1175. struct mmc_cmd cmd;
  1176. if ((w != 4) && (w != 1))
  1177. return -EINVAL;
  1178. cmd.cmdidx = MMC_CMD_APP_CMD;
  1179. cmd.resp_type = MMC_RSP_R1;
  1180. cmd.cmdarg = mmc->rca << 16;
  1181. err = mmc_send_cmd(mmc, &cmd, NULL);
  1182. if (err)
  1183. return err;
  1184. cmd.cmdidx = SD_CMD_APP_SET_BUS_WIDTH;
  1185. cmd.resp_type = MMC_RSP_R1;
  1186. if (w == 4)
  1187. cmd.cmdarg = 2;
  1188. else if (w == 1)
  1189. cmd.cmdarg = 0;
  1190. err = mmc_send_cmd(mmc, &cmd, NULL);
  1191. if (err)
  1192. return err;
  1193. return 0;
  1194. }
  1195. #endif
  1196. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1197. static int sd_read_ssr(struct mmc *mmc)
  1198. {
  1199. static const unsigned int sd_au_size[] = {
  1200. 0, SZ_16K / 512, SZ_32K / 512,
  1201. SZ_64K / 512, SZ_128K / 512, SZ_256K / 512,
  1202. SZ_512K / 512, SZ_1M / 512, SZ_2M / 512,
  1203. SZ_4M / 512, SZ_8M / 512, (SZ_8M + SZ_4M) / 512,
  1204. SZ_16M / 512, (SZ_16M + SZ_8M) / 512, SZ_32M / 512,
  1205. SZ_64M / 512,
  1206. };
  1207. int err, i;
  1208. struct mmc_cmd cmd;
  1209. ALLOC_CACHE_ALIGN_BUFFER(uint, ssr, 16);
  1210. struct mmc_data data;
  1211. int timeout = 3;
  1212. unsigned int au, eo, et, es;
  1213. cmd.cmdidx = MMC_CMD_APP_CMD;
  1214. cmd.resp_type = MMC_RSP_R1;
  1215. cmd.cmdarg = mmc->rca << 16;
  1216. err = mmc_send_cmd(mmc, &cmd, NULL);
  1217. #ifdef CONFIG_MMC_QUIRKS
  1218. if (err && (mmc->quirks & MMC_QUIRK_RETRY_APP_CMD)) {
  1219. int retries = 4;
  1220. /*
  1221. * It has been seen that APP_CMD may fail on the first
  1222. * attempt, let's try a few more times
  1223. */
  1224. do {
  1225. err = mmc_send_cmd(mmc, &cmd, NULL);
  1226. if (!err)
  1227. break;
  1228. } while (retries--);
  1229. }
  1230. #endif
  1231. if (err)
  1232. return err;
  1233. cmd.cmdidx = SD_CMD_APP_SD_STATUS;
  1234. cmd.resp_type = MMC_RSP_R1;
  1235. cmd.cmdarg = 0;
  1236. retry_ssr:
  1237. data.dest = (char *)ssr;
  1238. data.blocksize = 64;
  1239. data.blocks = 1;
  1240. data.flags = MMC_DATA_READ;
  1241. err = mmc_send_cmd(mmc, &cmd, &data);
  1242. if (err) {
  1243. if (timeout--)
  1244. goto retry_ssr;
  1245. return err;
  1246. }
  1247. for (i = 0; i < 16; i++)
  1248. ssr[i] = be32_to_cpu(ssr[i]);
  1249. au = (ssr[2] >> 12) & 0xF;
  1250. if ((au <= 9) || (mmc->version == SD_VERSION_3)) {
  1251. mmc->ssr.au = sd_au_size[au];
  1252. es = (ssr[3] >> 24) & 0xFF;
  1253. es |= (ssr[2] & 0xFF) << 8;
  1254. et = (ssr[3] >> 18) & 0x3F;
  1255. if (es && et) {
  1256. eo = (ssr[3] >> 16) & 0x3;
  1257. mmc->ssr.erase_timeout = (et * 1000) / es;
  1258. mmc->ssr.erase_offset = eo * 1000;
  1259. }
  1260. } else {
  1261. pr_debug("Invalid Allocation Unit Size.\n");
  1262. }
  1263. return 0;
  1264. }
  1265. #endif
  1266. /* frequency bases */
  1267. /* divided by 10 to be nice to platforms without floating point */
  1268. static const int fbase[] = {
  1269. 10000,
  1270. 100000,
  1271. 1000000,
  1272. 10000000,
  1273. };
  1274. /* Multiplier values for TRAN_SPEED. Multiplied by 10 to be nice
  1275. * to platforms without floating point.
  1276. */
  1277. static const u8 multipliers[] = {
  1278. 0, /* reserved */
  1279. 10,
  1280. 12,
  1281. 13,
  1282. 15,
  1283. 20,
  1284. 25,
  1285. 30,
  1286. 35,
  1287. 40,
  1288. 45,
  1289. 50,
  1290. 55,
  1291. 60,
  1292. 70,
  1293. 80,
  1294. };
  1295. static inline int bus_width(uint cap)
  1296. {
  1297. if (cap == MMC_MODE_8BIT)
  1298. return 8;
  1299. if (cap == MMC_MODE_4BIT)
  1300. return 4;
  1301. if (cap == MMC_MODE_1BIT)
  1302. return 1;
  1303. pr_warn("invalid bus witdh capability 0x%x\n", cap);
  1304. return 0;
  1305. }
  1306. #if !CONFIG_IS_ENABLED(DM_MMC)
  1307. #ifdef MMC_SUPPORTS_TUNING
  1308. static int mmc_execute_tuning(struct mmc *mmc, uint opcode)
  1309. {
  1310. return -ENOTSUPP;
  1311. }
  1312. #endif
  1313. static int mmc_set_ios(struct mmc *mmc)
  1314. {
  1315. int ret = 0;
  1316. if (mmc->cfg->ops->set_ios)
  1317. ret = mmc->cfg->ops->set_ios(mmc);
  1318. return ret;
  1319. }
  1320. static int mmc_host_power_cycle(struct mmc *mmc)
  1321. {
  1322. int ret = 0;
  1323. if (mmc->cfg->ops->host_power_cycle)
  1324. ret = mmc->cfg->ops->host_power_cycle(mmc);
  1325. return ret;
  1326. }
  1327. #endif
  1328. int mmc_set_clock(struct mmc *mmc, uint clock, bool disable)
  1329. {
  1330. if (!disable) {
  1331. if (clock > mmc->cfg->f_max)
  1332. clock = mmc->cfg->f_max;
  1333. if (clock < mmc->cfg->f_min)
  1334. clock = mmc->cfg->f_min;
  1335. }
  1336. mmc->clock = clock;
  1337. mmc->clk_disable = disable;
  1338. debug("clock is %s (%dHz)\n", disable ? "disabled" : "enabled", clock);
  1339. return mmc_set_ios(mmc);
  1340. }
  1341. static int mmc_set_bus_width(struct mmc *mmc, uint width)
  1342. {
  1343. mmc->bus_width = width;
  1344. return mmc_set_ios(mmc);
  1345. }
  1346. #if CONFIG_IS_ENABLED(MMC_VERBOSE) || defined(DEBUG)
  1347. /*
  1348. * helper function to display the capabilities in a human
  1349. * friendly manner. The capabilities include bus width and
  1350. * supported modes.
  1351. */
  1352. void mmc_dump_capabilities(const char *text, uint caps)
  1353. {
  1354. enum bus_mode mode;
  1355. pr_debug("%s: widths [", text);
  1356. if (caps & MMC_MODE_8BIT)
  1357. pr_debug("8, ");
  1358. if (caps & MMC_MODE_4BIT)
  1359. pr_debug("4, ");
  1360. if (caps & MMC_MODE_1BIT)
  1361. pr_debug("1, ");
  1362. pr_debug("\b\b] modes [");
  1363. for (mode = MMC_LEGACY; mode < MMC_MODES_END; mode++)
  1364. if (MMC_CAP(mode) & caps)
  1365. pr_debug("%s, ", mmc_mode_name(mode));
  1366. pr_debug("\b\b]\n");
  1367. }
  1368. #endif
  1369. struct mode_width_tuning {
  1370. enum bus_mode mode;
  1371. uint widths;
  1372. #ifdef MMC_SUPPORTS_TUNING
  1373. uint tuning;
  1374. #endif
  1375. };
  1376. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1377. int mmc_voltage_to_mv(enum mmc_voltage voltage)
  1378. {
  1379. switch (voltage) {
  1380. case MMC_SIGNAL_VOLTAGE_000: return 0;
  1381. case MMC_SIGNAL_VOLTAGE_330: return 3300;
  1382. case MMC_SIGNAL_VOLTAGE_180: return 1800;
  1383. case MMC_SIGNAL_VOLTAGE_120: return 1200;
  1384. }
  1385. return -EINVAL;
  1386. }
  1387. static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
  1388. {
  1389. int err;
  1390. if (mmc->signal_voltage == signal_voltage)
  1391. return 0;
  1392. mmc->signal_voltage = signal_voltage;
  1393. err = mmc_set_ios(mmc);
  1394. if (err)
  1395. pr_debug("unable to set voltage (err %d)\n", err);
  1396. return err;
  1397. }
  1398. #else
  1399. static inline int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage)
  1400. {
  1401. return 0;
  1402. }
  1403. #endif
  1404. #if !CONFIG_IS_ENABLED(MMC_TINY)
  1405. static const struct mode_width_tuning sd_modes_by_pref[] = {
  1406. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1407. #ifdef MMC_SUPPORTS_TUNING
  1408. {
  1409. .mode = UHS_SDR104,
  1410. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1411. .tuning = MMC_CMD_SEND_TUNING_BLOCK
  1412. },
  1413. #endif
  1414. {
  1415. .mode = UHS_SDR50,
  1416. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1417. },
  1418. {
  1419. .mode = UHS_DDR50,
  1420. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1421. },
  1422. {
  1423. .mode = UHS_SDR25,
  1424. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1425. },
  1426. #endif
  1427. {
  1428. .mode = SD_HS,
  1429. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1430. },
  1431. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1432. {
  1433. .mode = UHS_SDR12,
  1434. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1435. },
  1436. #endif
  1437. {
  1438. .mode = MMC_LEGACY,
  1439. .widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
  1440. }
  1441. };
  1442. #define for_each_sd_mode_by_pref(caps, mwt) \
  1443. for (mwt = sd_modes_by_pref;\
  1444. mwt < sd_modes_by_pref + ARRAY_SIZE(sd_modes_by_pref);\
  1445. mwt++) \
  1446. if (caps & MMC_CAP(mwt->mode))
  1447. static int sd_select_mode_and_width(struct mmc *mmc, uint card_caps)
  1448. {
  1449. int err;
  1450. uint widths[] = {MMC_MODE_4BIT, MMC_MODE_1BIT};
  1451. const struct mode_width_tuning *mwt;
  1452. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  1453. bool uhs_en = (mmc->ocr & OCR_S18R) ? true : false;
  1454. #else
  1455. bool uhs_en = false;
  1456. #endif
  1457. uint caps;
  1458. #ifdef DEBUG
  1459. mmc_dump_capabilities("sd card", card_caps);
  1460. mmc_dump_capabilities("host", mmc->host_caps);
  1461. #endif
  1462. if (mmc_host_is_spi(mmc)) {
  1463. mmc_set_bus_width(mmc, 1);
  1464. mmc_select_mode(mmc, MMC_LEGACY);
  1465. mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
  1466. return 0;
  1467. }
  1468. /* Restrict card's capabilities by what the host can do */
  1469. caps = card_caps & mmc->host_caps;
  1470. if (!uhs_en)
  1471. caps &= ~UHS_CAPS;
  1472. for_each_sd_mode_by_pref(caps, mwt) {
  1473. uint *w;
  1474. for (w = widths; w < widths + ARRAY_SIZE(widths); w++) {
  1475. if (*w & caps & mwt->widths) {
  1476. pr_debug("trying mode %s width %d (at %d MHz)\n",
  1477. mmc_mode_name(mwt->mode),
  1478. bus_width(*w),
  1479. mmc_mode2freq(mmc, mwt->mode) / 1000000);
  1480. /* configure the bus width (card + host) */
  1481. err = sd_select_bus_width(mmc, bus_width(*w));
  1482. if (err)
  1483. goto error;
  1484. mmc_set_bus_width(mmc, bus_width(*w));
  1485. /* configure the bus mode (card) */
  1486. err = sd_set_card_speed(mmc, mwt->mode);
  1487. if (err)
  1488. goto error;
  1489. /* configure the bus mode (host) */
  1490. mmc_select_mode(mmc, mwt->mode);
  1491. mmc_set_clock(mmc, mmc->tran_speed,
  1492. MMC_CLK_ENABLE);
  1493. #ifdef MMC_SUPPORTS_TUNING
  1494. /* execute tuning if needed */
  1495. if (mwt->tuning && !mmc_host_is_spi(mmc)) {
  1496. err = mmc_execute_tuning(mmc,
  1497. mwt->tuning);
  1498. if (err) {
  1499. pr_debug("tuning failed\n");
  1500. goto error;
  1501. }
  1502. }
  1503. #endif
  1504. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1505. err = sd_read_ssr(mmc);
  1506. if (err)
  1507. pr_warn("unable to read ssr\n");
  1508. #endif
  1509. if (!err)
  1510. return 0;
  1511. error:
  1512. /* revert to a safer bus speed */
  1513. mmc_select_mode(mmc, MMC_LEGACY);
  1514. mmc_set_clock(mmc, mmc->tran_speed,
  1515. MMC_CLK_ENABLE);
  1516. }
  1517. }
  1518. }
  1519. pr_err("unable to select a mode\n");
  1520. return -ENOTSUPP;
  1521. }
  1522. /*
  1523. * read the compare the part of ext csd that is constant.
  1524. * This can be used to check that the transfer is working
  1525. * as expected.
  1526. */
  1527. static int mmc_read_and_compare_ext_csd(struct mmc *mmc)
  1528. {
  1529. int err;
  1530. const u8 *ext_csd = mmc->ext_csd;
  1531. ALLOC_CACHE_ALIGN_BUFFER(u8, test_csd, MMC_MAX_BLOCK_LEN);
  1532. if (mmc->version < MMC_VERSION_4)
  1533. return 0;
  1534. err = mmc_send_ext_csd(mmc, test_csd);
  1535. if (err)
  1536. return err;
  1537. /* Only compare read only fields */
  1538. if (ext_csd[EXT_CSD_PARTITIONING_SUPPORT]
  1539. == test_csd[EXT_CSD_PARTITIONING_SUPPORT] &&
  1540. ext_csd[EXT_CSD_HC_WP_GRP_SIZE]
  1541. == test_csd[EXT_CSD_HC_WP_GRP_SIZE] &&
  1542. ext_csd[EXT_CSD_REV]
  1543. == test_csd[EXT_CSD_REV] &&
  1544. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  1545. == test_csd[EXT_CSD_HC_ERASE_GRP_SIZE] &&
  1546. memcmp(&ext_csd[EXT_CSD_SEC_CNT],
  1547. &test_csd[EXT_CSD_SEC_CNT], 4) == 0)
  1548. return 0;
  1549. return -EBADMSG;
  1550. }
  1551. #if CONFIG_IS_ENABLED(MMC_IO_VOLTAGE)
  1552. static int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
  1553. uint32_t allowed_mask)
  1554. {
  1555. u32 card_mask = 0;
  1556. switch (mode) {
  1557. case MMC_HS_400_ES:
  1558. case MMC_HS_400:
  1559. case MMC_HS_200:
  1560. if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_8V |
  1561. EXT_CSD_CARD_TYPE_HS400_1_8V))
  1562. card_mask |= MMC_SIGNAL_VOLTAGE_180;
  1563. if (mmc->cardtype & (EXT_CSD_CARD_TYPE_HS200_1_2V |
  1564. EXT_CSD_CARD_TYPE_HS400_1_2V))
  1565. card_mask |= MMC_SIGNAL_VOLTAGE_120;
  1566. break;
  1567. case MMC_DDR_52:
  1568. if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_8V)
  1569. card_mask |= MMC_SIGNAL_VOLTAGE_330 |
  1570. MMC_SIGNAL_VOLTAGE_180;
  1571. if (mmc->cardtype & EXT_CSD_CARD_TYPE_DDR_1_2V)
  1572. card_mask |= MMC_SIGNAL_VOLTAGE_120;
  1573. break;
  1574. default:
  1575. card_mask |= MMC_SIGNAL_VOLTAGE_330;
  1576. break;
  1577. }
  1578. while (card_mask & allowed_mask) {
  1579. enum mmc_voltage best_match;
  1580. best_match = 1 << (ffs(card_mask & allowed_mask) - 1);
  1581. if (!mmc_set_signal_voltage(mmc, best_match))
  1582. return 0;
  1583. allowed_mask &= ~best_match;
  1584. }
  1585. return -ENOTSUPP;
  1586. }
  1587. #else
  1588. static inline int mmc_set_lowest_voltage(struct mmc *mmc, enum bus_mode mode,
  1589. uint32_t allowed_mask)
  1590. {
  1591. return 0;
  1592. }
  1593. #endif
  1594. static const struct mode_width_tuning mmc_modes_by_pref[] = {
  1595. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1596. {
  1597. .mode = MMC_HS_400_ES,
  1598. .widths = MMC_MODE_8BIT,
  1599. },
  1600. #endif
  1601. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  1602. {
  1603. .mode = MMC_HS_400,
  1604. .widths = MMC_MODE_8BIT,
  1605. .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
  1606. },
  1607. #endif
  1608. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  1609. {
  1610. .mode = MMC_HS_200,
  1611. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
  1612. .tuning = MMC_CMD_SEND_TUNING_BLOCK_HS200
  1613. },
  1614. #endif
  1615. {
  1616. .mode = MMC_DDR_52,
  1617. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT,
  1618. },
  1619. {
  1620. .mode = MMC_HS_52,
  1621. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1622. },
  1623. {
  1624. .mode = MMC_HS,
  1625. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1626. },
  1627. {
  1628. .mode = MMC_LEGACY,
  1629. .widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
  1630. }
  1631. };
  1632. #define for_each_mmc_mode_by_pref(caps, mwt) \
  1633. for (mwt = mmc_modes_by_pref;\
  1634. mwt < mmc_modes_by_pref + ARRAY_SIZE(mmc_modes_by_pref);\
  1635. mwt++) \
  1636. if (caps & MMC_CAP(mwt->mode))
  1637. static const struct ext_csd_bus_width {
  1638. uint cap;
  1639. bool is_ddr;
  1640. uint ext_csd_bits;
  1641. } ext_csd_bus_width[] = {
  1642. {MMC_MODE_8BIT, true, EXT_CSD_DDR_BUS_WIDTH_8},
  1643. {MMC_MODE_4BIT, true, EXT_CSD_DDR_BUS_WIDTH_4},
  1644. {MMC_MODE_8BIT, false, EXT_CSD_BUS_WIDTH_8},
  1645. {MMC_MODE_4BIT, false, EXT_CSD_BUS_WIDTH_4},
  1646. {MMC_MODE_1BIT, false, EXT_CSD_BUS_WIDTH_1},
  1647. };
  1648. #if CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  1649. static int mmc_select_hs400(struct mmc *mmc)
  1650. {
  1651. int err;
  1652. /* Set timing to HS200 for tuning */
  1653. err = mmc_set_card_speed(mmc, MMC_HS_200, false);
  1654. if (err)
  1655. return err;
  1656. /* configure the bus mode (host) */
  1657. mmc_select_mode(mmc, MMC_HS_200);
  1658. mmc_set_clock(mmc, mmc->tran_speed, false);
  1659. /* execute tuning if needed */
  1660. err = mmc_execute_tuning(mmc, MMC_CMD_SEND_TUNING_BLOCK_HS200);
  1661. if (err) {
  1662. debug("tuning failed\n");
  1663. return err;
  1664. }
  1665. /* Set back to HS */
  1666. mmc_set_card_speed(mmc, MMC_HS, true);
  1667. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
  1668. EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG);
  1669. if (err)
  1670. return err;
  1671. err = mmc_set_card_speed(mmc, MMC_HS_400, false);
  1672. if (err)
  1673. return err;
  1674. mmc_select_mode(mmc, MMC_HS_400);
  1675. err = mmc_set_clock(mmc, mmc->tran_speed, false);
  1676. if (err)
  1677. return err;
  1678. return 0;
  1679. }
  1680. #else
  1681. static int mmc_select_hs400(struct mmc *mmc)
  1682. {
  1683. return -ENOTSUPP;
  1684. }
  1685. #endif
  1686. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1687. #if !CONFIG_IS_ENABLED(DM_MMC)
  1688. static int mmc_set_enhanced_strobe(struct mmc *mmc)
  1689. {
  1690. return -ENOTSUPP;
  1691. }
  1692. #endif
  1693. static int mmc_select_hs400es(struct mmc *mmc)
  1694. {
  1695. int err;
  1696. err = mmc_set_card_speed(mmc, MMC_HS, true);
  1697. if (err)
  1698. return err;
  1699. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
  1700. EXT_CSD_BUS_WIDTH_8 | EXT_CSD_DDR_FLAG |
  1701. EXT_CSD_BUS_WIDTH_STROBE);
  1702. if (err) {
  1703. printf("switch to bus width for hs400 failed\n");
  1704. return err;
  1705. }
  1706. /* TODO: driver strength */
  1707. err = mmc_set_card_speed(mmc, MMC_HS_400_ES, false);
  1708. if (err)
  1709. return err;
  1710. mmc_select_mode(mmc, MMC_HS_400_ES);
  1711. err = mmc_set_clock(mmc, mmc->tran_speed, false);
  1712. if (err)
  1713. return err;
  1714. return mmc_set_enhanced_strobe(mmc);
  1715. }
  1716. #else
  1717. static int mmc_select_hs400es(struct mmc *mmc)
  1718. {
  1719. return -ENOTSUPP;
  1720. }
  1721. #endif
  1722. #define for_each_supported_width(caps, ddr, ecbv) \
  1723. for (ecbv = ext_csd_bus_width;\
  1724. ecbv < ext_csd_bus_width + ARRAY_SIZE(ext_csd_bus_width);\
  1725. ecbv++) \
  1726. if ((ddr == ecbv->is_ddr) && (caps & ecbv->cap))
  1727. static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
  1728. {
  1729. int err;
  1730. const struct mode_width_tuning *mwt;
  1731. const struct ext_csd_bus_width *ecbw;
  1732. #ifdef DEBUG
  1733. mmc_dump_capabilities("mmc", card_caps);
  1734. mmc_dump_capabilities("host", mmc->host_caps);
  1735. #endif
  1736. if (mmc_host_is_spi(mmc)) {
  1737. mmc_set_bus_width(mmc, 1);
  1738. mmc_select_mode(mmc, MMC_LEGACY);
  1739. mmc_set_clock(mmc, mmc->tran_speed, MMC_CLK_ENABLE);
  1740. return 0;
  1741. }
  1742. /* Restrict card's capabilities by what the host can do */
  1743. card_caps &= mmc->host_caps;
  1744. /* Only version 4 of MMC supports wider bus widths */
  1745. if (mmc->version < MMC_VERSION_4)
  1746. return 0;
  1747. if (!mmc->ext_csd) {
  1748. pr_debug("No ext_csd found!\n"); /* this should enver happen */
  1749. return -ENOTSUPP;
  1750. }
  1751. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  1752. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  1753. /*
  1754. * In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
  1755. * before doing anything else, since a transition from either of
  1756. * the HS200/HS400 mode directly to legacy mode is not supported.
  1757. */
  1758. if (mmc->selected_mode == MMC_HS_200 ||
  1759. mmc->selected_mode == MMC_HS_400)
  1760. mmc_set_card_speed(mmc, MMC_HS, true);
  1761. else
  1762. #endif
  1763. mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
  1764. for_each_mmc_mode_by_pref(card_caps, mwt) {
  1765. for_each_supported_width(card_caps & mwt->widths,
  1766. mmc_is_mode_ddr(mwt->mode), ecbw) {
  1767. enum mmc_voltage old_voltage;
  1768. pr_debug("trying mode %s width %d (at %d MHz)\n",
  1769. mmc_mode_name(mwt->mode),
  1770. bus_width(ecbw->cap),
  1771. mmc_mode2freq(mmc, mwt->mode) / 1000000);
  1772. old_voltage = mmc->signal_voltage;
  1773. err = mmc_set_lowest_voltage(mmc, mwt->mode,
  1774. MMC_ALL_SIGNAL_VOLTAGE);
  1775. if (err)
  1776. continue;
  1777. /* configure the bus width (card + host) */
  1778. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1779. EXT_CSD_BUS_WIDTH,
  1780. ecbw->ext_csd_bits & ~EXT_CSD_DDR_FLAG);
  1781. if (err)
  1782. goto error;
  1783. mmc_set_bus_width(mmc, bus_width(ecbw->cap));
  1784. if (mwt->mode == MMC_HS_400) {
  1785. err = mmc_select_hs400(mmc);
  1786. if (err) {
  1787. printf("Select HS400 failed %d\n", err);
  1788. goto error;
  1789. }
  1790. } else if (mwt->mode == MMC_HS_400_ES) {
  1791. err = mmc_select_hs400es(mmc);
  1792. if (err) {
  1793. printf("Select HS400ES failed %d\n",
  1794. err);
  1795. goto error;
  1796. }
  1797. } else {
  1798. /* configure the bus speed (card) */
  1799. err = mmc_set_card_speed(mmc, mwt->mode, false);
  1800. if (err)
  1801. goto error;
  1802. /*
  1803. * configure the bus width AND the ddr mode
  1804. * (card). The host side will be taken care
  1805. * of in the next step
  1806. */
  1807. if (ecbw->ext_csd_bits & EXT_CSD_DDR_FLAG) {
  1808. err = mmc_switch(mmc,
  1809. EXT_CSD_CMD_SET_NORMAL,
  1810. EXT_CSD_BUS_WIDTH,
  1811. ecbw->ext_csd_bits);
  1812. if (err)
  1813. goto error;
  1814. }
  1815. /* configure the bus mode (host) */
  1816. mmc_select_mode(mmc, mwt->mode);
  1817. mmc_set_clock(mmc, mmc->tran_speed,
  1818. MMC_CLK_ENABLE);
  1819. #ifdef MMC_SUPPORTS_TUNING
  1820. /* execute tuning if needed */
  1821. if (mwt->tuning) {
  1822. err = mmc_execute_tuning(mmc,
  1823. mwt->tuning);
  1824. if (err) {
  1825. pr_debug("tuning failed\n");
  1826. goto error;
  1827. }
  1828. }
  1829. #endif
  1830. }
  1831. /* do a transfer to check the configuration */
  1832. err = mmc_read_and_compare_ext_csd(mmc);
  1833. if (!err)
  1834. return 0;
  1835. error:
  1836. mmc_set_signal_voltage(mmc, old_voltage);
  1837. /* if an error occured, revert to a safer bus mode */
  1838. mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1839. EXT_CSD_BUS_WIDTH, EXT_CSD_BUS_WIDTH_1);
  1840. mmc_select_mode(mmc, MMC_LEGACY);
  1841. mmc_set_bus_width(mmc, 1);
  1842. }
  1843. }
  1844. pr_err("unable to select a mode\n");
  1845. return -ENOTSUPP;
  1846. }
  1847. #endif
  1848. #if CONFIG_IS_ENABLED(MMC_TINY)
  1849. DEFINE_CACHE_ALIGN_BUFFER(u8, ext_csd_bkup, MMC_MAX_BLOCK_LEN);
  1850. #endif
  1851. static int mmc_startup_v4(struct mmc *mmc)
  1852. {
  1853. int err, i;
  1854. u64 capacity;
  1855. bool has_parts = false;
  1856. bool part_completed;
  1857. static const u32 mmc_versions[] = {
  1858. MMC_VERSION_4,
  1859. MMC_VERSION_4_1,
  1860. MMC_VERSION_4_2,
  1861. MMC_VERSION_4_3,
  1862. MMC_VERSION_4_4,
  1863. MMC_VERSION_4_41,
  1864. MMC_VERSION_4_5,
  1865. MMC_VERSION_5_0,
  1866. MMC_VERSION_5_1
  1867. };
  1868. #if CONFIG_IS_ENABLED(MMC_TINY)
  1869. u8 *ext_csd = ext_csd_bkup;
  1870. if (IS_SD(mmc) || mmc->version < MMC_VERSION_4)
  1871. return 0;
  1872. if (!mmc->ext_csd)
  1873. memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup));
  1874. err = mmc_send_ext_csd(mmc, ext_csd);
  1875. if (err)
  1876. goto error;
  1877. /* store the ext csd for future reference */
  1878. if (!mmc->ext_csd)
  1879. mmc->ext_csd = ext_csd;
  1880. #else
  1881. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  1882. if (IS_SD(mmc) || (mmc->version < MMC_VERSION_4))
  1883. return 0;
  1884. /* check ext_csd version and capacity */
  1885. err = mmc_send_ext_csd(mmc, ext_csd);
  1886. if (err)
  1887. goto error;
  1888. /* store the ext csd for future reference */
  1889. if (!mmc->ext_csd)
  1890. mmc->ext_csd = malloc(MMC_MAX_BLOCK_LEN);
  1891. if (!mmc->ext_csd)
  1892. return -ENOMEM;
  1893. memcpy(mmc->ext_csd, ext_csd, MMC_MAX_BLOCK_LEN);
  1894. #endif
  1895. if (ext_csd[EXT_CSD_REV] >= ARRAY_SIZE(mmc_versions))
  1896. return -EINVAL;
  1897. mmc->version = mmc_versions[ext_csd[EXT_CSD_REV]];
  1898. if (mmc->version >= MMC_VERSION_4_2) {
  1899. /*
  1900. * According to the JEDEC Standard, the value of
  1901. * ext_csd's capacity is valid if the value is more
  1902. * than 2GB
  1903. */
  1904. capacity = ext_csd[EXT_CSD_SEC_CNT] << 0
  1905. | ext_csd[EXT_CSD_SEC_CNT + 1] << 8
  1906. | ext_csd[EXT_CSD_SEC_CNT + 2] << 16
  1907. | ext_csd[EXT_CSD_SEC_CNT + 3] << 24;
  1908. capacity *= MMC_MAX_BLOCK_LEN;
  1909. if ((capacity >> 20) > 2 * 1024)
  1910. mmc->capacity_user = capacity;
  1911. }
  1912. if (mmc->version >= MMC_VERSION_4_5)
  1913. mmc->gen_cmd6_time = ext_csd[EXT_CSD_GENERIC_CMD6_TIME];
  1914. /* The partition data may be non-zero but it is only
  1915. * effective if PARTITION_SETTING_COMPLETED is set in
  1916. * EXT_CSD, so ignore any data if this bit is not set,
  1917. * except for enabling the high-capacity group size
  1918. * definition (see below).
  1919. */
  1920. part_completed = !!(ext_csd[EXT_CSD_PARTITION_SETTING] &
  1921. EXT_CSD_PARTITION_SETTING_COMPLETED);
  1922. mmc->part_switch_time = ext_csd[EXT_CSD_PART_SWITCH_TIME];
  1923. /* Some eMMC set the value too low so set a minimum */
  1924. if (mmc->part_switch_time < MMC_MIN_PART_SWITCH_TIME && mmc->part_switch_time)
  1925. mmc->part_switch_time = MMC_MIN_PART_SWITCH_TIME;
  1926. /* store the partition info of emmc */
  1927. mmc->part_support = ext_csd[EXT_CSD_PARTITIONING_SUPPORT];
  1928. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) ||
  1929. ext_csd[EXT_CSD_BOOT_MULT])
  1930. mmc->part_config = ext_csd[EXT_CSD_PART_CONF];
  1931. if (part_completed &&
  1932. (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & ENHNCD_SUPPORT))
  1933. mmc->part_attr = ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE];
  1934. mmc->capacity_boot = ext_csd[EXT_CSD_BOOT_MULT] << 17;
  1935. mmc->capacity_rpmb = ext_csd[EXT_CSD_RPMB_MULT] << 17;
  1936. for (i = 0; i < 4; i++) {
  1937. int idx = EXT_CSD_GP_SIZE_MULT + i * 3;
  1938. uint mult = (ext_csd[idx + 2] << 16) +
  1939. (ext_csd[idx + 1] << 8) + ext_csd[idx];
  1940. if (mult)
  1941. has_parts = true;
  1942. if (!part_completed)
  1943. continue;
  1944. mmc->capacity_gp[i] = mult;
  1945. mmc->capacity_gp[i] *=
  1946. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1947. mmc->capacity_gp[i] *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1948. mmc->capacity_gp[i] <<= 19;
  1949. }
  1950. #ifndef CONFIG_SPL_BUILD
  1951. if (part_completed) {
  1952. mmc->enh_user_size =
  1953. (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16) +
  1954. (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) +
  1955. ext_csd[EXT_CSD_ENH_SIZE_MULT];
  1956. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE];
  1957. mmc->enh_user_size *= ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  1958. mmc->enh_user_size <<= 19;
  1959. mmc->enh_user_start =
  1960. (ext_csd[EXT_CSD_ENH_START_ADDR + 3] << 24) +
  1961. (ext_csd[EXT_CSD_ENH_START_ADDR + 2] << 16) +
  1962. (ext_csd[EXT_CSD_ENH_START_ADDR + 1] << 8) +
  1963. ext_csd[EXT_CSD_ENH_START_ADDR];
  1964. if (mmc->high_capacity)
  1965. mmc->enh_user_start <<= 9;
  1966. }
  1967. #endif
  1968. /*
  1969. * Host needs to enable ERASE_GRP_DEF bit if device is
  1970. * partitioned. This bit will be lost every time after a reset
  1971. * or power off. This will affect erase size.
  1972. */
  1973. if (part_completed)
  1974. has_parts = true;
  1975. if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & PART_SUPPORT) &&
  1976. (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & PART_ENH_ATTRIB))
  1977. has_parts = true;
  1978. if (has_parts) {
  1979. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
  1980. EXT_CSD_ERASE_GROUP_DEF, 1);
  1981. if (err)
  1982. goto error;
  1983. ext_csd[EXT_CSD_ERASE_GROUP_DEF] = 1;
  1984. }
  1985. if (ext_csd[EXT_CSD_ERASE_GROUP_DEF] & 0x01) {
  1986. #if CONFIG_IS_ENABLED(MMC_WRITE)
  1987. /* Read out group size from ext_csd */
  1988. mmc->erase_grp_size =
  1989. ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024;
  1990. #endif
  1991. /*
  1992. * if high capacity and partition setting completed
  1993. * SEC_COUNT is valid even if it is smaller than 2 GiB
  1994. * JEDEC Standard JESD84-B45, 6.2.4
  1995. */
  1996. if (mmc->high_capacity && part_completed) {
  1997. capacity = (ext_csd[EXT_CSD_SEC_CNT]) |
  1998. (ext_csd[EXT_CSD_SEC_CNT + 1] << 8) |
  1999. (ext_csd[EXT_CSD_SEC_CNT + 2] << 16) |
  2000. (ext_csd[EXT_CSD_SEC_CNT + 3] << 24);
  2001. capacity *= MMC_MAX_BLOCK_LEN;
  2002. mmc->capacity_user = capacity;
  2003. }
  2004. }
  2005. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2006. else {
  2007. /* Calculate the group size from the csd value. */
  2008. int erase_gsz, erase_gmul;
  2009. erase_gsz = (mmc->csd[2] & 0x00007c00) >> 10;
  2010. erase_gmul = (mmc->csd[2] & 0x000003e0) >> 5;
  2011. mmc->erase_grp_size = (erase_gsz + 1)
  2012. * (erase_gmul + 1);
  2013. }
  2014. #endif
  2015. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  2016. mmc->hc_wp_grp_size = 1024
  2017. * ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]
  2018. * ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
  2019. #endif
  2020. mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
  2021. return 0;
  2022. error:
  2023. if (mmc->ext_csd) {
  2024. #if !CONFIG_IS_ENABLED(MMC_TINY)
  2025. free(mmc->ext_csd);
  2026. #endif
  2027. mmc->ext_csd = NULL;
  2028. }
  2029. return err;
  2030. }
  2031. static int mmc_startup(struct mmc *mmc)
  2032. {
  2033. int err, i;
  2034. uint mult, freq;
  2035. u64 cmult, csize;
  2036. struct mmc_cmd cmd;
  2037. struct blk_desc *bdesc;
  2038. #ifdef CONFIG_MMC_SPI_CRC_ON
  2039. if (mmc_host_is_spi(mmc)) { /* enable CRC check for spi */
  2040. cmd.cmdidx = MMC_CMD_SPI_CRC_ON_OFF;
  2041. cmd.resp_type = MMC_RSP_R1;
  2042. cmd.cmdarg = 1;
  2043. err = mmc_send_cmd(mmc, &cmd, NULL);
  2044. if (err)
  2045. return err;
  2046. }
  2047. #endif
  2048. /* Put the Card in Identify Mode */
  2049. cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
  2050. MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
  2051. cmd.resp_type = MMC_RSP_R2;
  2052. cmd.cmdarg = 0;
  2053. err = mmc_send_cmd(mmc, &cmd, NULL);
  2054. #ifdef CONFIG_MMC_QUIRKS
  2055. if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
  2056. int retries = 4;
  2057. /*
  2058. * It has been seen that SEND_CID may fail on the first
  2059. * attempt, let's try a few more time
  2060. */
  2061. do {
  2062. err = mmc_send_cmd(mmc, &cmd, NULL);
  2063. if (!err)
  2064. break;
  2065. } while (retries--);
  2066. }
  2067. #endif
  2068. if (err)
  2069. return err;
  2070. memcpy(mmc->cid, cmd.response, 16);
  2071. /*
  2072. * For MMC cards, set the Relative Address.
  2073. * For SD cards, get the Relatvie Address.
  2074. * This also puts the cards into Standby State
  2075. */
  2076. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  2077. cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
  2078. cmd.cmdarg = mmc->rca << 16;
  2079. cmd.resp_type = MMC_RSP_R6;
  2080. err = mmc_send_cmd(mmc, &cmd, NULL);
  2081. if (err)
  2082. return err;
  2083. if (IS_SD(mmc))
  2084. mmc->rca = (cmd.response[0] >> 16) & 0xffff;
  2085. }
  2086. /* Get the Card-Specific Data */
  2087. cmd.cmdidx = MMC_CMD_SEND_CSD;
  2088. cmd.resp_type = MMC_RSP_R2;
  2089. cmd.cmdarg = mmc->rca << 16;
  2090. err = mmc_send_cmd(mmc, &cmd, NULL);
  2091. if (err)
  2092. return err;
  2093. mmc->csd[0] = cmd.response[0];
  2094. mmc->csd[1] = cmd.response[1];
  2095. mmc->csd[2] = cmd.response[2];
  2096. mmc->csd[3] = cmd.response[3];
  2097. if (mmc->version == MMC_VERSION_UNKNOWN) {
  2098. int version = (cmd.response[0] >> 26) & 0xf;
  2099. switch (version) {
  2100. case 0:
  2101. mmc->version = MMC_VERSION_1_2;
  2102. break;
  2103. case 1:
  2104. mmc->version = MMC_VERSION_1_4;
  2105. break;
  2106. case 2:
  2107. mmc->version = MMC_VERSION_2_2;
  2108. break;
  2109. case 3:
  2110. mmc->version = MMC_VERSION_3;
  2111. break;
  2112. case 4:
  2113. mmc->version = MMC_VERSION_4;
  2114. break;
  2115. default:
  2116. mmc->version = MMC_VERSION_1_2;
  2117. break;
  2118. }
  2119. }
  2120. /* divide frequency by 10, since the mults are 10x bigger */
  2121. freq = fbase[(cmd.response[0] & 0x7)];
  2122. mult = multipliers[((cmd.response[0] >> 3) & 0xf)];
  2123. mmc->legacy_speed = freq * mult;
  2124. mmc_select_mode(mmc, MMC_LEGACY);
  2125. mmc->dsr_imp = ((cmd.response[1] >> 12) & 0x1);
  2126. mmc->read_bl_len = 1 << ((cmd.response[1] >> 16) & 0xf);
  2127. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2128. if (IS_SD(mmc))
  2129. mmc->write_bl_len = mmc->read_bl_len;
  2130. else
  2131. mmc->write_bl_len = 1 << ((cmd.response[3] >> 22) & 0xf);
  2132. #endif
  2133. if (mmc->high_capacity) {
  2134. csize = (mmc->csd[1] & 0x3f) << 16
  2135. | (mmc->csd[2] & 0xffff0000) >> 16;
  2136. cmult = 8;
  2137. } else {
  2138. csize = (mmc->csd[1] & 0x3ff) << 2
  2139. | (mmc->csd[2] & 0xc0000000) >> 30;
  2140. cmult = (mmc->csd[2] & 0x00038000) >> 15;
  2141. }
  2142. mmc->capacity_user = (csize + 1) << (cmult + 2);
  2143. mmc->capacity_user *= mmc->read_bl_len;
  2144. mmc->capacity_boot = 0;
  2145. mmc->capacity_rpmb = 0;
  2146. for (i = 0; i < 4; i++)
  2147. mmc->capacity_gp[i] = 0;
  2148. if (mmc->read_bl_len > MMC_MAX_BLOCK_LEN)
  2149. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  2150. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2151. if (mmc->write_bl_len > MMC_MAX_BLOCK_LEN)
  2152. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  2153. #endif
  2154. if ((mmc->dsr_imp) && (0xffffffff != mmc->dsr)) {
  2155. cmd.cmdidx = MMC_CMD_SET_DSR;
  2156. cmd.cmdarg = (mmc->dsr & 0xffff) << 16;
  2157. cmd.resp_type = MMC_RSP_NONE;
  2158. if (mmc_send_cmd(mmc, &cmd, NULL))
  2159. pr_warn("MMC: SET_DSR failed\n");
  2160. }
  2161. /* Select the card, and put it into Transfer Mode */
  2162. if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
  2163. cmd.cmdidx = MMC_CMD_SELECT_CARD;
  2164. cmd.resp_type = MMC_RSP_R1;
  2165. cmd.cmdarg = mmc->rca << 16;
  2166. err = mmc_send_cmd(mmc, &cmd, NULL);
  2167. if (err)
  2168. return err;
  2169. }
  2170. /*
  2171. * For SD, its erase group is always one sector
  2172. */
  2173. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2174. mmc->erase_grp_size = 1;
  2175. #endif
  2176. mmc->part_config = MMCPART_NOAVAILABLE;
  2177. err = mmc_startup_v4(mmc);
  2178. if (err)
  2179. return err;
  2180. err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
  2181. if (err)
  2182. return err;
  2183. #if CONFIG_IS_ENABLED(MMC_TINY)
  2184. mmc_set_clock(mmc, mmc->legacy_speed, false);
  2185. mmc_select_mode(mmc, MMC_LEGACY);
  2186. mmc_set_bus_width(mmc, 1);
  2187. #else
  2188. if (IS_SD(mmc)) {
  2189. err = sd_get_capabilities(mmc);
  2190. if (err)
  2191. return err;
  2192. err = sd_select_mode_and_width(mmc, mmc->card_caps);
  2193. } else {
  2194. err = mmc_get_capabilities(mmc);
  2195. if (err)
  2196. return err;
  2197. err = mmc_select_mode_and_width(mmc, mmc->card_caps);
  2198. }
  2199. #endif
  2200. if (err)
  2201. return err;
  2202. mmc->best_mode = mmc->selected_mode;
  2203. /* Fix the block length for DDR mode */
  2204. if (mmc->ddr_mode) {
  2205. mmc->read_bl_len = MMC_MAX_BLOCK_LEN;
  2206. #if CONFIG_IS_ENABLED(MMC_WRITE)
  2207. mmc->write_bl_len = MMC_MAX_BLOCK_LEN;
  2208. #endif
  2209. }
  2210. /* fill in device description */
  2211. bdesc = mmc_get_blk_desc(mmc);
  2212. bdesc->lun = 0;
  2213. bdesc->hwpart = 0;
  2214. bdesc->type = 0;
  2215. bdesc->blksz = mmc->read_bl_len;
  2216. bdesc->log2blksz = LOG2(bdesc->blksz);
  2217. bdesc->lba = lldiv(mmc->capacity, mmc->read_bl_len);
  2218. #if !defined(CONFIG_SPL_BUILD) || \
  2219. (defined(CONFIG_SPL_LIBCOMMON_SUPPORT) && \
  2220. !CONFIG_IS_ENABLED(USE_TINY_PRINTF))
  2221. sprintf(bdesc->vendor, "Man %06x Snr %04x%04x",
  2222. mmc->cid[0] >> 24, (mmc->cid[2] & 0xffff),
  2223. (mmc->cid[3] >> 16) & 0xffff);
  2224. sprintf(bdesc->product, "%c%c%c%c%c%c", mmc->cid[0] & 0xff,
  2225. (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
  2226. (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff,
  2227. (mmc->cid[2] >> 24) & 0xff);
  2228. sprintf(bdesc->revision, "%d.%d", (mmc->cid[2] >> 20) & 0xf,
  2229. (mmc->cid[2] >> 16) & 0xf);
  2230. #else
  2231. bdesc->vendor[0] = 0;
  2232. bdesc->product[0] = 0;
  2233. bdesc->revision[0] = 0;
  2234. #endif
  2235. #if !defined(CONFIG_DM_MMC) && (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBDISK_SUPPORT))
  2236. part_init(bdesc);
  2237. #endif
  2238. return 0;
  2239. }
  2240. static int mmc_send_if_cond(struct mmc *mmc)
  2241. {
  2242. struct mmc_cmd cmd;
  2243. int err;
  2244. cmd.cmdidx = SD_CMD_SEND_IF_COND;
  2245. /* We set the bit if the host supports voltages between 2.7 and 3.6 V */
  2246. cmd.cmdarg = ((mmc->cfg->voltages & 0xff8000) != 0) << 8 | 0xaa;
  2247. cmd.resp_type = MMC_RSP_R7;
  2248. err = mmc_send_cmd(mmc, &cmd, NULL);
  2249. if (err)
  2250. return err;
  2251. if ((cmd.response[0] & 0xff) != 0xaa)
  2252. return -EOPNOTSUPP;
  2253. else
  2254. mmc->version = SD_VERSION_2;
  2255. return 0;
  2256. }
  2257. #if !CONFIG_IS_ENABLED(DM_MMC)
  2258. /* board-specific MMC power initializations. */
  2259. __weak void board_mmc_power_init(void)
  2260. {
  2261. }
  2262. #endif
  2263. static int mmc_power_init(struct mmc *mmc)
  2264. {
  2265. #if CONFIG_IS_ENABLED(DM_MMC)
  2266. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  2267. int ret;
  2268. ret = device_get_supply_regulator(mmc->dev, "vmmc-supply",
  2269. &mmc->vmmc_supply);
  2270. if (ret)
  2271. pr_debug("%s: No vmmc supply\n", mmc->dev->name);
  2272. ret = device_get_supply_regulator(mmc->dev, "vqmmc-supply",
  2273. &mmc->vqmmc_supply);
  2274. if (ret)
  2275. pr_debug("%s: No vqmmc supply\n", mmc->dev->name);
  2276. #endif
  2277. #else /* !CONFIG_DM_MMC */
  2278. /*
  2279. * Driver model should use a regulator, as above, rather than calling
  2280. * out to board code.
  2281. */
  2282. board_mmc_power_init();
  2283. #endif
  2284. return 0;
  2285. }
  2286. /*
  2287. * put the host in the initial state:
  2288. * - turn on Vdd (card power supply)
  2289. * - configure the bus width and clock to minimal values
  2290. */
  2291. static void mmc_set_initial_state(struct mmc *mmc)
  2292. {
  2293. int err;
  2294. /* First try to set 3.3V. If it fails set to 1.8V */
  2295. err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_330);
  2296. if (err != 0)
  2297. err = mmc_set_signal_voltage(mmc, MMC_SIGNAL_VOLTAGE_180);
  2298. if (err != 0)
  2299. pr_warn("mmc: failed to set signal voltage\n");
  2300. mmc_select_mode(mmc, MMC_LEGACY);
  2301. mmc_set_bus_width(mmc, 1);
  2302. mmc_set_clock(mmc, 0, MMC_CLK_ENABLE);
  2303. }
  2304. static int mmc_power_on(struct mmc *mmc)
  2305. {
  2306. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
  2307. if (mmc->vmmc_supply) {
  2308. int ret = regulator_set_enable(mmc->vmmc_supply, true);
  2309. if (ret) {
  2310. puts("Error enabling VMMC supply\n");
  2311. return ret;
  2312. }
  2313. }
  2314. #endif
  2315. return 0;
  2316. }
  2317. static int mmc_power_off(struct mmc *mmc)
  2318. {
  2319. mmc_set_clock(mmc, 0, MMC_CLK_DISABLE);
  2320. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_REGULATOR)
  2321. if (mmc->vmmc_supply) {
  2322. int ret = regulator_set_enable(mmc->vmmc_supply, false);
  2323. if (ret) {
  2324. pr_debug("Error disabling VMMC supply\n");
  2325. return ret;
  2326. }
  2327. }
  2328. #endif
  2329. return 0;
  2330. }
  2331. static int mmc_power_cycle(struct mmc *mmc)
  2332. {
  2333. int ret;
  2334. ret = mmc_power_off(mmc);
  2335. if (ret)
  2336. return ret;
  2337. ret = mmc_host_power_cycle(mmc);
  2338. if (ret)
  2339. return ret;
  2340. /*
  2341. * SD spec recommends at least 1ms of delay. Let's wait for 2ms
  2342. * to be on the safer side.
  2343. */
  2344. udelay(2000);
  2345. return mmc_power_on(mmc);
  2346. }
  2347. int mmc_get_op_cond(struct mmc *mmc)
  2348. {
  2349. bool uhs_en = supports_uhs(mmc->cfg->host_caps);
  2350. int err;
  2351. if (mmc->has_init)
  2352. return 0;
  2353. #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  2354. mmc_adapter_card_type_ident();
  2355. #endif
  2356. err = mmc_power_init(mmc);
  2357. if (err)
  2358. return err;
  2359. #ifdef CONFIG_MMC_QUIRKS
  2360. mmc->quirks = MMC_QUIRK_RETRY_SET_BLOCKLEN |
  2361. MMC_QUIRK_RETRY_SEND_CID |
  2362. MMC_QUIRK_RETRY_APP_CMD;
  2363. #endif
  2364. err = mmc_power_cycle(mmc);
  2365. if (err) {
  2366. /*
  2367. * if power cycling is not supported, we should not try
  2368. * to use the UHS modes, because we wouldn't be able to
  2369. * recover from an error during the UHS initialization.
  2370. */
  2371. pr_debug("Unable to do a full power cycle. Disabling the UHS modes for safety\n");
  2372. uhs_en = false;
  2373. mmc->host_caps &= ~UHS_CAPS;
  2374. err = mmc_power_on(mmc);
  2375. }
  2376. if (err)
  2377. return err;
  2378. #if CONFIG_IS_ENABLED(DM_MMC)
  2379. /* The device has already been probed ready for use */
  2380. #else
  2381. /* made sure it's not NULL earlier */
  2382. err = mmc->cfg->ops->init(mmc);
  2383. if (err)
  2384. return err;
  2385. #endif
  2386. mmc->ddr_mode = 0;
  2387. retry:
  2388. mmc_set_initial_state(mmc);
  2389. /* Reset the Card */
  2390. err = mmc_go_idle(mmc);
  2391. if (err)
  2392. return err;
  2393. /* The internal partition reset to user partition(0) at every CMD0*/
  2394. mmc_get_blk_desc(mmc)->hwpart = 0;
  2395. /* Test for SD version 2 */
  2396. err = mmc_send_if_cond(mmc);
  2397. /* Now try to get the SD card's operating condition */
  2398. err = sd_send_op_cond(mmc, uhs_en);
  2399. if (err && uhs_en) {
  2400. uhs_en = false;
  2401. mmc_power_cycle(mmc);
  2402. goto retry;
  2403. }
  2404. /* If the command timed out, we check for an MMC card */
  2405. if (err == -ETIMEDOUT) {
  2406. err = mmc_send_op_cond(mmc);
  2407. if (err) {
  2408. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  2409. pr_err("Card did not respond to voltage select!\n");
  2410. #endif
  2411. return -EOPNOTSUPP;
  2412. }
  2413. }
  2414. return err;
  2415. }
  2416. int mmc_start_init(struct mmc *mmc)
  2417. {
  2418. bool no_card;
  2419. int err = 0;
  2420. /*
  2421. * all hosts are capable of 1 bit bus-width and able to use the legacy
  2422. * timings.
  2423. */
  2424. mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
  2425. MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
  2426. #if CONFIG_IS_ENABLED(DM_MMC)
  2427. mmc_deferred_probe(mmc);
  2428. #endif
  2429. #if !defined(CONFIG_MMC_BROKEN_CD)
  2430. no_card = mmc_getcd(mmc) == 0;
  2431. #else
  2432. no_card = 0;
  2433. #endif
  2434. #if !CONFIG_IS_ENABLED(DM_MMC)
  2435. /* we pretend there's no card when init is NULL */
  2436. no_card = no_card || (mmc->cfg->ops->init == NULL);
  2437. #endif
  2438. if (no_card) {
  2439. mmc->has_init = 0;
  2440. #if !defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_LIBCOMMON_SUPPORT)
  2441. pr_err("MMC: no card present\n");
  2442. #endif
  2443. return -ENOMEDIUM;
  2444. }
  2445. err = mmc_get_op_cond(mmc);
  2446. if (!err)
  2447. mmc->init_in_progress = 1;
  2448. return err;
  2449. }
  2450. static int mmc_complete_init(struct mmc *mmc)
  2451. {
  2452. int err = 0;
  2453. mmc->init_in_progress = 0;
  2454. if (mmc->op_cond_pending)
  2455. err = mmc_complete_op_cond(mmc);
  2456. if (!err)
  2457. err = mmc_startup(mmc);
  2458. if (err)
  2459. mmc->has_init = 0;
  2460. else
  2461. mmc->has_init = 1;
  2462. return err;
  2463. }
  2464. int mmc_init(struct mmc *mmc)
  2465. {
  2466. int err = 0;
  2467. __maybe_unused ulong start;
  2468. #if CONFIG_IS_ENABLED(DM_MMC)
  2469. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
  2470. upriv->mmc = mmc;
  2471. #endif
  2472. if (mmc->has_init)
  2473. return 0;
  2474. start = get_timer(0);
  2475. if (!mmc->init_in_progress)
  2476. err = mmc_start_init(mmc);
  2477. if (!err)
  2478. err = mmc_complete_init(mmc);
  2479. if (err)
  2480. pr_info("%s: %d, time %lu\n", __func__, err, get_timer(start));
  2481. return err;
  2482. }
  2483. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT) || \
  2484. CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
  2485. CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
  2486. int mmc_deinit(struct mmc *mmc)
  2487. {
  2488. u32 caps_filtered;
  2489. if (!mmc->has_init)
  2490. return 0;
  2491. if (IS_SD(mmc)) {
  2492. caps_filtered = mmc->card_caps &
  2493. ~(MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) |
  2494. MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_DDR50) |
  2495. MMC_CAP(UHS_SDR104));
  2496. return sd_select_mode_and_width(mmc, caps_filtered);
  2497. } else {
  2498. caps_filtered = mmc->card_caps &
  2499. ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
  2500. return mmc_select_mode_and_width(mmc, caps_filtered);
  2501. }
  2502. }
  2503. #endif
  2504. int mmc_set_dsr(struct mmc *mmc, u16 val)
  2505. {
  2506. mmc->dsr = val;
  2507. return 0;
  2508. }
  2509. /* CPU-specific MMC initializations */
  2510. __weak int cpu_mmc_init(bd_t *bis)
  2511. {
  2512. return -1;
  2513. }
  2514. /* board-specific MMC initializations. */
  2515. __weak int board_mmc_init(bd_t *bis)
  2516. {
  2517. return -1;
  2518. }
  2519. void mmc_set_preinit(struct mmc *mmc, int preinit)
  2520. {
  2521. mmc->preinit = preinit;
  2522. }
  2523. #if CONFIG_IS_ENABLED(DM_MMC)
  2524. static int mmc_probe(bd_t *bis)
  2525. {
  2526. int ret, i;
  2527. struct uclass *uc;
  2528. struct udevice *dev;
  2529. ret = uclass_get(UCLASS_MMC, &uc);
  2530. if (ret)
  2531. return ret;
  2532. /*
  2533. * Try to add them in sequence order. Really with driver model we
  2534. * should allow holes, but the current MMC list does not allow that.
  2535. * So if we request 0, 1, 3 we will get 0, 1, 2.
  2536. */
  2537. for (i = 0; ; i++) {
  2538. ret = uclass_get_device_by_seq(UCLASS_MMC, i, &dev);
  2539. if (ret == -ENODEV)
  2540. break;
  2541. }
  2542. uclass_foreach_dev(dev, uc) {
  2543. ret = device_probe(dev);
  2544. if (ret)
  2545. pr_err("%s - probe failed: %d\n", dev->name, ret);
  2546. }
  2547. return 0;
  2548. }
  2549. #else
  2550. static int mmc_probe(bd_t *bis)
  2551. {
  2552. if (board_mmc_init(bis) < 0)
  2553. cpu_mmc_init(bis);
  2554. return 0;
  2555. }
  2556. #endif
  2557. int mmc_initialize(bd_t *bis)
  2558. {
  2559. static int initialized = 0;
  2560. int ret;
  2561. if (initialized) /* Avoid initializing mmc multiple times */
  2562. return 0;
  2563. initialized = 1;
  2564. #if !CONFIG_IS_ENABLED(BLK)
  2565. #if !CONFIG_IS_ENABLED(MMC_TINY)
  2566. mmc_list_init();
  2567. #endif
  2568. #endif
  2569. ret = mmc_probe(bis);
  2570. if (ret)
  2571. return ret;
  2572. #ifndef CONFIG_SPL_BUILD
  2573. print_mmc_devices(',');
  2574. #endif
  2575. mmc_do_preinit();
  2576. return 0;
  2577. }
  2578. #if CONFIG_IS_ENABLED(DM_MMC)
  2579. int mmc_init_device(int num)
  2580. {
  2581. struct udevice *dev;
  2582. struct mmc *m;
  2583. int ret;
  2584. ret = uclass_get_device(UCLASS_MMC, num, &dev);
  2585. if (ret)
  2586. return ret;
  2587. m = mmc_get_mmc_dev(dev);
  2588. if (!m)
  2589. return 0;
  2590. #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
  2591. mmc_set_preinit(m, 1);
  2592. #endif
  2593. if (m->preinit)
  2594. mmc_start_init(m);
  2595. return 0;
  2596. }
  2597. #endif
  2598. #ifdef CONFIG_CMD_BKOPS_ENABLE
  2599. int mmc_set_bkops_enable(struct mmc *mmc)
  2600. {
  2601. int err;
  2602. ALLOC_CACHE_ALIGN_BUFFER(u8, ext_csd, MMC_MAX_BLOCK_LEN);
  2603. err = mmc_send_ext_csd(mmc, ext_csd);
  2604. if (err) {
  2605. puts("Could not get ext_csd register values\n");
  2606. return err;
  2607. }
  2608. if (!(ext_csd[EXT_CSD_BKOPS_SUPPORT] & 0x1)) {
  2609. puts("Background operations not supported on device\n");
  2610. return -EMEDIUMTYPE;
  2611. }
  2612. if (ext_csd[EXT_CSD_BKOPS_EN] & 0x1) {
  2613. puts("Background operations already enabled\n");
  2614. return 0;
  2615. }
  2616. err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BKOPS_EN, 1);
  2617. if (err) {
  2618. puts("Failed to enable manual background operations\n");
  2619. return err;
  2620. }
  2621. puts("Enabled manual background operations\n");
  2622. return 0;
  2623. }
  2624. #endif