iproc_sdhci.c 7.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2019 Broadcom.
  4. *
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <malloc.h>
  10. #include <sdhci.h>
  11. DECLARE_GLOBAL_DATA_PTR;
  12. struct sdhci_iproc_host {
  13. struct sdhci_host host;
  14. u32 shadow_cmd;
  15. u32 shadow_blk;
  16. };
  17. #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
  18. static inline struct sdhci_iproc_host *to_iproc(struct sdhci_host *host)
  19. {
  20. return (struct sdhci_iproc_host *)host;
  21. }
  22. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  23. static u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
  24. {
  25. u32 val = readl(host->ioaddr + reg);
  26. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS_TRACE
  27. printf("%s %d: readl [0x%02x] 0x%08x\n",
  28. host->name, host->index, reg, val);
  29. #endif
  30. return val;
  31. }
  32. static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
  33. {
  34. u32 val = sdhci_iproc_readl(host, (reg & ~3));
  35. u16 word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
  36. return word;
  37. }
  38. static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
  39. {
  40. u32 val = sdhci_iproc_readl(host, (reg & ~3));
  41. u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
  42. return byte;
  43. }
  44. static void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
  45. {
  46. u32 clock = 0;
  47. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS_TRACE
  48. printf("%s %d: writel [0x%02x] 0x%08x\n",
  49. host->name, host->index, reg, val);
  50. #endif
  51. writel(val, host->ioaddr + reg);
  52. if (host->mmc)
  53. clock = host->mmc->clock;
  54. if (clock <= 400000) {
  55. /* Round up to micro-second four SD clock delay */
  56. if (clock)
  57. udelay((4 * 1000000 + clock - 1) / clock);
  58. else
  59. udelay(10);
  60. }
  61. }
  62. /*
  63. * The Arasan has a bugette whereby it may lose the content of successive
  64. * writes to the same register that are within two SD-card clock cycles of
  65. * each other (a clock domain crossing problem). The data
  66. * register does not have this problem, which is just as well - otherwise we'd
  67. * have to nobble the DMA engine too.
  68. *
  69. * This wouldn't be a problem with the code except that we can only write the
  70. * controller with 32-bit writes. So two different 16-bit registers are
  71. * written back to back creates the problem.
  72. *
  73. * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
  74. * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
  75. * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
  76. * the work around can be further optimized. We can keep shadow values of
  77. * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
  78. * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
  79. * by the TRANSFER+COMMAND in another 32-bit write.
  80. */
  81. static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
  82. {
  83. struct sdhci_iproc_host *iproc_host = to_iproc(host);
  84. u32 word_shift = REG_OFFSET_IN_BITS(reg);
  85. u32 mask = 0xffff << word_shift;
  86. u32 oldval, newval;
  87. if (reg == SDHCI_COMMAND) {
  88. /* Write the block now as we are issuing a command */
  89. if (iproc_host->shadow_blk != 0) {
  90. sdhci_iproc_writel(host, iproc_host->shadow_blk,
  91. SDHCI_BLOCK_SIZE);
  92. iproc_host->shadow_blk = 0;
  93. }
  94. oldval = iproc_host->shadow_cmd;
  95. } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
  96. /* Block size and count are stored in shadow reg */
  97. oldval = iproc_host->shadow_blk;
  98. } else {
  99. /* Read reg, all other registers are not shadowed */
  100. oldval = sdhci_iproc_readl(host, (reg & ~3));
  101. }
  102. newval = (oldval & ~mask) | (val << word_shift);
  103. if (reg == SDHCI_TRANSFER_MODE) {
  104. /* Save the transfer mode until the command is issued */
  105. iproc_host->shadow_cmd = newval;
  106. } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
  107. /* Save the block info until the command is issued */
  108. iproc_host->shadow_blk = newval;
  109. } else {
  110. /* Command or other regular 32-bit write */
  111. sdhci_iproc_writel(host, newval, reg & ~3);
  112. }
  113. }
  114. static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
  115. {
  116. u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
  117. u32 byte_shift = REG_OFFSET_IN_BITS(reg);
  118. u32 mask = 0xff << byte_shift;
  119. u32 newval = (oldval & ~mask) | (val << byte_shift);
  120. sdhci_iproc_writel(host, newval, reg & ~3);
  121. }
  122. #endif
  123. static int sdhci_iproc_set_ios_post(struct sdhci_host *host)
  124. {
  125. u32 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  126. /* Reset UHS mode bits */
  127. ctrl &= ~SDHCI_CTRL_UHS_MASK;
  128. if (host->mmc->ddr_mode)
  129. ctrl |= UHS_DDR50_BUS_SPEED;
  130. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  131. return 0;
  132. }
  133. static struct sdhci_ops sdhci_platform_ops = {
  134. #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
  135. .read_l = sdhci_iproc_readl,
  136. .read_w = sdhci_iproc_readw,
  137. .read_b = sdhci_iproc_readb,
  138. .write_l = sdhci_iproc_writel,
  139. .write_w = sdhci_iproc_writew,
  140. .write_b = sdhci_iproc_writeb,
  141. #endif
  142. .set_ios_post = sdhci_iproc_set_ios_post,
  143. };
  144. struct iproc_sdhci_plat {
  145. struct mmc_config cfg;
  146. struct mmc mmc;
  147. };
  148. static int iproc_sdhci_probe(struct udevice *dev)
  149. {
  150. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  151. struct iproc_sdhci_plat *plat = dev_get_platdata(dev);
  152. struct sdhci_host *host = dev_get_priv(dev);
  153. struct sdhci_iproc_host *iproc_host;
  154. int node = dev_of_offset(dev);
  155. u32 f_min_max[2];
  156. int ret;
  157. iproc_host = malloc(sizeof(struct sdhci_iproc_host));
  158. if (!iproc_host) {
  159. printf("%s: sdhci host malloc fail!\n", __func__);
  160. return -ENOMEM;
  161. }
  162. iproc_host->shadow_cmd = 0;
  163. iproc_host->shadow_blk = 0;
  164. host->name = dev->name;
  165. host->ioaddr = (void *)devfdt_get_addr(dev);
  166. host->voltages = MMC_VDD_165_195 |
  167. MMC_VDD_32_33 | MMC_VDD_33_34;
  168. host->quirks = SDHCI_QUIRK_BROKEN_VOLTAGE | SDHCI_QUIRK_BROKEN_R1B;
  169. host->host_caps = MMC_MODE_DDR_52MHz;
  170. host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
  171. host->ops = &sdhci_platform_ops;
  172. host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
  173. ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
  174. "clock-freq-min-max", f_min_max, 2);
  175. if (ret) {
  176. printf("sdhci: clock-freq-min-max not found\n");
  177. free(iproc_host);
  178. return ret;
  179. }
  180. host->max_clk = f_min_max[1];
  181. host->bus_width = fdtdec_get_int(gd->fdt_blob,
  182. dev_of_offset(dev), "bus-width", 4);
  183. /* Update host_caps for 8 bit bus width */
  184. if (host->bus_width == 8)
  185. host->host_caps |= MMC_MODE_8BIT;
  186. memcpy(&iproc_host->host, host, sizeof(struct sdhci_host));
  187. iproc_host->host.mmc = &plat->mmc;
  188. iproc_host->host.mmc->dev = dev;
  189. iproc_host->host.mmc->priv = &iproc_host->host;
  190. upriv->mmc = iproc_host->host.mmc;
  191. ret = sdhci_setup_cfg(&plat->cfg, &iproc_host->host,
  192. f_min_max[1], f_min_max[0]);
  193. if (ret) {
  194. free(iproc_host);
  195. return ret;
  196. }
  197. return sdhci_probe(dev);
  198. }
  199. static int iproc_sdhci_bind(struct udevice *dev)
  200. {
  201. struct iproc_sdhci_plat *plat = dev_get_platdata(dev);
  202. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  203. }
  204. static const struct udevice_id iproc_sdhci_ids[] = {
  205. { .compatible = "brcm,iproc-sdhci" },
  206. { }
  207. };
  208. U_BOOT_DRIVER(iproc_sdhci_drv) = {
  209. .name = "iproc_sdhci",
  210. .id = UCLASS_MMC,
  211. .of_match = iproc_sdhci_ids,
  212. .ops = &sdhci_ops,
  213. .bind = iproc_sdhci_bind,
  214. .probe = iproc_sdhci_probe,
  215. .priv_auto_alloc_size = sizeof(struct sdhci_host),
  216. .platdata_auto_alloc_size = sizeof(struct iproc_sdhci_plat),
  217. };