am654_sdhci.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Texas Instruments' K3 SD Host Controller Interface
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <malloc.h>
  11. #include <power-domain.h>
  12. #include <regmap.h>
  13. #include <sdhci.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/err.h>
  16. /* CTL_CFG Registers */
  17. #define CTL_CFG_2 0x14
  18. #define SLOTTYPE_MASK GENMASK(31, 30)
  19. #define SLOTTYPE_EMBEDDED BIT(30)
  20. /* PHY Registers */
  21. #define PHY_CTRL1 0x100
  22. #define PHY_CTRL2 0x104
  23. #define PHY_CTRL3 0x108
  24. #define PHY_CTRL4 0x10C
  25. #define PHY_CTRL5 0x110
  26. #define PHY_CTRL6 0x114
  27. #define PHY_STAT1 0x130
  28. #define PHY_STAT2 0x134
  29. #define IOMUX_ENABLE_SHIFT 31
  30. #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
  31. #define OTAPDLYENA_SHIFT 20
  32. #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
  33. #define OTAPDLYSEL_SHIFT 12
  34. #define OTAPDLYSEL_MASK GENMASK(15, 12)
  35. #define STRBSEL_SHIFT 24
  36. #define STRBSEL_4BIT_MASK GENMASK(27, 24)
  37. #define STRBSEL_8BIT_MASK GENMASK(31, 24)
  38. #define SEL50_SHIFT 8
  39. #define SEL50_MASK BIT(SEL50_SHIFT)
  40. #define SEL100_SHIFT 9
  41. #define SEL100_MASK BIT(SEL100_SHIFT)
  42. #define FREQSEL_SHIFT 8
  43. #define FREQSEL_MASK GENMASK(10, 8)
  44. #define DLL_TRIM_ICP_SHIFT 4
  45. #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
  46. #define DR_TY_SHIFT 20
  47. #define DR_TY_MASK GENMASK(22, 20)
  48. #define ENDLL_SHIFT 1
  49. #define ENDLL_MASK BIT(ENDLL_SHIFT)
  50. #define DLLRDY_SHIFT 0
  51. #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
  52. #define PDB_SHIFT 0
  53. #define PDB_MASK BIT(PDB_SHIFT)
  54. #define CALDONE_SHIFT 1
  55. #define CALDONE_MASK BIT(CALDONE_SHIFT)
  56. #define RETRIM_SHIFT 17
  57. #define RETRIM_MASK BIT(RETRIM_SHIFT)
  58. #define DRIVER_STRENGTH_50_OHM 0x0
  59. #define DRIVER_STRENGTH_33_OHM 0x1
  60. #define DRIVER_STRENGTH_66_OHM 0x2
  61. #define DRIVER_STRENGTH_100_OHM 0x3
  62. #define DRIVER_STRENGTH_40_OHM 0x4
  63. #define AM654_SDHCI_MIN_FREQ 400000
  64. struct am654_sdhci_plat {
  65. struct mmc_config cfg;
  66. struct mmc mmc;
  67. struct regmap *base;
  68. bool non_removable;
  69. u32 otap_del_sel[11];
  70. u32 trm_icp;
  71. u32 drv_strength;
  72. u32 strb_sel;
  73. u32 flags;
  74. #define DLL_PRESENT (1 << 0)
  75. #define IOMUX_PRESENT (1 << 1)
  76. #define FREQSEL_2_BIT (1 << 2)
  77. #define STRBSEL_4_BIT (1 << 3)
  78. bool dll_on;
  79. };
  80. struct timing_data {
  81. const char *binding;
  82. u32 capability;
  83. };
  84. static const struct timing_data td[] = {
  85. [MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0},
  86. [MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)},
  87. [SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)},
  88. [UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)},
  89. [UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)},
  90. [UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)},
  91. [UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)},
  92. [UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)},
  93. [MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)},
  94. [MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)},
  95. [MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)},
  96. };
  97. struct am654_driver_data {
  98. const struct sdhci_ops *ops;
  99. u32 flags;
  100. };
  101. static void am654_sdhci_set_control_reg(struct sdhci_host *host)
  102. {
  103. struct mmc *mmc = (struct mmc *)host->mmc;
  104. u32 reg;
  105. if (IS_SD(host->mmc) &&
  106. mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  107. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  108. reg |= SDHCI_CTRL_VDD_180;
  109. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  110. }
  111. sdhci_set_uhs_timing(host);
  112. }
  113. static int am654_sdhci_set_ios_post(struct sdhci_host *host)
  114. {
  115. struct udevice *dev = host->mmc->dev;
  116. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  117. unsigned int speed = host->mmc->clock;
  118. int sel50, sel100, freqsel;
  119. u32 otap_del_sel;
  120. u32 mask, val;
  121. int ret;
  122. /* Reset SD Clock Enable */
  123. val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  124. val &= ~SDHCI_CLOCK_CARD_EN;
  125. sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
  126. /* power off phy */
  127. if (plat->dll_on) {
  128. regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
  129. plat->dll_on = false;
  130. }
  131. /* restart clock */
  132. sdhci_set_clock(host->mmc, speed);
  133. /* switch phy back on */
  134. if (speed > AM654_SDHCI_MIN_FREQ) {
  135. otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
  136. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  137. val = (1 << OTAPDLYENA_SHIFT) |
  138. (otap_del_sel << OTAPDLYSEL_SHIFT);
  139. /* Write to STRBSEL for HS400 speed mode */
  140. if (host->mmc->selected_mode == MMC_HS_400) {
  141. if (plat->flags & STRBSEL_4_BIT)
  142. mask |= STRBSEL_4BIT_MASK;
  143. else
  144. mask |= STRBSEL_8BIT_MASK;
  145. val |= plat->strb_sel << STRBSEL_SHIFT;
  146. }
  147. regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
  148. if (plat->flags & FREQSEL_2_BIT) {
  149. switch (speed) {
  150. case 200000000:
  151. sel50 = 0;
  152. sel100 = 0;
  153. break;
  154. case 100000000:
  155. sel50 = 0;
  156. sel100 = 1;
  157. break;
  158. default:
  159. sel50 = 1;
  160. sel100 = 0;
  161. }
  162. /* Configure PHY DLL frequency */
  163. mask = SEL50_MASK | SEL100_MASK;
  164. val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
  165. regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
  166. } else {
  167. switch (speed) {
  168. case 200000000:
  169. freqsel = 0x0;
  170. break;
  171. default:
  172. freqsel = 0x4;
  173. }
  174. regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
  175. freqsel << FREQSEL_SHIFT);
  176. }
  177. /* Enable DLL */
  178. regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
  179. 0x1 << ENDLL_SHIFT);
  180. /*
  181. * Poll for DLL ready. Use a one second timeout.
  182. * Works in all experiments done so far
  183. */
  184. ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
  185. val & DLLRDY_MASK, 1000, 1000000);
  186. if (ret)
  187. return ret;
  188. plat->dll_on = true;
  189. }
  190. return 0;
  191. }
  192. int am654_sdhci_init(struct am654_sdhci_plat *plat)
  193. {
  194. u32 ctl_cfg_2 = 0;
  195. u32 mask, val;
  196. int ret;
  197. /* Reset OTAP to default value */
  198. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  199. regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
  200. if (plat->flags & DLL_PRESENT) {
  201. regmap_read(plat->base, PHY_STAT1, &val);
  202. if (~val & CALDONE_MASK) {
  203. /* Calibrate IO lines */
  204. regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
  205. PDB_MASK);
  206. ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
  207. val, val & CALDONE_MASK,
  208. 1, 20);
  209. if (ret)
  210. return ret;
  211. }
  212. /* Configure DLL TRIM */
  213. mask = DLL_TRIM_ICP_MASK;
  214. val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
  215. /* Configure DLL driver strength */
  216. mask |= DR_TY_MASK;
  217. val |= plat->drv_strength << DR_TY_SHIFT;
  218. regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
  219. }
  220. /* Enable pins by setting IO mux to 0 */
  221. if (plat->flags & IOMUX_PRESENT)
  222. regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
  223. /* Set slot type based on SD or eMMC */
  224. if (plat->non_removable)
  225. ctl_cfg_2 = SLOTTYPE_EMBEDDED;
  226. regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
  227. return 0;
  228. }
  229. #define MAX_SDCD_DEBOUNCE_TIME 2000
  230. static int am654_sdhci_deferred_probe(struct sdhci_host *host)
  231. {
  232. struct udevice *dev = host->mmc->dev;
  233. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  234. unsigned long start;
  235. int val;
  236. /*
  237. * The controller takes about 1 second to debounce the card detect line
  238. * and doesn't let us power on until that time is up. Instead of waiting
  239. * for 1 second at every stage, poll on the CARD_PRESENT bit upto a
  240. * maximum of 2 seconds to be safe..
  241. */
  242. start = get_timer(0);
  243. do {
  244. if (get_timer(start) > MAX_SDCD_DEBOUNCE_TIME)
  245. return -ENOMEDIUM;
  246. val = mmc_getcd(host->mmc);
  247. } while (!val);
  248. am654_sdhci_init(plat);
  249. return sdhci_probe(dev);
  250. }
  251. const struct sdhci_ops am654_sdhci_ops = {
  252. .deferred_probe = am654_sdhci_deferred_probe,
  253. .set_ios_post = &am654_sdhci_set_ios_post,
  254. .set_control_reg = &am654_sdhci_set_control_reg,
  255. };
  256. const struct am654_driver_data am654_drv_data = {
  257. .ops = &am654_sdhci_ops,
  258. .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT,
  259. };
  260. const struct am654_driver_data j721e_8bit_drv_data = {
  261. .ops = &am654_sdhci_ops,
  262. .flags = DLL_PRESENT,
  263. };
  264. static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
  265. {
  266. struct udevice *dev = host->mmc->dev;
  267. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  268. u32 otap_del_sel, mask, val;
  269. otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
  270. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  271. val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
  272. regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
  273. return 0;
  274. }
  275. const struct sdhci_ops j721e_4bit_sdhci_ops = {
  276. .deferred_probe = am654_sdhci_deferred_probe,
  277. .set_ios_post = &j721e_4bit_sdhci_set_ios_post,
  278. };
  279. const struct am654_driver_data j721e_4bit_drv_data = {
  280. .ops = &j721e_4bit_sdhci_ops,
  281. .flags = IOMUX_PRESENT,
  282. };
  283. static int sdhci_am654_get_otap_delay(struct udevice *dev,
  284. struct mmc_config *cfg)
  285. {
  286. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  287. int ret;
  288. int i;
  289. /* ti,otap-del-sel-legacy is mandatory */
  290. ret = dev_read_u32(dev, "ti,otap-del-sel-legacy",
  291. &plat->otap_del_sel[0]);
  292. if (ret)
  293. return ret;
  294. /*
  295. * Remove the corresponding capability if an otap-del-sel
  296. * value is not found
  297. */
  298. for (i = MMC_HS; i <= MMC_HS_400; i++) {
  299. ret = dev_read_u32(dev, td[i].binding, &plat->otap_del_sel[i]);
  300. if (ret) {
  301. dev_dbg(dev, "Couldn't find %s\n", td[i].binding);
  302. /*
  303. * Remove the corresponding capability
  304. * if an otap-del-sel value is not found
  305. */
  306. cfg->host_caps &= ~td[i].capability;
  307. }
  308. }
  309. return 0;
  310. }
  311. static int am654_sdhci_probe(struct udevice *dev)
  312. {
  313. struct am654_driver_data *drv_data =
  314. (struct am654_driver_data *)dev_get_driver_data(dev);
  315. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  316. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  317. struct sdhci_host *host = dev_get_priv(dev);
  318. struct mmc_config *cfg = &plat->cfg;
  319. struct clk clk;
  320. unsigned long clock;
  321. int ret;
  322. ret = clk_get_by_name(dev, "clk_xin", &clk);
  323. if (ret) {
  324. dev_err(dev, "failed to get clock\n");
  325. return ret;
  326. }
  327. clock = clk_get_rate(&clk);
  328. if (IS_ERR_VALUE(clock)) {
  329. dev_err(dev, "failed to get rate\n");
  330. return clock;
  331. }
  332. host->max_clk = clock;
  333. host->mmc = &plat->mmc;
  334. host->mmc->dev = dev;
  335. ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
  336. AM654_SDHCI_MIN_FREQ);
  337. if (ret)
  338. return ret;
  339. ret = sdhci_am654_get_otap_delay(dev, cfg);
  340. if (ret)
  341. return ret;
  342. host->ops = drv_data->ops;
  343. host->mmc->priv = host;
  344. upriv->mmc = host->mmc;
  345. regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
  346. return 0;
  347. }
  348. static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
  349. {
  350. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  351. struct sdhci_host *host = dev_get_priv(dev);
  352. struct mmc_config *cfg = &plat->cfg;
  353. u32 drv_strength;
  354. int ret;
  355. host->name = dev->name;
  356. host->ioaddr = (void *)dev_read_addr(dev);
  357. plat->non_removable = dev_read_bool(dev, "non-removable");
  358. if (plat->flags & DLL_PRESENT) {
  359. ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
  360. if (ret)
  361. return ret;
  362. ret = dev_read_u32(dev, "ti,driver-strength-ohm",
  363. &drv_strength);
  364. if (ret)
  365. return ret;
  366. switch (drv_strength) {
  367. case 50:
  368. plat->drv_strength = DRIVER_STRENGTH_50_OHM;
  369. break;
  370. case 33:
  371. plat->drv_strength = DRIVER_STRENGTH_33_OHM;
  372. break;
  373. case 66:
  374. plat->drv_strength = DRIVER_STRENGTH_66_OHM;
  375. break;
  376. case 100:
  377. plat->drv_strength = DRIVER_STRENGTH_100_OHM;
  378. break;
  379. case 40:
  380. plat->drv_strength = DRIVER_STRENGTH_40_OHM;
  381. break;
  382. default:
  383. dev_err(dev, "Invalid driver strength\n");
  384. return -EINVAL;
  385. }
  386. }
  387. ret = mmc_of_parse(dev, cfg);
  388. if (ret)
  389. return ret;
  390. return 0;
  391. }
  392. static int am654_sdhci_bind(struct udevice *dev)
  393. {
  394. struct am654_driver_data *drv_data =
  395. (struct am654_driver_data *)dev_get_driver_data(dev);
  396. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  397. plat->flags = drv_data->flags;
  398. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  399. }
  400. static const struct udevice_id am654_sdhci_ids[] = {
  401. {
  402. .compatible = "ti,am654-sdhci-5.1",
  403. .data = (ulong)&am654_drv_data,
  404. },
  405. {
  406. .compatible = "ti,j721e-sdhci-8bit",
  407. .data = (ulong)&j721e_8bit_drv_data,
  408. },
  409. {
  410. .compatible = "ti,j721e-sdhci-4bit",
  411. .data = (ulong)&j721e_4bit_drv_data,
  412. },
  413. { }
  414. };
  415. U_BOOT_DRIVER(am654_sdhci_drv) = {
  416. .name = "am654_sdhci",
  417. .id = UCLASS_MMC,
  418. .of_match = am654_sdhci_ids,
  419. .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata,
  420. .ops = &sdhci_ops,
  421. .bind = am654_sdhci_bind,
  422. .probe = am654_sdhci_probe,
  423. .priv_auto_alloc_size = sizeof(struct sdhci_host),
  424. .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat),
  425. };