sata_sil3114.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Excito Elektronik i Skåne AB, All rights reserved.
  4. * Author: Tor Krill <tor@excito.com>
  5. *
  6. * This is a driver for Silicon Image sil3114 sata chip modelled on
  7. * the ata_piix driver
  8. */
  9. #include <common.h>
  10. #include <blk.h>
  11. #include <part.h>
  12. #include <pci.h>
  13. #include <command.h>
  14. #include <config.h>
  15. #include <asm/byteorder.h>
  16. #include <asm/io.h>
  17. #include <ide.h>
  18. #include <sata.h>
  19. #include <libata.h>
  20. #include "sata_sil3114.h"
  21. /* Convert sectorsize to wordsize */
  22. #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
  23. /* Forwards */
  24. u8 sil3114_spin_up (int num);
  25. u8 sil3114_spin_down (int num);
  26. static int sata_bus_softreset (int num);
  27. static void sata_identify (int num, int dev);
  28. static u8 check_power_mode (int num);
  29. static void sata_port (struct sata_ioports *ioport);
  30. static void set_Feature_cmd (int num, int dev);
  31. static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
  32. unsigned int max, u8 usealtstatus);
  33. static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus);
  34. static void msleep (int count);
  35. static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
  36. static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
  37. static void output_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
  38. {
  39. while (words--) {
  40. __raw_writew (*sect_buf++, (void *)ioaddr->data_addr);
  41. }
  42. }
  43. static int input_data (struct sata_ioports *ioaddr, u16 * sect_buf, int words)
  44. {
  45. while (words--) {
  46. *sect_buf++ = __raw_readw ((void *)ioaddr->data_addr);
  47. }
  48. return 0;
  49. }
  50. static int sata_bus_softreset (int num)
  51. {
  52. u8 status = 0;
  53. port[num].dev_mask = 1;
  54. port[num].ctl_reg = 0x08; /*Default value of control reg */
  55. writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
  56. udelay (10);
  57. writeb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
  58. udelay (10);
  59. writeb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
  60. /* spec mandates ">= 2ms" before checking status.
  61. * We wait 150ms, because that was the magic delay used for
  62. * ATAPI devices in Hale Landis's ATADRVR, for the period of time
  63. * between when the ATA command register is written, and then
  64. * status is checked. Because waiting for "a while" before
  65. * checking status is fine, post SRST, we perform this magic
  66. * delay here as well.
  67. */
  68. msleep (150);
  69. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300, 0);
  70. while ((status & ATA_BUSY)) {
  71. msleep (100);
  72. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3, 0);
  73. }
  74. if (status & ATA_BUSY) {
  75. printf ("ata%u is slow to respond,plz be patient\n", num);
  76. }
  77. while ((status & ATA_BUSY)) {
  78. msleep (100);
  79. status = sata_chk_status (&port[num].ioaddr, 0);
  80. }
  81. if (status & ATA_BUSY) {
  82. printf ("ata%u failed to respond : ", num);
  83. printf ("bus reset failed\n");
  84. port[num].dev_mask = 0;
  85. return 1;
  86. }
  87. return 0;
  88. }
  89. static void sata_identify (int num, int dev)
  90. {
  91. u8 cmd = 0, status = 0, devno = num;
  92. u16 iobuf[ATA_SECTOR_WORDS];
  93. u64 n_sectors = 0;
  94. memset (iobuf, 0, sizeof (iobuf));
  95. if (!(port[num].dev_mask & 0x01)) {
  96. printf ("dev%d is not present on port#%d\n", dev, num);
  97. return;
  98. }
  99. debug ("port=%d dev=%d\n", num, dev);
  100. status = 0;
  101. cmd = ATA_CMD_ID_ATA; /*Device Identify Command */
  102. writeb (cmd, port[num].ioaddr.command_addr);
  103. readb (port[num].ioaddr.altstatus_addr);
  104. udelay (10);
  105. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000, 0);
  106. if (status & ATA_ERR) {
  107. printf ("\ndevice not responding\n");
  108. port[num].dev_mask &= ~0x01;
  109. return;
  110. }
  111. input_data (&port[num].ioaddr, iobuf, ATA_SECTOR_WORDS);
  112. ata_swap_buf_le16 (iobuf, ATA_SECTOR_WORDS);
  113. debug ("Specific config: %x\n", iobuf[2]);
  114. /* we require LBA and DMA support (bits 8 & 9 of word 49) */
  115. if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
  116. debug ("ata%u: no dma/lba\n", num);
  117. }
  118. #ifdef DEBUG
  119. ata_dump_id (iobuf);
  120. #endif
  121. n_sectors = ata_id_n_sectors (iobuf);
  122. if (n_sectors == 0) {
  123. port[num].dev_mask &= ~0x01;
  124. return;
  125. }
  126. ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].revision,
  127. ATA_ID_FW_REV, sizeof (sata_dev_desc[devno].revision));
  128. ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].vendor,
  129. ATA_ID_PROD, sizeof (sata_dev_desc[devno].vendor));
  130. ata_id_c_string (iobuf, (unsigned char *)sata_dev_desc[devno].product,
  131. ATA_ID_SERNO, sizeof (sata_dev_desc[devno].product));
  132. /* TODO - atm we asume harddisk ie not removable */
  133. sata_dev_desc[devno].removable = 0;
  134. sata_dev_desc[devno].lba = (u32) n_sectors;
  135. debug("lba=0x%lx\n", sata_dev_desc[devno].lba);
  136. #ifdef CONFIG_LBA48
  137. if (iobuf[83] & (1 << 10)) {
  138. sata_dev_desc[devno].lba48 = 1;
  139. } else {
  140. sata_dev_desc[devno].lba48 = 0;
  141. }
  142. #endif
  143. /* assuming HD */
  144. sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
  145. sata_dev_desc[devno].blksz = ATA_SECT_SIZE;
  146. sata_dev_desc[devno].lun = 0; /* just to fill something in... */
  147. }
  148. static void set_Feature_cmd (int num, int dev)
  149. {
  150. u8 status = 0;
  151. if (!(port[num].dev_mask & 0x01)) {
  152. debug ("dev%d is not present on port#%d\n", dev, num);
  153. return;
  154. }
  155. writeb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
  156. writeb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
  157. writeb (0, port[num].ioaddr.lbal_addr);
  158. writeb (0, port[num].ioaddr.lbam_addr);
  159. writeb (0, port[num].ioaddr.lbah_addr);
  160. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  161. writeb (ATA_CMD_SET_FEATURES, port[num].ioaddr.command_addr);
  162. udelay (50);
  163. msleep (150);
  164. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
  165. if ((status & (ATA_BUSY | ATA_ERR))) {
  166. printf ("Error : status 0x%02x\n", status);
  167. port[num].dev_mask &= ~0x01;
  168. }
  169. }
  170. u8 sil3114_spin_down (int num)
  171. {
  172. u8 status = 0;
  173. debug ("Spin down disk\n");
  174. if (!(port[num].dev_mask & 0x01)) {
  175. debug ("Device ata%d is not present\n", num);
  176. return 1;
  177. }
  178. if ((status = check_power_mode (num)) == 0x00) {
  179. debug ("Already in standby\n");
  180. return 0;
  181. }
  182. if (status == 0x01) {
  183. printf ("Failed to check power mode on ata%d\n", num);
  184. return 1;
  185. }
  186. if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
  187. printf ("Device ata%d not ready\n", num);
  188. return 1;
  189. }
  190. writeb (0x00, port[num].ioaddr.feature_addr);
  191. writeb (0x00, port[num].ioaddr.nsect_addr);
  192. writeb (0x00, port[num].ioaddr.lbal_addr);
  193. writeb (0x00, port[num].ioaddr.lbam_addr);
  194. writeb (0x00, port[num].ioaddr.lbah_addr);
  195. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  196. writeb (ATA_CMD_STANDBY, port[num].ioaddr.command_addr);
  197. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
  198. if ((status & (ATA_BUSY | ATA_ERR))) {
  199. printf ("Error waiting for disk spin down: status 0x%02x\n",
  200. status);
  201. port[num].dev_mask &= ~0x01;
  202. return 1;
  203. }
  204. return 0;
  205. }
  206. u8 sil3114_spin_up (int num)
  207. {
  208. u8 status = 0;
  209. debug ("Spin up disk\n");
  210. if (!(port[num].dev_mask & 0x01)) {
  211. debug ("Device ata%d is not present\n", num);
  212. return 1;
  213. }
  214. if ((status = check_power_mode (num)) != 0x00) {
  215. if (status == 0x01) {
  216. printf ("Failed to check power mode on ata%d\n", num);
  217. return 1;
  218. } else {
  219. /* should be up and running already */
  220. return 0;
  221. }
  222. }
  223. if (!((status = sata_chk_status (&port[num].ioaddr, 0)) & ATA_DRDY)) {
  224. printf ("Device ata%d not ready\n", num);
  225. return 1;
  226. }
  227. debug ("Stautus of device check: %d\n", status);
  228. writeb (0x00, port[num].ioaddr.feature_addr);
  229. writeb (0x00, port[num].ioaddr.nsect_addr);
  230. writeb (0x00, port[num].ioaddr.lbal_addr);
  231. writeb (0x00, port[num].ioaddr.lbam_addr);
  232. writeb (0x00, port[num].ioaddr.lbah_addr);
  233. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  234. writeb (ATA_CMD_IDLE, port[num].ioaddr.command_addr);
  235. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 30000, 0);
  236. if ((status & (ATA_BUSY | ATA_ERR))) {
  237. printf ("Error waiting for disk spin up: status 0x%02x\n",
  238. status);
  239. port[num].dev_mask &= ~0x01;
  240. return 1;
  241. }
  242. /* Wait for disk to enter Active state */
  243. do {
  244. msleep (10);
  245. status = check_power_mode (num);
  246. } while ((status == 0x00) || (status == 0x80));
  247. if (status == 0x01) {
  248. printf ("Falied waiting for disk to spin up\n");
  249. return 1;
  250. }
  251. return 0;
  252. }
  253. /* Return value is not the usual here
  254. * 0x00 - Device stand by
  255. * 0x01 - Operation failed
  256. * 0x80 - Device idle
  257. * 0xff - Device active
  258. */
  259. static u8 check_power_mode (int num)
  260. {
  261. u8 status = 0;
  262. u8 res = 0;
  263. if (!(port[num].dev_mask & 0x01)) {
  264. debug ("Device ata%d is not present\n", num);
  265. return 1;
  266. }
  267. if (!(sata_chk_status (&port[num].ioaddr, 0) & ATA_DRDY)) {
  268. printf ("Device ata%d not ready\n", num);
  269. return 1;
  270. }
  271. writeb (0, port[num].ioaddr.feature_addr);
  272. writeb (0, port[num].ioaddr.nsect_addr);
  273. writeb (0, port[num].ioaddr.lbal_addr);
  274. writeb (0, port[num].ioaddr.lbam_addr);
  275. writeb (0, port[num].ioaddr.lbah_addr);
  276. writeb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
  277. writeb (ATA_CMD_CHK_POWER, port[num].ioaddr.command_addr);
  278. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000, 0);
  279. if ((status & (ATA_BUSY | ATA_ERR))) {
  280. printf
  281. ("Error waiting for check power mode complete : status 0x%02x\n",
  282. status);
  283. port[num].dev_mask &= ~0x01;
  284. return 1;
  285. }
  286. res = readb (port[num].ioaddr.nsect_addr);
  287. debug ("Check powermode: %d\n", res);
  288. return res;
  289. }
  290. static void sata_port (struct sata_ioports *ioport)
  291. {
  292. ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
  293. ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
  294. ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
  295. ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
  296. ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
  297. ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
  298. ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
  299. ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
  300. ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
  301. ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
  302. }
  303. static u8 wait_for_irq (int num, unsigned int max)
  304. {
  305. u32 port = iobase[5];
  306. switch (num) {
  307. case 0:
  308. port += VND_TF_CNST_CH0;
  309. break;
  310. case 1:
  311. port += VND_TF_CNST_CH1;
  312. break;
  313. case 2:
  314. port += VND_TF_CNST_CH2;
  315. break;
  316. case 3:
  317. port += VND_TF_CNST_CH3;
  318. break;
  319. default:
  320. return 1;
  321. }
  322. do {
  323. if (readl (port) & VND_TF_CNST_INTST) {
  324. break;
  325. }
  326. udelay (1000);
  327. max--;
  328. } while ((max > 0));
  329. return (max == 0);
  330. }
  331. static u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits,
  332. unsigned int max, u8 usealtstatus)
  333. {
  334. u8 status;
  335. do {
  336. if (!((status = sata_chk_status (ioaddr, usealtstatus)) & bits)) {
  337. break;
  338. }
  339. udelay (1000);
  340. max--;
  341. } while ((status & bits) && (max > 0));
  342. return status;
  343. }
  344. static u8 sata_chk_status (struct sata_ioports *ioaddr, u8 usealtstatus)
  345. {
  346. if (!usealtstatus) {
  347. return readb (ioaddr->status_addr);
  348. } else {
  349. return readb (ioaddr->altstatus_addr);
  350. }
  351. }
  352. static void msleep (int count)
  353. {
  354. int i;
  355. for (i = 0; i < count; i++)
  356. udelay (1000);
  357. }
  358. /* Read up to 255 sectors
  359. *
  360. * Returns sectors read
  361. */
  362. static u8 do_one_read (int device, ulong block, u8 blkcnt, u16 * buff,
  363. uchar lba48)
  364. {
  365. u8 sr = 0;
  366. u8 status;
  367. u64 blknr = (u64) block;
  368. if (!(sata_chk_status (&port[device].ioaddr, 0) & ATA_DRDY)) {
  369. printf ("Device ata%d not ready\n", device);
  370. return 0;
  371. }
  372. /* Set up transfer */
  373. #ifdef CONFIG_LBA48
  374. if (lba48) {
  375. /* write high bits */
  376. writeb (0, port[device].ioaddr.nsect_addr);
  377. writeb ((blknr >> 24) & 0xFF, port[device].ioaddr.lbal_addr);
  378. writeb ((blknr >> 32) & 0xFF, port[device].ioaddr.lbam_addr);
  379. writeb ((blknr >> 40) & 0xFF, port[device].ioaddr.lbah_addr);
  380. }
  381. #endif
  382. writeb (blkcnt, port[device].ioaddr.nsect_addr);
  383. writeb (((blknr) >> 0) & 0xFF, port[device].ioaddr.lbal_addr);
  384. writeb ((blknr >> 8) & 0xFF, port[device].ioaddr.lbam_addr);
  385. writeb ((blknr >> 16) & 0xFF, port[device].ioaddr.lbah_addr);
  386. #ifdef CONFIG_LBA48
  387. if (lba48) {
  388. writeb (ATA_LBA, port[device].ioaddr.device_addr);
  389. writeb (ATA_CMD_PIO_READ_EXT, port[device].ioaddr.command_addr);
  390. } else
  391. #endif
  392. {
  393. writeb (ATA_LBA | ((blknr >> 24) & 0xF),
  394. port[device].ioaddr.device_addr);
  395. writeb (ATA_CMD_PIO_READ, port[device].ioaddr.command_addr);
  396. }
  397. status = sata_busy_wait (&port[device].ioaddr, ATA_BUSY, 10000, 1);
  398. if (status & ATA_BUSY) {
  399. u8 err = 0;
  400. printf ("Device %d not responding status %d\n", device, status);
  401. err = readb (port[device].ioaddr.error_addr);
  402. printf ("Error reg = 0x%x\n", err);
  403. return (sr);
  404. }
  405. while (blkcnt--) {
  406. if (wait_for_irq (device, 500)) {
  407. printf ("ata%u irq failed\n", device);
  408. return sr;
  409. }
  410. status = sata_chk_status (&port[device].ioaddr, 0);
  411. if (status & ATA_ERR) {
  412. printf ("ata%u error %d\n", device,
  413. readb (port[device].ioaddr.error_addr));
  414. return sr;
  415. }
  416. /* Read one sector */
  417. input_data (&port[device].ioaddr, buff, ATA_SECTOR_WORDS);
  418. buff += ATA_SECTOR_WORDS;
  419. sr++;
  420. }
  421. return sr;
  422. }
  423. ulong sata_read (int device, ulong block, lbaint_t blkcnt, void *buff)
  424. {
  425. ulong n = 0, sread;
  426. u16 *buffer = (u16 *) buff;
  427. u8 status = 0;
  428. u64 blknr = (u64) block;
  429. unsigned char lba48 = 0;
  430. #ifdef CONFIG_LBA48
  431. if (blknr > 0xfffffff) {
  432. if (!sata_dev_desc[device].lba48) {
  433. printf ("Drive doesn't support 48-bit addressing\n");
  434. return 0;
  435. }
  436. /* more than 28 bits used, use 48bit mode */
  437. lba48 = 1;
  438. }
  439. #endif
  440. while (blkcnt > 0) {
  441. if (blkcnt > 255) {
  442. sread = 255;
  443. } else {
  444. sread = blkcnt;
  445. }
  446. status = do_one_read (device, blknr, sread, buffer, lba48);
  447. if (status != sread) {
  448. printf ("Read failed\n");
  449. return n;
  450. }
  451. blkcnt -= sread;
  452. blknr += sread;
  453. n += sread;
  454. buffer += sread * ATA_SECTOR_WORDS;
  455. }
  456. return n;
  457. }
  458. ulong sata_write (int device, ulong block, lbaint_t blkcnt, const void *buff)
  459. {
  460. ulong n = 0;
  461. u16 *buffer = (u16 *) buff;
  462. unsigned char status = 0, num = 0;
  463. u64 blknr = (u64) block;
  464. #ifdef CONFIG_LBA48
  465. unsigned char lba48 = 0;
  466. if (blknr > 0xfffffff) {
  467. if (!sata_dev_desc[device].lba48) {
  468. printf ("Drive doesn't support 48-bit addressing\n");
  469. return 0;
  470. }
  471. /* more than 28 bits used, use 48bit mode */
  472. lba48 = 1;
  473. }
  474. #endif
  475. /*Port Number */
  476. num = device;
  477. while (blkcnt-- > 0) {
  478. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500, 0);
  479. if (status & ATA_BUSY) {
  480. printf ("ata%u failed to respond\n", port[num].port_no);
  481. return n;
  482. }
  483. #ifdef CONFIG_LBA48
  484. if (lba48) {
  485. /* write high bits */
  486. writeb (0, port[num].ioaddr.nsect_addr);
  487. writeb ((blknr >> 24) & 0xFF,
  488. port[num].ioaddr.lbal_addr);
  489. writeb ((blknr >> 32) & 0xFF,
  490. port[num].ioaddr.lbam_addr);
  491. writeb ((blknr >> 40) & 0xFF,
  492. port[num].ioaddr.lbah_addr);
  493. }
  494. #endif
  495. writeb (1, port[num].ioaddr.nsect_addr);
  496. writeb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
  497. writeb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
  498. writeb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
  499. #ifdef CONFIG_LBA48
  500. if (lba48) {
  501. writeb (ATA_LBA, port[num].ioaddr.device_addr);
  502. writeb (ATA_CMD_PIO_WRITE_EXT, port[num].ioaddr.command_addr);
  503. } else
  504. #endif
  505. {
  506. writeb (ATA_LBA | ((blknr >> 24) & 0xF),
  507. port[num].ioaddr.device_addr);
  508. writeb (ATA_CMD_PIO_WRITE, port[num].ioaddr.command_addr);
  509. }
  510. msleep (50);
  511. /*may take up to 4 sec */
  512. status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000, 0);
  513. if ((status & (ATA_DRQ | ATA_BUSY | ATA_ERR)) != ATA_DRQ) {
  514. printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
  515. device, (ulong) blknr, status);
  516. return (n);
  517. }
  518. output_data (&port[num].ioaddr, buffer, ATA_SECTOR_WORDS);
  519. readb (port[num].ioaddr.altstatus_addr);
  520. udelay (50);
  521. ++n;
  522. ++blknr;
  523. buffer += ATA_SECTOR_WORDS;
  524. }
  525. return n;
  526. }
  527. /* Driver implementation */
  528. static u8 sil_get_device_cache_line (pci_dev_t pdev)
  529. {
  530. u8 cache_line = 0;
  531. pci_read_config_byte (pdev, PCI_CACHE_LINE_SIZE, &cache_line);
  532. return cache_line;
  533. }
  534. int init_sata (int dev)
  535. {
  536. static u8 init_done = 0;
  537. static int res = 1;
  538. pci_dev_t devno;
  539. u8 cls = 0;
  540. u16 cmd = 0;
  541. u32 sconf = 0;
  542. if (init_done) {
  543. return res;
  544. }
  545. init_done = 1;
  546. if ((devno = pci_find_device (SIL_VEND_ID, SIL3114_DEVICE_ID, 0)) == -1) {
  547. res = 1;
  548. return res;
  549. }
  550. /* Read out all BARs, even though we only use MMIO from BAR5 */
  551. pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase[0]);
  552. pci_read_config_dword (devno, PCI_BASE_ADDRESS_1, &iobase[1]);
  553. pci_read_config_dword (devno, PCI_BASE_ADDRESS_2, &iobase[2]);
  554. pci_read_config_dword (devno, PCI_BASE_ADDRESS_3, &iobase[3]);
  555. pci_read_config_dword (devno, PCI_BASE_ADDRESS_4, &iobase[4]);
  556. pci_read_config_dword (devno, PCI_BASE_ADDRESS_5, &iobase[5]);
  557. if ((iobase[0] == 0xFFFFFFFF) || (iobase[1] == 0xFFFFFFFF) ||
  558. (iobase[2] == 0xFFFFFFFF) || (iobase[3] == 0xFFFFFFFF) ||
  559. (iobase[4] == 0xFFFFFFFF) || (iobase[5] == 0xFFFFFFFF)) {
  560. printf ("Error no base addr for SATA controller\n");
  561. res = 1;
  562. return res;
  563. }
  564. /* mask off unused bits */
  565. iobase[0] &= 0xfffffffc;
  566. iobase[1] &= 0xfffffff8;
  567. iobase[2] &= 0xfffffffc;
  568. iobase[3] &= 0xfffffff8;
  569. iobase[4] &= 0xfffffff0;
  570. iobase[5] &= 0xfffffc00;
  571. /* from sata_sil in Linux kernel */
  572. cls = sil_get_device_cache_line (devno);
  573. if (cls) {
  574. cls >>= 3;
  575. cls++; /* cls = (line_size/8)+1 */
  576. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH0);
  577. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH1);
  578. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH2);
  579. writel (cls << 8 | cls, iobase[5] + VND_FIFOCFG_CH3);
  580. } else {
  581. printf ("Cache line not set. Driver may not function\n");
  582. }
  583. /* Enable operation */
  584. pci_read_config_word (devno, PCI_COMMAND, &cmd);
  585. cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  586. pci_write_config_word (devno, PCI_COMMAND, cmd);
  587. /* Disable interrupt usage */
  588. pci_read_config_dword (devno, VND_SYSCONFSTAT, &sconf);
  589. sconf |= (VND_SYSCONFSTAT_CHN_0_INTBLOCK | VND_SYSCONFSTAT_CHN_1_INTBLOCK);
  590. pci_write_config_dword (devno, VND_SYSCONFSTAT, sconf);
  591. res = 0;
  592. return res;
  593. }
  594. int reset_sata(int dev)
  595. {
  596. return 0;
  597. }
  598. /* Check if device is connected to port */
  599. int sata_bus_probe (int portno)
  600. {
  601. u32 port = iobase[5];
  602. u32 val;
  603. switch (portno) {
  604. case 0:
  605. port += VND_SSTATUS_CH0;
  606. break;
  607. case 1:
  608. port += VND_SSTATUS_CH1;
  609. break;
  610. case 2:
  611. port += VND_SSTATUS_CH2;
  612. break;
  613. case 3:
  614. port += VND_SSTATUS_CH3;
  615. break;
  616. default:
  617. return 0;
  618. }
  619. val = readl (port);
  620. if ((val & SATA_DET_PRES) == SATA_DET_PRES) {
  621. return 1;
  622. } else {
  623. return 0;
  624. }
  625. }
  626. int sata_phy_reset (int portno)
  627. {
  628. u32 port = iobase[5];
  629. u32 val;
  630. switch (portno) {
  631. case 0:
  632. port += VND_SCONTROL_CH0;
  633. break;
  634. case 1:
  635. port += VND_SCONTROL_CH1;
  636. break;
  637. case 2:
  638. port += VND_SCONTROL_CH2;
  639. break;
  640. case 3:
  641. port += VND_SCONTROL_CH3;
  642. break;
  643. default:
  644. return 0;
  645. }
  646. val = readl (port);
  647. writel (val | SATA_SC_DET_RST, port);
  648. msleep (150);
  649. writel (val & ~SATA_SC_DET_RST, port);
  650. return 0;
  651. }
  652. int scan_sata (int dev)
  653. {
  654. /* A bit brain dead, but the code has a legacy */
  655. switch (dev) {
  656. case 0:
  657. port[0].port_no = 0;
  658. port[0].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH0;
  659. port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
  660. (iobase[5] + VND_TF2_CH0) | ATA_PCI_CTL_OFS;
  661. port[0].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH0;
  662. break;
  663. #if (CONFIG_SYS_SATA_MAX_DEVICE >= 1)
  664. case 1:
  665. port[1].port_no = 0;
  666. port[1].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH1;
  667. port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
  668. (iobase[5] + VND_TF2_CH1) | ATA_PCI_CTL_OFS;
  669. port[1].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH1;
  670. break;
  671. #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 2)
  672. case 2:
  673. port[2].port_no = 0;
  674. port[2].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH2;
  675. port[2].ioaddr.altstatus_addr = port[2].ioaddr.ctl_addr =
  676. (iobase[5] + VND_TF2_CH2) | ATA_PCI_CTL_OFS;
  677. port[2].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH2;
  678. break;
  679. #elif (CONFIG_SYS_SATA_MAX_DEVICE >= 3)
  680. case 3:
  681. port[3].port_no = 0;
  682. port[3].ioaddr.cmd_addr = iobase[5] + VND_TF0_CH3;
  683. port[3].ioaddr.altstatus_addr = port[3].ioaddr.ctl_addr =
  684. (iobase[5] + VND_TF2_CH3) | ATA_PCI_CTL_OFS;
  685. port[3].ioaddr.bmdma_addr = iobase[5] + VND_BMDMA_CH3;
  686. break;
  687. #endif
  688. default:
  689. printf ("Tried to scan unknown port: ata%d\n", dev);
  690. return 1;
  691. }
  692. /* Initialize other registers */
  693. sata_port (&port[dev].ioaddr);
  694. /* Check for attached device */
  695. if (!sata_bus_probe (dev)) {
  696. port[dev].port_state = 0;
  697. debug ("SATA#%d port is not present\n", dev);
  698. } else {
  699. debug ("SATA#%d port is present\n", dev);
  700. if (sata_bus_softreset (dev)) {
  701. /* soft reset failed, try a hard one */
  702. sata_phy_reset (dev);
  703. if (sata_bus_softreset (dev)) {
  704. port[dev].port_state = 0;
  705. } else {
  706. port[dev].port_state = 1;
  707. }
  708. } else {
  709. port[dev].port_state = 1;
  710. }
  711. }
  712. if (port[dev].port_state == 1) {
  713. /* Probe device and set xfer mode */
  714. sata_identify (dev, 0);
  715. set_Feature_cmd (dev, 0);
  716. }
  717. return 0;
  718. }