sata_mv.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Excito Elektronik i Skåne AB, 2010.
  4. * Author: Tor Krill <tor@excito.com>
  5. *
  6. * Copyright (C) 2015, 2019 Stefan Roese <sr@denx.de>
  7. */
  8. /*
  9. * This driver supports the SATA controller of some Mavell SoC's.
  10. * Here a (most likely incomplete) list of the supported SoC's:
  11. * - Kirkwood
  12. * - Armada 370
  13. * - Armada XP
  14. *
  15. * This driver implementation is an alternative to the already available
  16. * driver via the "ide" commands interface (drivers/block/mvsata_ide.c).
  17. * But this driver only supports PIO mode and as this new driver also
  18. * supports transfer via DMA, its much faster.
  19. *
  20. * Please note, that the newer SoC's (e.g. Armada 38x) are not supported
  21. * by this driver. As they have an AHCI compatible SATA controller
  22. * integrated.
  23. */
  24. /*
  25. * TODO:
  26. * Better error recovery
  27. * No support for using PRDs (Thus max 64KB transfers)
  28. * No NCQ support
  29. * No port multiplier support
  30. */
  31. #include <common.h>
  32. #include <ahci.h>
  33. #include <blk.h>
  34. #include <cpu_func.h>
  35. #include <dm.h>
  36. #include <asm/cache.h>
  37. #include <dm/device-internal.h>
  38. #include <dm/lists.h>
  39. #include <fis.h>
  40. #include <libata.h>
  41. #include <malloc.h>
  42. #include <sata.h>
  43. #include <linux/errno.h>
  44. #include <asm/io.h>
  45. #include <linux/mbus.h>
  46. #include <asm/arch/soc.h>
  47. #if defined(CONFIG_ARCH_KIRKWOOD)
  48. #define SATAHC_BASE KW_SATA_BASE
  49. #else
  50. #define SATAHC_BASE MVEBU_AXP_SATA_BASE
  51. #endif
  52. #define SATA0_BASE (SATAHC_BASE + 0x2000)
  53. #define SATA1_BASE (SATAHC_BASE + 0x4000)
  54. /* EDMA registers */
  55. #define EDMA_CFG 0x000
  56. #define EDMA_CFG_NCQ (1 << 5)
  57. #define EDMA_CFG_EQUE (1 << 9)
  58. #define EDMA_TIMER 0x004
  59. #define EDMA_IECR 0x008
  60. #define EDMA_IEMR 0x00c
  61. #define EDMA_RQBA_HI 0x010
  62. #define EDMA_RQIPR 0x014
  63. #define EDMA_RQIPR_IPMASK (0x1f << 5)
  64. #define EDMA_RQIPR_IPSHIFT 5
  65. #define EDMA_RQOPR 0x018
  66. #define EDMA_RQOPR_OPMASK (0x1f << 5)
  67. #define EDMA_RQOPR_OPSHIFT 5
  68. #define EDMA_RSBA_HI 0x01c
  69. #define EDMA_RSIPR 0x020
  70. #define EDMA_RSIPR_IPMASK (0x1f << 3)
  71. #define EDMA_RSIPR_IPSHIFT 3
  72. #define EDMA_RSOPR 0x024
  73. #define EDMA_RSOPR_OPMASK (0x1f << 3)
  74. #define EDMA_RSOPR_OPSHIFT 3
  75. #define EDMA_CMD 0x028
  76. #define EDMA_CMD_ENEDMA (0x01 << 0)
  77. #define EDMA_CMD_DISEDMA (0x01 << 1)
  78. #define EDMA_CMD_ATARST (0x01 << 2)
  79. #define EDMA_CMD_FREEZE (0x01 << 4)
  80. #define EDMA_TEST_CTL 0x02c
  81. #define EDMA_STATUS 0x030
  82. #define EDMA_IORTO 0x034
  83. #define EDMA_CDTR 0x040
  84. #define EDMA_HLTCND 0x060
  85. #define EDMA_NTSR 0x094
  86. /* Basic DMA registers */
  87. #define BDMA_CMD 0x224
  88. #define BDMA_STATUS 0x228
  89. #define BDMA_DTLB 0x22c
  90. #define BDMA_DTHB 0x230
  91. #define BDMA_DRL 0x234
  92. #define BDMA_DRH 0x238
  93. /* SATA Interface registers */
  94. #define SIR_ICFG 0x050
  95. #define SIR_CFG_GEN2EN (0x1 << 7)
  96. #define SIR_PLL_CFG 0x054
  97. #define SIR_SSTATUS 0x300
  98. #define SSTATUS_DET_MASK (0x0f << 0)
  99. #define SIR_SERROR 0x304
  100. #define SIR_SCONTROL 0x308
  101. #define SIR_SCONTROL_DETEN (0x01 << 0)
  102. #define SIR_LTMODE 0x30c
  103. #define SIR_LTMODE_NELBE (0x01 << 7)
  104. #define SIR_PHYMODE3 0x310
  105. #define SIR_PHYMODE4 0x314
  106. #define SIR_PHYMODE1 0x32c
  107. #define SIR_PHYMODE2 0x330
  108. #define SIR_BIST_CTRL 0x334
  109. #define SIR_BIST_DW1 0x338
  110. #define SIR_BIST_DW2 0x33c
  111. #define SIR_SERR_IRQ_MASK 0x340
  112. #define SIR_SATA_IFCTRL 0x344
  113. #define SIR_SATA_TESTCTRL 0x348
  114. #define SIR_SATA_IFSTATUS 0x34c
  115. #define SIR_VEND_UNIQ 0x35c
  116. #define SIR_FIS_CFG 0x360
  117. #define SIR_FIS_IRQ_CAUSE 0x364
  118. #define SIR_FIS_IRQ_MASK 0x368
  119. #define SIR_FIS_DWORD0 0x370
  120. #define SIR_FIS_DWORD1 0x374
  121. #define SIR_FIS_DWORD2 0x378
  122. #define SIR_FIS_DWORD3 0x37c
  123. #define SIR_FIS_DWORD4 0x380
  124. #define SIR_FIS_DWORD5 0x384
  125. #define SIR_FIS_DWORD6 0x388
  126. #define SIR_PHYM9_GEN2 0x398
  127. #define SIR_PHYM9_GEN1 0x39c
  128. #define SIR_PHY_CFG 0x3a0
  129. #define SIR_PHYCTL 0x3a4
  130. #define SIR_PHYM10 0x3a8
  131. #define SIR_PHYM12 0x3b0
  132. /* Shadow registers */
  133. #define PIO_DATA 0x100
  134. #define PIO_ERR_FEATURES 0x104
  135. #define PIO_SECTOR_COUNT 0x108
  136. #define PIO_LBA_LOW 0x10c
  137. #define PIO_LBA_MID 0x110
  138. #define PIO_LBA_HI 0x114
  139. #define PIO_DEVICE 0x118
  140. #define PIO_CMD_STATUS 0x11c
  141. #define PIO_STATUS_ERR (0x01 << 0)
  142. #define PIO_STATUS_DRQ (0x01 << 3)
  143. #define PIO_STATUS_DF (0x01 << 5)
  144. #define PIO_STATUS_DRDY (0x01 << 6)
  145. #define PIO_STATUS_BSY (0x01 << 7)
  146. #define PIO_CTRL_ALTSTAT 0x120
  147. /* SATAHC arbiter registers */
  148. #define SATAHC_CFG 0x000
  149. #define SATAHC_RQOP 0x004
  150. #define SATAHC_RQIP 0x008
  151. #define SATAHC_ICT 0x00c
  152. #define SATAHC_ITT 0x010
  153. #define SATAHC_ICR 0x014
  154. #define SATAHC_ICR_PORT0 (0x01 << 0)
  155. #define SATAHC_ICR_PORT1 (0x01 << 1)
  156. #define SATAHC_MIC 0x020
  157. #define SATAHC_MIM 0x024
  158. #define SATAHC_LED_CFG 0x02c
  159. #define REQUEST_QUEUE_SIZE 32
  160. #define RESPONSE_QUEUE_SIZE REQUEST_QUEUE_SIZE
  161. struct crqb {
  162. u32 dtb_low; /* DW0 */
  163. u32 dtb_high; /* DW1 */
  164. u32 control_flags; /* DW2 */
  165. u32 drb_count; /* DW3 */
  166. u32 ata_cmd_feat; /* DW4 */
  167. u32 ata_addr; /* DW5 */
  168. u32 ata_addr_exp; /* DW6 */
  169. u32 ata_sect_count; /* DW7 */
  170. };
  171. #define CRQB_ALIGN 0x400
  172. #define CRQB_CNTRLFLAGS_DIR (0x01 << 0)
  173. #define CRQB_CNTRLFLAGS_DQTAGMASK (0x1f << 1)
  174. #define CRQB_CNTRLFLAGS_DQTAGSHIFT 1
  175. #define CRQB_CNTRLFLAGS_PMPORTMASK (0x0f << 12)
  176. #define CRQB_CNTRLFLAGS_PMPORTSHIFT 12
  177. #define CRQB_CNTRLFLAGS_PRDMODE (0x01 << 16)
  178. #define CRQB_CNTRLFLAGS_HQTAGMASK (0x1f << 17)
  179. #define CRQB_CNTRLFLAGS_HQTAGSHIFT 17
  180. #define CRQB_CMDFEAT_CMDMASK (0xff << 16)
  181. #define CRQB_CMDFEAT_CMDSHIFT 16
  182. #define CRQB_CMDFEAT_FEATMASK (0xff << 16)
  183. #define CRQB_CMDFEAT_FEATSHIFT 24
  184. #define CRQB_ADDR_LBA_LOWMASK (0xff << 0)
  185. #define CRQB_ADDR_LBA_LOWSHIFT 0
  186. #define CRQB_ADDR_LBA_MIDMASK (0xff << 8)
  187. #define CRQB_ADDR_LBA_MIDSHIFT 8
  188. #define CRQB_ADDR_LBA_HIGHMASK (0xff << 16)
  189. #define CRQB_ADDR_LBA_HIGHSHIFT 16
  190. #define CRQB_ADDR_DEVICE_MASK (0xff << 24)
  191. #define CRQB_ADDR_DEVICE_SHIFT 24
  192. #define CRQB_ADDR_LBA_LOW_EXP_MASK (0xff << 0)
  193. #define CRQB_ADDR_LBA_LOW_EXP_SHIFT 0
  194. #define CRQB_ADDR_LBA_MID_EXP_MASK (0xff << 8)
  195. #define CRQB_ADDR_LBA_MID_EXP_SHIFT 8
  196. #define CRQB_ADDR_LBA_HIGH_EXP_MASK (0xff << 16)
  197. #define CRQB_ADDR_LBA_HIGH_EXP_SHIFT 16
  198. #define CRQB_ADDR_FEATURE_EXP_MASK (0xff << 24)
  199. #define CRQB_ADDR_FEATURE_EXP_SHIFT 24
  200. #define CRQB_SECTCOUNT_COUNT_MASK (0xff << 0)
  201. #define CRQB_SECTCOUNT_COUNT_SHIFT 0
  202. #define CRQB_SECTCOUNT_COUNT_EXP_MASK (0xff << 8)
  203. #define CRQB_SECTCOUNT_COUNT_EXP_SHIFT 8
  204. #define MVSATA_WIN_CONTROL(w) (SATAHC_BASE + 0x30 + ((w) << 4))
  205. #define MVSATA_WIN_BASE(w) (SATAHC_BASE + 0x34 + ((w) << 4))
  206. struct eprd {
  207. u32 phyaddr_low;
  208. u32 bytecount_eot;
  209. u32 phyaddr_hi;
  210. u32 reserved;
  211. };
  212. #define EPRD_PHYADDR_MASK 0xfffffffe
  213. #define EPRD_BYTECOUNT_MASK 0x0000ffff
  214. #define EPRD_EOT (0x01 << 31)
  215. struct crpb {
  216. u32 id;
  217. u32 flags;
  218. u32 timestamp;
  219. };
  220. #define CRPB_ALIGN 0x100
  221. #define READ_CMD 0
  222. #define WRITE_CMD 1
  223. /*
  224. * Since we don't use PRDs yet max transfer size
  225. * is 64KB
  226. */
  227. #define MV_ATA_MAX_SECTORS (65535 / ATA_SECT_SIZE)
  228. /* Keep track if hw is initialized or not */
  229. static u32 hw_init;
  230. struct mv_priv {
  231. char name[12];
  232. u32 link;
  233. u32 regbase;
  234. u32 queue_depth;
  235. u16 pio;
  236. u16 mwdma;
  237. u16 udma;
  238. int dev_nr;
  239. void *crqb_alloc;
  240. struct crqb *request;
  241. void *crpb_alloc;
  242. struct crpb *response;
  243. };
  244. static int ata_wait_register(u32 *addr, u32 mask, u32 val, u32 timeout_msec)
  245. {
  246. ulong start;
  247. start = get_timer(0);
  248. do {
  249. if ((in_le32(addr) & mask) == val)
  250. return 0;
  251. } while (get_timer(start) < timeout_msec);
  252. return -ETIMEDOUT;
  253. }
  254. /* Cut from sata_mv in linux kernel */
  255. static int mv_stop_edma_engine(struct udevice *dev, int port)
  256. {
  257. struct mv_priv *priv = dev_get_platdata(dev);
  258. int i;
  259. /* Disable eDMA. The disable bit auto clears. */
  260. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_DISEDMA);
  261. /* Wait for the chip to confirm eDMA is off. */
  262. for (i = 10000; i > 0; i--) {
  263. u32 reg = in_le32(priv->regbase + EDMA_CMD);
  264. if (!(reg & EDMA_CMD_ENEDMA)) {
  265. debug("EDMA stop on port %d succesful\n", port);
  266. return 0;
  267. }
  268. udelay(10);
  269. }
  270. debug("EDMA stop on port %d failed\n", port);
  271. return -1;
  272. }
  273. static int mv_start_edma_engine(struct udevice *dev, int port)
  274. {
  275. struct mv_priv *priv = dev_get_platdata(dev);
  276. u32 tmp;
  277. /* Check preconditions */
  278. tmp = in_le32(priv->regbase + SIR_SSTATUS);
  279. if ((tmp & SSTATUS_DET_MASK) != 0x03) {
  280. printf("Device error on port: %d\n", port);
  281. return -1;
  282. }
  283. tmp = in_le32(priv->regbase + PIO_CMD_STATUS);
  284. if (tmp & (ATA_BUSY | ATA_DRQ)) {
  285. printf("Device not ready on port: %d\n", port);
  286. return -1;
  287. }
  288. /* Clear interrupt cause */
  289. out_le32(priv->regbase + EDMA_IECR, 0x0);
  290. tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
  291. tmp &= ~(port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1);
  292. out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
  293. /* Configure edma operation */
  294. tmp = in_le32(priv->regbase + EDMA_CFG);
  295. tmp &= ~EDMA_CFG_NCQ; /* No NCQ */
  296. tmp &= ~EDMA_CFG_EQUE; /* Dont queue operations */
  297. out_le32(priv->regbase + EDMA_CFG, tmp);
  298. out_le32(priv->regbase + SIR_FIS_IRQ_CAUSE, 0x0);
  299. /* Configure fis, set all to no-wait for now */
  300. out_le32(priv->regbase + SIR_FIS_CFG, 0x0);
  301. /* Setup request queue */
  302. out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
  303. out_le32(priv->regbase + EDMA_RQIPR, priv->request);
  304. out_le32(priv->regbase + EDMA_RQOPR, 0x0);
  305. /* Setup response queue */
  306. out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
  307. out_le32(priv->regbase + EDMA_RSOPR, priv->response);
  308. out_le32(priv->regbase + EDMA_RSIPR, 0x0);
  309. /* Start edma */
  310. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ENEDMA);
  311. return 0;
  312. }
  313. static int mv_reset_channel(struct udevice *dev, int port)
  314. {
  315. struct mv_priv *priv = dev_get_platdata(dev);
  316. /* Make sure edma is stopped */
  317. mv_stop_edma_engine(dev, port);
  318. out_le32(priv->regbase + EDMA_CMD, EDMA_CMD_ATARST);
  319. udelay(25); /* allow reset propagation */
  320. out_le32(priv->regbase + EDMA_CMD, 0);
  321. mdelay(10);
  322. return 0;
  323. }
  324. static void mv_reset_port(struct udevice *dev, int port)
  325. {
  326. struct mv_priv *priv = dev_get_platdata(dev);
  327. mv_reset_channel(dev, port);
  328. out_le32(priv->regbase + EDMA_CMD, 0x0);
  329. out_le32(priv->regbase + EDMA_CFG, 0x101f);
  330. out_le32(priv->regbase + EDMA_IECR, 0x0);
  331. out_le32(priv->regbase + EDMA_IEMR, 0x0);
  332. out_le32(priv->regbase + EDMA_RQBA_HI, 0x0);
  333. out_le32(priv->regbase + EDMA_RQIPR, 0x0);
  334. out_le32(priv->regbase + EDMA_RQOPR, 0x0);
  335. out_le32(priv->regbase + EDMA_RSBA_HI, 0x0);
  336. out_le32(priv->regbase + EDMA_RSIPR, 0x0);
  337. out_le32(priv->regbase + EDMA_RSOPR, 0x0);
  338. out_le32(priv->regbase + EDMA_IORTO, 0xfa);
  339. }
  340. static void mv_reset_one_hc(void)
  341. {
  342. out_le32(SATAHC_BASE + SATAHC_ICT, 0x00);
  343. out_le32(SATAHC_BASE + SATAHC_ITT, 0x00);
  344. out_le32(SATAHC_BASE + SATAHC_ICR, 0x00);
  345. }
  346. static int probe_port(struct udevice *dev, int port)
  347. {
  348. struct mv_priv *priv = dev_get_platdata(dev);
  349. int tries, tries2, set15 = 0;
  350. u32 tmp;
  351. debug("Probe port: %d\n", port);
  352. for (tries = 0; tries < 2; tries++) {
  353. /* Clear SError */
  354. out_le32(priv->regbase + SIR_SERROR, 0x0);
  355. /* trigger com-init */
  356. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  357. tmp = (tmp & 0x0f0) | 0x300 | SIR_SCONTROL_DETEN;
  358. out_le32(priv->regbase + SIR_SCONTROL, tmp);
  359. mdelay(1);
  360. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  361. tries2 = 5;
  362. do {
  363. tmp = (tmp & 0x0f0) | 0x300;
  364. out_le32(priv->regbase + SIR_SCONTROL, tmp);
  365. mdelay(10);
  366. tmp = in_le32(priv->regbase + SIR_SCONTROL);
  367. } while ((tmp & 0xf0f) != 0x300 && tries2--);
  368. mdelay(10);
  369. for (tries2 = 0; tries2 < 200; tries2++) {
  370. tmp = in_le32(priv->regbase + SIR_SSTATUS);
  371. if ((tmp & SSTATUS_DET_MASK) == 0x03) {
  372. debug("Found device on port\n");
  373. return 0;
  374. }
  375. mdelay(1);
  376. }
  377. if ((tmp & SSTATUS_DET_MASK) == 0) {
  378. debug("No device attached on port %d\n", port);
  379. return -ENODEV;
  380. }
  381. if (!set15) {
  382. /* Try on 1.5Gb/S */
  383. debug("Try 1.5Gb link\n");
  384. set15 = 1;
  385. out_le32(priv->regbase + SIR_SCONTROL, 0x304);
  386. tmp = in_le32(priv->regbase + SIR_ICFG);
  387. tmp &= ~SIR_CFG_GEN2EN;
  388. out_le32(priv->regbase + SIR_ICFG, tmp);
  389. mv_reset_channel(dev, port);
  390. }
  391. }
  392. debug("Failed to probe port\n");
  393. return -1;
  394. }
  395. /* Get request queue in pointer */
  396. static int get_reqip(struct udevice *dev, int port)
  397. {
  398. struct mv_priv *priv = dev_get_platdata(dev);
  399. u32 tmp;
  400. tmp = in_le32(priv->regbase + EDMA_RQIPR) & EDMA_RQIPR_IPMASK;
  401. tmp = tmp >> EDMA_RQIPR_IPSHIFT;
  402. return tmp;
  403. }
  404. static void set_reqip(struct udevice *dev, int port, int reqin)
  405. {
  406. struct mv_priv *priv = dev_get_platdata(dev);
  407. u32 tmp;
  408. tmp = in_le32(priv->regbase + EDMA_RQIPR) & ~EDMA_RQIPR_IPMASK;
  409. tmp |= ((reqin << EDMA_RQIPR_IPSHIFT) & EDMA_RQIPR_IPMASK);
  410. out_le32(priv->regbase + EDMA_RQIPR, tmp);
  411. }
  412. /* Get next available slot, ignoring possible overwrite */
  413. static int get_next_reqip(struct udevice *dev, int port)
  414. {
  415. int slot = get_reqip(dev, port);
  416. slot = (slot + 1) % REQUEST_QUEUE_SIZE;
  417. return slot;
  418. }
  419. /* Get response queue in pointer */
  420. static int get_rspip(struct udevice *dev, int port)
  421. {
  422. struct mv_priv *priv = dev_get_platdata(dev);
  423. u32 tmp;
  424. tmp = in_le32(priv->regbase + EDMA_RSIPR) & EDMA_RSIPR_IPMASK;
  425. tmp = tmp >> EDMA_RSIPR_IPSHIFT;
  426. return tmp;
  427. }
  428. /* Get response queue out pointer */
  429. static int get_rspop(struct udevice *dev, int port)
  430. {
  431. struct mv_priv *priv = dev_get_platdata(dev);
  432. u32 tmp;
  433. tmp = in_le32(priv->regbase + EDMA_RSOPR) & EDMA_RSOPR_OPMASK;
  434. tmp = tmp >> EDMA_RSOPR_OPSHIFT;
  435. return tmp;
  436. }
  437. /* Get next response queue pointer */
  438. static int get_next_rspop(struct udevice *dev, int port)
  439. {
  440. return (get_rspop(dev, port) + 1) % RESPONSE_QUEUE_SIZE;
  441. }
  442. /* Set response queue pointer */
  443. static void set_rspop(struct udevice *dev, int port, int reqin)
  444. {
  445. struct mv_priv *priv = dev_get_platdata(dev);
  446. u32 tmp;
  447. tmp = in_le32(priv->regbase + EDMA_RSOPR) & ~EDMA_RSOPR_OPMASK;
  448. tmp |= ((reqin << EDMA_RSOPR_OPSHIFT) & EDMA_RSOPR_OPMASK);
  449. out_le32(priv->regbase + EDMA_RSOPR, tmp);
  450. }
  451. static int wait_dma_completion(struct udevice *dev, int port, int index,
  452. u32 timeout_msec)
  453. {
  454. u32 tmp, res;
  455. tmp = port == 0 ? SATAHC_ICR_PORT0 : SATAHC_ICR_PORT1;
  456. res = ata_wait_register((u32 *)(SATAHC_BASE + SATAHC_ICR), tmp,
  457. tmp, timeout_msec);
  458. if (res)
  459. printf("Failed to wait for completion on port %d\n", port);
  460. return res;
  461. }
  462. static void process_responses(struct udevice *dev, int port)
  463. {
  464. #ifdef DEBUG
  465. struct mv_priv *priv = dev_get_platdata(dev);
  466. #endif
  467. u32 tmp;
  468. u32 outind = get_rspop(dev, port);
  469. /* Ack interrupts */
  470. tmp = in_le32(SATAHC_BASE + SATAHC_ICR);
  471. if (port == 0)
  472. tmp &= ~(BIT(0) | BIT(8));
  473. else
  474. tmp &= ~(BIT(1) | BIT(9));
  475. tmp &= ~(BIT(4));
  476. out_le32(SATAHC_BASE + SATAHC_ICR, tmp);
  477. while (get_rspip(dev, port) != outind) {
  478. #ifdef DEBUG
  479. debug("Response index %d flags %08x on port %d\n", outind,
  480. priv->response[outind].flags, port);
  481. #endif
  482. outind = get_next_rspop(dev, port);
  483. set_rspop(dev, port, outind);
  484. }
  485. }
  486. static int mv_ata_exec_ata_cmd(struct udevice *dev, int port,
  487. struct sata_fis_h2d *cfis,
  488. u8 *buffer, u32 len, u32 iswrite)
  489. {
  490. struct mv_priv *priv = dev_get_platdata(dev);
  491. struct crqb *req;
  492. int slot;
  493. u32 start;
  494. if (len >= 64 * 1024) {
  495. printf("We only support <64K transfers for now\n");
  496. return -1;
  497. }
  498. /* Initialize request */
  499. slot = get_reqip(dev, port);
  500. memset(&priv->request[slot], 0, sizeof(struct crqb));
  501. req = &priv->request[slot];
  502. req->dtb_low = (u32)buffer;
  503. /* Dont use PRDs */
  504. req->control_flags = CRQB_CNTRLFLAGS_PRDMODE;
  505. req->control_flags |= iswrite ? 0 : CRQB_CNTRLFLAGS_DIR;
  506. req->control_flags |=
  507. ((cfis->pm_port_c << CRQB_CNTRLFLAGS_PMPORTSHIFT)
  508. & CRQB_CNTRLFLAGS_PMPORTMASK);
  509. req->drb_count = len;
  510. req->ata_cmd_feat = (cfis->command << CRQB_CMDFEAT_CMDSHIFT) &
  511. CRQB_CMDFEAT_CMDMASK;
  512. req->ata_cmd_feat |= (cfis->features << CRQB_CMDFEAT_FEATSHIFT) &
  513. CRQB_CMDFEAT_FEATMASK;
  514. req->ata_addr = (cfis->lba_low << CRQB_ADDR_LBA_LOWSHIFT) &
  515. CRQB_ADDR_LBA_LOWMASK;
  516. req->ata_addr |= (cfis->lba_mid << CRQB_ADDR_LBA_MIDSHIFT) &
  517. CRQB_ADDR_LBA_MIDMASK;
  518. req->ata_addr |= (cfis->lba_high << CRQB_ADDR_LBA_HIGHSHIFT) &
  519. CRQB_ADDR_LBA_HIGHMASK;
  520. req->ata_addr |= (cfis->device << CRQB_ADDR_DEVICE_SHIFT) &
  521. CRQB_ADDR_DEVICE_MASK;
  522. req->ata_addr_exp = (cfis->lba_low_exp << CRQB_ADDR_LBA_LOW_EXP_SHIFT) &
  523. CRQB_ADDR_LBA_LOW_EXP_MASK;
  524. req->ata_addr_exp |=
  525. (cfis->lba_mid_exp << CRQB_ADDR_LBA_MID_EXP_SHIFT) &
  526. CRQB_ADDR_LBA_MID_EXP_MASK;
  527. req->ata_addr_exp |=
  528. (cfis->lba_high_exp << CRQB_ADDR_LBA_HIGH_EXP_SHIFT) &
  529. CRQB_ADDR_LBA_HIGH_EXP_MASK;
  530. req->ata_addr_exp |=
  531. (cfis->features_exp << CRQB_ADDR_FEATURE_EXP_SHIFT) &
  532. CRQB_ADDR_FEATURE_EXP_MASK;
  533. req->ata_sect_count =
  534. (cfis->sector_count << CRQB_SECTCOUNT_COUNT_SHIFT) &
  535. CRQB_SECTCOUNT_COUNT_MASK;
  536. req->ata_sect_count |=
  537. (cfis->sector_count_exp << CRQB_SECTCOUNT_COUNT_EXP_SHIFT) &
  538. CRQB_SECTCOUNT_COUNT_EXP_MASK;
  539. /* Flush data */
  540. start = (u32)req & ~(ARCH_DMA_MINALIGN - 1);
  541. flush_dcache_range(start,
  542. start + ALIGN(sizeof(*req), ARCH_DMA_MINALIGN));
  543. /* Trigger operation */
  544. slot = get_next_reqip(dev, port);
  545. set_reqip(dev, port, slot);
  546. /* Wait for completion */
  547. if (wait_dma_completion(dev, port, slot, 10000)) {
  548. printf("ATA operation timed out\n");
  549. return -1;
  550. }
  551. process_responses(dev, port);
  552. /* Invalidate data on read */
  553. if (buffer && len) {
  554. start = (u32)buffer & ~(ARCH_DMA_MINALIGN - 1);
  555. invalidate_dcache_range(start,
  556. start + ALIGN(len, ARCH_DMA_MINALIGN));
  557. }
  558. return len;
  559. }
  560. static u32 mv_sata_rw_cmd_ext(struct udevice *dev, int port, lbaint_t start,
  561. u32 blkcnt,
  562. u8 *buffer, int is_write)
  563. {
  564. struct sata_fis_h2d cfis;
  565. u32 res;
  566. u64 block;
  567. block = (u64)start;
  568. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  569. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  570. cfis.command = (is_write) ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
  571. cfis.lba_high_exp = (block >> 40) & 0xff;
  572. cfis.lba_mid_exp = (block >> 32) & 0xff;
  573. cfis.lba_low_exp = (block >> 24) & 0xff;
  574. cfis.lba_high = (block >> 16) & 0xff;
  575. cfis.lba_mid = (block >> 8) & 0xff;
  576. cfis.lba_low = block & 0xff;
  577. cfis.device = ATA_LBA;
  578. cfis.sector_count_exp = (blkcnt >> 8) & 0xff;
  579. cfis.sector_count = blkcnt & 0xff;
  580. res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
  581. ATA_SECT_SIZE * blkcnt, is_write);
  582. return res >= 0 ? blkcnt : res;
  583. }
  584. static u32 mv_sata_rw_cmd(struct udevice *dev, int port, lbaint_t start,
  585. u32 blkcnt, u8 *buffer, int is_write)
  586. {
  587. struct sata_fis_h2d cfis;
  588. lbaint_t block;
  589. u32 res;
  590. block = start;
  591. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  592. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  593. cfis.command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  594. cfis.device = ATA_LBA;
  595. cfis.device |= (block >> 24) & 0xf;
  596. cfis.lba_high = (block >> 16) & 0xff;
  597. cfis.lba_mid = (block >> 8) & 0xff;
  598. cfis.lba_low = block & 0xff;
  599. cfis.sector_count = (u8)(blkcnt & 0xff);
  600. res = mv_ata_exec_ata_cmd(dev, port, &cfis, buffer,
  601. ATA_SECT_SIZE * blkcnt, is_write);
  602. return res >= 0 ? blkcnt : res;
  603. }
  604. static u32 ata_low_level_rw(struct udevice *dev, int port, lbaint_t blknr,
  605. lbaint_t blkcnt, void *buffer, int is_write)
  606. {
  607. struct blk_desc *desc = dev_get_uclass_platdata(dev);
  608. lbaint_t start, blks;
  609. u8 *addr;
  610. int max_blks;
  611. debug("%s: " LBAFU " " LBAFU "\n", __func__, blknr, blkcnt);
  612. start = blknr;
  613. blks = blkcnt;
  614. addr = (u8 *)buffer;
  615. max_blks = MV_ATA_MAX_SECTORS;
  616. do {
  617. if (blks > max_blks) {
  618. if (desc->lba48) {
  619. mv_sata_rw_cmd_ext(dev, port, start, max_blks,
  620. addr, is_write);
  621. } else {
  622. mv_sata_rw_cmd(dev, port, start, max_blks,
  623. addr, is_write);
  624. }
  625. start += max_blks;
  626. blks -= max_blks;
  627. addr += ATA_SECT_SIZE * max_blks;
  628. } else {
  629. if (desc->lba48) {
  630. mv_sata_rw_cmd_ext(dev, port, start, blks, addr,
  631. is_write);
  632. } else {
  633. mv_sata_rw_cmd(dev, port, start, blks, addr,
  634. is_write);
  635. }
  636. start += blks;
  637. blks = 0;
  638. addr += ATA_SECT_SIZE * blks;
  639. }
  640. } while (blks != 0);
  641. return blkcnt;
  642. }
  643. static int mv_ata_exec_ata_cmd_nondma(struct udevice *dev, int port,
  644. struct sata_fis_h2d *cfis, u8 *buffer,
  645. u32 len, u32 iswrite)
  646. {
  647. struct mv_priv *priv = dev_get_platdata(dev);
  648. int i;
  649. u16 *tp;
  650. debug("%s\n", __func__);
  651. out_le32(priv->regbase + PIO_SECTOR_COUNT, cfis->sector_count);
  652. out_le32(priv->regbase + PIO_LBA_HI, cfis->lba_high);
  653. out_le32(priv->regbase + PIO_LBA_MID, cfis->lba_mid);
  654. out_le32(priv->regbase + PIO_LBA_LOW, cfis->lba_low);
  655. out_le32(priv->regbase + PIO_ERR_FEATURES, cfis->features);
  656. out_le32(priv->regbase + PIO_DEVICE, cfis->device);
  657. out_le32(priv->regbase + PIO_CMD_STATUS, cfis->command);
  658. if (ata_wait_register((u32 *)(priv->regbase + PIO_CMD_STATUS),
  659. ATA_BUSY, 0x0, 10000)) {
  660. debug("Failed to wait for completion\n");
  661. return -1;
  662. }
  663. if (len > 0) {
  664. tp = (u16 *)buffer;
  665. for (i = 0; i < len / 2; i++) {
  666. if (iswrite)
  667. out_le16(priv->regbase + PIO_DATA, *tp++);
  668. else
  669. *tp++ = in_le16(priv->regbase + PIO_DATA);
  670. }
  671. }
  672. return len;
  673. }
  674. static int mv_sata_identify(struct udevice *dev, int port, u16 *id)
  675. {
  676. struct sata_fis_h2d h2d;
  677. memset(&h2d, 0, sizeof(struct sata_fis_h2d));
  678. h2d.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  679. h2d.command = ATA_CMD_ID_ATA;
  680. /* Give device time to get operational */
  681. mdelay(10);
  682. return mv_ata_exec_ata_cmd_nondma(dev, port, &h2d, (u8 *)id,
  683. ATA_ID_WORDS * 2, READ_CMD);
  684. }
  685. static void mv_sata_xfer_mode(struct udevice *dev, int port, u16 *id)
  686. {
  687. struct mv_priv *priv = dev_get_platdata(dev);
  688. priv->pio = id[ATA_ID_PIO_MODES];
  689. priv->mwdma = id[ATA_ID_MWDMA_MODES];
  690. priv->udma = id[ATA_ID_UDMA_MODES];
  691. debug("pio %04x, mwdma %04x, udma %04x\n", priv->pio, priv->mwdma,
  692. priv->udma);
  693. }
  694. static void mv_sata_set_features(struct udevice *dev, int port)
  695. {
  696. struct mv_priv *priv = dev_get_platdata(dev);
  697. struct sata_fis_h2d cfis;
  698. u8 udma_cap;
  699. memset(&cfis, 0, sizeof(struct sata_fis_h2d));
  700. cfis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  701. cfis.command = ATA_CMD_SET_FEATURES;
  702. cfis.features = SETFEATURES_XFER;
  703. /* First check the device capablity */
  704. udma_cap = (u8) (priv->udma & 0xff);
  705. if (udma_cap == ATA_UDMA6)
  706. cfis.sector_count = XFER_UDMA_6;
  707. if (udma_cap == ATA_UDMA5)
  708. cfis.sector_count = XFER_UDMA_5;
  709. if (udma_cap == ATA_UDMA4)
  710. cfis.sector_count = XFER_UDMA_4;
  711. if (udma_cap == ATA_UDMA3)
  712. cfis.sector_count = XFER_UDMA_3;
  713. mv_ata_exec_ata_cmd_nondma(dev, port, &cfis, NULL, 0, READ_CMD);
  714. }
  715. /*
  716. * Initialize SATA memory windows
  717. */
  718. static void mvsata_ide_conf_mbus_windows(void)
  719. {
  720. const struct mbus_dram_target_info *dram;
  721. int i;
  722. dram = mvebu_mbus_dram_info();
  723. /* Disable windows, Set Size/Base to 0 */
  724. for (i = 0; i < 4; i++) {
  725. writel(0, MVSATA_WIN_CONTROL(i));
  726. writel(0, MVSATA_WIN_BASE(i));
  727. }
  728. for (i = 0; i < dram->num_cs; i++) {
  729. const struct mbus_dram_window *cs = dram->cs + i;
  730. writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
  731. (dram->mbus_dram_target_id << 4) | 1,
  732. MVSATA_WIN_CONTROL(i));
  733. writel(cs->base & 0xffff0000, MVSATA_WIN_BASE(i));
  734. }
  735. }
  736. static int sata_mv_init_sata(struct udevice *dev, int port)
  737. {
  738. struct mv_priv *priv = dev_get_platdata(dev);
  739. debug("Initialize sata dev: %d\n", port);
  740. if (port < 0 || port >= CONFIG_SYS_SATA_MAX_DEVICE) {
  741. printf("Invalid sata device %d\n", port);
  742. return -1;
  743. }
  744. /* Allocate and align request buffer */
  745. priv->crqb_alloc = malloc(sizeof(struct crqb) * REQUEST_QUEUE_SIZE +
  746. CRQB_ALIGN);
  747. if (!priv->crqb_alloc) {
  748. printf("Unable to allocate memory for request queue\n");
  749. return -ENOMEM;
  750. }
  751. memset(priv->crqb_alloc, 0,
  752. sizeof(struct crqb) * REQUEST_QUEUE_SIZE + CRQB_ALIGN);
  753. priv->request = (struct crqb *)(((u32) priv->crqb_alloc + CRQB_ALIGN) &
  754. ~(CRQB_ALIGN - 1));
  755. /* Allocate and align response buffer */
  756. priv->crpb_alloc = malloc(sizeof(struct crpb) * REQUEST_QUEUE_SIZE +
  757. CRPB_ALIGN);
  758. if (!priv->crpb_alloc) {
  759. printf("Unable to allocate memory for response queue\n");
  760. return -ENOMEM;
  761. }
  762. memset(priv->crpb_alloc, 0,
  763. sizeof(struct crpb) * REQUEST_QUEUE_SIZE + CRPB_ALIGN);
  764. priv->response = (struct crpb *)(((u32) priv->crpb_alloc + CRPB_ALIGN) &
  765. ~(CRPB_ALIGN - 1));
  766. sprintf(priv->name, "SATA%d", port);
  767. priv->regbase = port == 0 ? SATA0_BASE : SATA1_BASE;
  768. if (!hw_init) {
  769. debug("Initialize sata hw\n");
  770. hw_init = 1;
  771. mv_reset_one_hc();
  772. mvsata_ide_conf_mbus_windows();
  773. }
  774. mv_reset_port(dev, port);
  775. if (probe_port(dev, port)) {
  776. priv->link = 0;
  777. return -ENODEV;
  778. }
  779. priv->link = 1;
  780. return 0;
  781. }
  782. static int sata_mv_scan_sata(struct udevice *dev, int port)
  783. {
  784. struct blk_desc *desc = dev_get_uclass_platdata(dev);
  785. struct mv_priv *priv = dev_get_platdata(dev);
  786. unsigned char serial[ATA_ID_SERNO_LEN + 1];
  787. unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
  788. unsigned char product[ATA_ID_PROD_LEN + 1];
  789. u64 n_sectors;
  790. u16 *id;
  791. if (!priv->link)
  792. return -ENODEV;
  793. id = (u16 *)malloc(ATA_ID_WORDS * 2);
  794. if (!id) {
  795. printf("Failed to malloc id data\n");
  796. return -ENOMEM;
  797. }
  798. mv_sata_identify(dev, port, id);
  799. ata_swap_buf_le16(id, ATA_ID_WORDS);
  800. #ifdef DEBUG
  801. ata_dump_id(id);
  802. #endif
  803. /* Serial number */
  804. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  805. memcpy(desc->product, serial, sizeof(serial));
  806. /* Firmware version */
  807. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  808. memcpy(desc->revision, firmware, sizeof(firmware));
  809. /* Product model */
  810. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  811. memcpy(desc->vendor, product, sizeof(product));
  812. /* Total sectors */
  813. n_sectors = ata_id_n_sectors(id);
  814. desc->lba = n_sectors;
  815. /* Check if support LBA48 */
  816. if (ata_id_has_lba48(id)) {
  817. desc->lba48 = 1;
  818. debug("Device support LBA48\n");
  819. }
  820. /* Get the NCQ queue depth from device */
  821. priv->queue_depth = ata_id_queue_depth(id);
  822. /* Get the xfer mode from device */
  823. mv_sata_xfer_mode(dev, port, id);
  824. /* Set the xfer mode to highest speed */
  825. mv_sata_set_features(dev, port);
  826. /* Start up */
  827. mv_start_edma_engine(dev, port);
  828. return 0;
  829. }
  830. static ulong sata_mv_read(struct udevice *blk, lbaint_t blknr,
  831. lbaint_t blkcnt, void *buffer)
  832. {
  833. struct mv_priv *priv = dev_get_platdata(blk);
  834. return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
  835. buffer, READ_CMD);
  836. }
  837. static ulong sata_mv_write(struct udevice *blk, lbaint_t blknr,
  838. lbaint_t blkcnt, const void *buffer)
  839. {
  840. struct mv_priv *priv = dev_get_platdata(blk);
  841. return ata_low_level_rw(blk, priv->dev_nr, blknr, blkcnt,
  842. (void *)buffer, WRITE_CMD);
  843. }
  844. static const struct blk_ops sata_mv_blk_ops = {
  845. .read = sata_mv_read,
  846. .write = sata_mv_write,
  847. };
  848. U_BOOT_DRIVER(sata_mv_driver) = {
  849. .name = "sata_mv_blk",
  850. .id = UCLASS_BLK,
  851. .ops = &sata_mv_blk_ops,
  852. .platdata_auto_alloc_size = sizeof(struct mv_priv),
  853. };
  854. static int sata_mv_probe(struct udevice *dev)
  855. {
  856. const void *blob = gd->fdt_blob;
  857. int node = dev_of_offset(dev);
  858. struct mv_priv *priv;
  859. struct udevice *blk;
  860. int nr_ports;
  861. int ret;
  862. int i;
  863. /* Get number of ports of this SATA controller */
  864. nr_ports = min(fdtdec_get_int(blob, node, "nr-ports", -1),
  865. CONFIG_SYS_SATA_MAX_DEVICE);
  866. for (i = 0; i < nr_ports; i++) {
  867. ret = blk_create_devicef(dev, "sata_mv_blk", "blk",
  868. IF_TYPE_SATA, -1, 512, 0, &blk);
  869. if (ret) {
  870. debug("Can't create device\n");
  871. return ret;
  872. }
  873. priv = dev_get_platdata(blk);
  874. priv->dev_nr = i;
  875. /* Init SATA port */
  876. ret = sata_mv_init_sata(blk, i);
  877. if (ret) {
  878. debug("%s: Failed to init bus\n", __func__);
  879. return ret;
  880. }
  881. /* Scan SATA port */
  882. ret = sata_mv_scan_sata(blk, i);
  883. if (ret) {
  884. debug("%s: Failed to scan bus\n", __func__);
  885. return ret;
  886. }
  887. }
  888. return 0;
  889. }
  890. static int sata_mv_scan(struct udevice *dev)
  891. {
  892. /* Nothing to do here */
  893. return 0;
  894. }
  895. static const struct udevice_id sata_mv_ids[] = {
  896. { .compatible = "marvell,armada-370-sata" },
  897. { .compatible = "marvell,orion-sata" },
  898. { }
  899. };
  900. struct ahci_ops sata_mv_ahci_ops = {
  901. .scan = sata_mv_scan,
  902. };
  903. U_BOOT_DRIVER(sata_mv_ahci) = {
  904. .name = "sata_mv_ahci",
  905. .id = UCLASS_AHCI,
  906. .of_match = sata_mv_ids,
  907. .ops = &sata_mv_ahci_ops,
  908. .probe = sata_mv_probe,
  909. };