dwc_ahsata.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
  4. * Terry Lv <r65388@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <ahci.h>
  8. #include <blk.h>
  9. #include <cpu_func.h>
  10. #include <dm.h>
  11. #include <dwc_ahsata.h>
  12. #include <fis.h>
  13. #include <libata.h>
  14. #include <malloc.h>
  15. #include <memalign.h>
  16. #include <part.h>
  17. #include <sata.h>
  18. #include <asm/cache.h>
  19. #include <asm/io.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/arch/sys_proto.h>
  22. #include <asm/mach-imx/sata.h>
  23. #include <linux/bitops.h>
  24. #include <linux/ctype.h>
  25. #include <linux/errno.h>
  26. #include "dwc_ahsata_priv.h"
  27. struct sata_port_regs {
  28. u32 clb;
  29. u32 clbu;
  30. u32 fb;
  31. u32 fbu;
  32. u32 is;
  33. u32 ie;
  34. u32 cmd;
  35. u32 res1[1];
  36. u32 tfd;
  37. u32 sig;
  38. u32 ssts;
  39. u32 sctl;
  40. u32 serr;
  41. u32 sact;
  42. u32 ci;
  43. u32 sntf;
  44. u32 res2[1];
  45. u32 dmacr;
  46. u32 res3[1];
  47. u32 phycr;
  48. u32 physr;
  49. };
  50. struct sata_host_regs {
  51. u32 cap;
  52. u32 ghc;
  53. u32 is;
  54. u32 pi;
  55. u32 vs;
  56. u32 ccc_ctl;
  57. u32 ccc_ports;
  58. u32 res1[2];
  59. u32 cap2;
  60. u32 res2[30];
  61. u32 bistafr;
  62. u32 bistcr;
  63. u32 bistfctr;
  64. u32 bistsr;
  65. u32 bistdecr;
  66. u32 res3[2];
  67. u32 oobr;
  68. u32 res4[8];
  69. u32 timer1ms;
  70. u32 res5[1];
  71. u32 gparam1r;
  72. u32 gparam2r;
  73. u32 pparamr;
  74. u32 testr;
  75. u32 versionr;
  76. u32 idr;
  77. };
  78. #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
  79. #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
  80. #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
  81. static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
  82. {
  83. return base + 0x100 + (port * 0x80);
  84. }
  85. static int waiting_for_cmd_completed(u8 *offset,
  86. int timeout_msec,
  87. u32 sign)
  88. {
  89. int i;
  90. u32 status;
  91. for (i = 0;
  92. ((status = readl(offset)) & sign) && i < timeout_msec;
  93. ++i)
  94. mdelay(1);
  95. return (i < timeout_msec) ? 0 : -1;
  96. }
  97. static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
  98. {
  99. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  100. writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
  101. writel(0x02060b14, &host_mmio->oobr);
  102. return 0;
  103. }
  104. static int ahci_host_init(struct ahci_uc_priv *uc_priv)
  105. {
  106. u32 tmp, cap_save, num_ports;
  107. int i, j, timeout = 1000;
  108. struct sata_port_regs *port_mmio = NULL;
  109. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  110. int clk = mxc_get_clock(MXC_SATA_CLK);
  111. cap_save = readl(&host_mmio->cap);
  112. cap_save |= SATA_HOST_CAP_SSS;
  113. /* global controller reset */
  114. tmp = readl(&host_mmio->ghc);
  115. if ((tmp & SATA_HOST_GHC_HR) == 0)
  116. writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
  117. while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
  118. ;
  119. if (timeout <= 0) {
  120. debug("controller reset failed (0x%x)\n", tmp);
  121. return -1;
  122. }
  123. /* Set timer 1ms */
  124. writel(clk / 1000, &host_mmio->timer1ms);
  125. ahci_setup_oobr(uc_priv, 0);
  126. writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
  127. writel(cap_save, &host_mmio->cap);
  128. num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
  129. writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
  130. /*
  131. * Determine which Ports are implemented by the DWC_ahsata,
  132. * by reading the PI register. This bit map value aids the
  133. * software to determine how many Ports are available and
  134. * which Port registers need to be initialized.
  135. */
  136. uc_priv->cap = readl(&host_mmio->cap);
  137. uc_priv->port_map = readl(&host_mmio->pi);
  138. /* Determine how many command slots the HBA supports */
  139. uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
  140. debug("cap 0x%x port_map 0x%x n_ports %d\n",
  141. uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
  142. for (i = 0; i < uc_priv->n_ports; i++) {
  143. uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
  144. port_mmio = uc_priv->port[i].port_mmio;
  145. /* Ensure that the DWC_ahsata is in idle state */
  146. tmp = readl(&port_mmio->cmd);
  147. /*
  148. * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
  149. * are all cleared, the Port is in an idle state.
  150. */
  151. if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
  152. SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
  153. /*
  154. * System software places a Port into the idle state by
  155. * clearing P#CMD.ST and waiting for P#CMD.CR to return
  156. * 0 when read.
  157. */
  158. tmp &= ~SATA_PORT_CMD_ST;
  159. writel_with_flush(tmp, &port_mmio->cmd);
  160. /*
  161. * spec says 500 msecs for each bit, so
  162. * this is slightly incorrect.
  163. */
  164. mdelay(500);
  165. timeout = 1000;
  166. while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
  167. && --timeout)
  168. ;
  169. if (timeout <= 0) {
  170. debug("port reset failed (0x%x)\n", tmp);
  171. return -1;
  172. }
  173. }
  174. /* Spin-up device */
  175. tmp = readl(&port_mmio->cmd);
  176. writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
  177. /* Wait for spin-up to finish */
  178. timeout = 1000;
  179. while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
  180. && --timeout)
  181. ;
  182. if (timeout <= 0) {
  183. debug("Spin-Up can't finish!\n");
  184. return -1;
  185. }
  186. for (j = 0; j < 100; ++j) {
  187. mdelay(10);
  188. tmp = readl(&port_mmio->ssts);
  189. if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
  190. ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
  191. break;
  192. }
  193. /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
  194. timeout = 1000;
  195. while (!(readl(&port_mmio->serr) & SATA_PORT_SERR_DIAG_X)
  196. && --timeout)
  197. ;
  198. if (timeout <= 0) {
  199. debug("Can't find DIAG_X set!\n");
  200. return -1;
  201. }
  202. /*
  203. * For each implemented Port, clear the P#SERR
  204. * register, by writing ones to each implemented\
  205. * bit location.
  206. */
  207. tmp = readl(&port_mmio->serr);
  208. debug("P#SERR 0x%x\n",
  209. tmp);
  210. writel(tmp, &port_mmio->serr);
  211. /* Ack any pending irq events for this port */
  212. tmp = readl(&host_mmio->is);
  213. debug("IS 0x%x\n", tmp);
  214. if (tmp)
  215. writel(tmp, &host_mmio->is);
  216. writel(1 << i, &host_mmio->is);
  217. /* set irq mask (enables interrupts) */
  218. writel(DEF_PORT_IRQ, &port_mmio->ie);
  219. /* register linkup ports */
  220. tmp = readl(&port_mmio->ssts);
  221. debug("Port %d status: 0x%x\n", i, tmp);
  222. if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
  223. uc_priv->link_port_map |= (0x01 << i);
  224. }
  225. tmp = readl(&host_mmio->ghc);
  226. debug("GHC 0x%x\n", tmp);
  227. writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
  228. tmp = readl(&host_mmio->ghc);
  229. debug("GHC 0x%x\n", tmp);
  230. return 0;
  231. }
  232. static void ahci_print_info(struct ahci_uc_priv *uc_priv)
  233. {
  234. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  235. u32 vers, cap, impl, speed;
  236. const char *speed_s;
  237. const char *scc_s;
  238. vers = readl(&host_mmio->vs);
  239. cap = uc_priv->cap;
  240. impl = uc_priv->port_map;
  241. speed = (cap & SATA_HOST_CAP_ISS_MASK)
  242. >> SATA_HOST_CAP_ISS_OFFSET;
  243. if (speed == 1)
  244. speed_s = "1.5";
  245. else if (speed == 2)
  246. speed_s = "3";
  247. else
  248. speed_s = "?";
  249. scc_s = "SATA";
  250. printf("AHCI %02x%02x.%02x%02x "
  251. "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  252. (vers >> 24) & 0xff,
  253. (vers >> 16) & 0xff,
  254. (vers >> 8) & 0xff,
  255. vers & 0xff,
  256. ((cap >> 8) & 0x1f) + 1,
  257. (cap & 0x1f) + 1,
  258. speed_s,
  259. impl,
  260. scc_s);
  261. printf("flags: "
  262. "%s%s%s%s%s%s"
  263. "%s%s%s%s%s%s%s\n",
  264. cap & (1 << 31) ? "64bit " : "",
  265. cap & (1 << 30) ? "ncq " : "",
  266. cap & (1 << 28) ? "ilck " : "",
  267. cap & (1 << 27) ? "stag " : "",
  268. cap & (1 << 26) ? "pm " : "",
  269. cap & (1 << 25) ? "led " : "",
  270. cap & (1 << 24) ? "clo " : "",
  271. cap & (1 << 19) ? "nz " : "",
  272. cap & (1 << 18) ? "only " : "",
  273. cap & (1 << 17) ? "pmp " : "",
  274. cap & (1 << 15) ? "pio " : "",
  275. cap & (1 << 14) ? "slum " : "",
  276. cap & (1 << 13) ? "part " : "");
  277. }
  278. static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
  279. unsigned char *buf, int buf_len)
  280. {
  281. struct ahci_ioports *pp = &uc_priv->port[port];
  282. struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  283. u32 sg_count, max_bytes;
  284. int i;
  285. max_bytes = MAX_DATA_BYTES_PER_SG;
  286. sg_count = ((buf_len - 1) / max_bytes) + 1;
  287. if (sg_count > AHCI_MAX_SG) {
  288. printf("Error:Too much sg!\n");
  289. return -1;
  290. }
  291. for (i = 0; i < sg_count; i++) {
  292. ahci_sg->addr =
  293. cpu_to_le32((u32)buf + i * max_bytes);
  294. ahci_sg->addr_hi = 0;
  295. ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  296. (buf_len < max_bytes
  297. ? (buf_len - 1)
  298. : (max_bytes - 1)));
  299. ahci_sg++;
  300. buf_len -= max_bytes;
  301. }
  302. return sg_count;
  303. }
  304. static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
  305. {
  306. struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
  307. AHCI_CMD_SLOT_SZ * cmd_slot);
  308. memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
  309. cmd_hdr->opts = cpu_to_le32(opts);
  310. cmd_hdr->status = 0;
  311. pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
  312. #ifdef CONFIG_PHYS_64BIT
  313. pp->cmd_slot->tbl_addr_hi =
  314. cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
  315. #endif
  316. }
  317. #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
  318. static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
  319. struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
  320. s32 is_write)
  321. {
  322. struct ahci_ioports *pp = &uc_priv->port[port];
  323. struct sata_port_regs *port_mmio = pp->port_mmio;
  324. u32 opts;
  325. int sg_count = 0, cmd_slot = 0;
  326. cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
  327. if (32 == cmd_slot) {
  328. printf("Can't find empty command slot!\n");
  329. return 0;
  330. }
  331. /* Check xfer length */
  332. if (buf_len > MAX_BYTES_PER_TRANS) {
  333. printf("Max transfer length is %dB\n\r",
  334. MAX_BYTES_PER_TRANS);
  335. return 0;
  336. }
  337. memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
  338. if (buf && buf_len)
  339. sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
  340. opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
  341. if (is_write) {
  342. opts |= 0x40;
  343. flush_cache((ulong)buf, buf_len);
  344. }
  345. ahci_fill_cmd_slot(pp, cmd_slot, opts);
  346. flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
  347. writel_with_flush(1 << cmd_slot, &port_mmio->ci);
  348. if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
  349. 0x1 << cmd_slot)) {
  350. printf("timeout exit!\n");
  351. return -1;
  352. }
  353. invalidate_dcache_range((int)(pp->cmd_slot),
  354. (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
  355. debug("ahci_exec_ata_cmd: %d byte transferred.\n",
  356. pp->cmd_slot->status);
  357. if (!is_write)
  358. invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
  359. return buf_len;
  360. }
  361. static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
  362. {
  363. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  364. struct sata_fis_h2d *cfis = &h2d;
  365. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  366. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  367. cfis->pm_port_c = 1 << 7;
  368. cfis->command = ATA_CMD_SET_FEATURES;
  369. cfis->features = SETFEATURES_XFER;
  370. cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
  371. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
  372. }
  373. static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
  374. {
  375. struct ahci_ioports *pp = &uc_priv->port[port];
  376. struct sata_port_regs *port_mmio = pp->port_mmio;
  377. u32 port_status;
  378. u32 mem;
  379. int timeout = 10000000;
  380. debug("Enter start port: %d\n", port);
  381. port_status = readl(&port_mmio->ssts);
  382. debug("Port %d status: %x\n", port, port_status);
  383. if ((port_status & 0xf) != 0x03) {
  384. printf("No Link on this port!\n");
  385. return -1;
  386. }
  387. mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
  388. if (!mem) {
  389. printf("No mem for table!\n");
  390. return -ENOMEM;
  391. }
  392. mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
  393. memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  394. /*
  395. * First item in chunk of DMA memory: 32-slot command table,
  396. * 32 bytes each in size
  397. */
  398. pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
  399. debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
  400. mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
  401. /*
  402. * Second item: Received-FIS area, 256-Byte aligned
  403. */
  404. pp->rx_fis = mem;
  405. mem += AHCI_RX_FIS_SZ;
  406. /*
  407. * Third item: data area for storing a single command
  408. * and its scatter-gather table
  409. */
  410. pp->cmd_tbl = mem;
  411. debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
  412. mem += AHCI_CMD_TBL_HDR;
  413. writel_with_flush(0x00004444, &port_mmio->dmacr);
  414. pp->cmd_tbl_sg = (struct ahci_sg *)mem;
  415. writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
  416. writel_with_flush(pp->rx_fis, &port_mmio->fb);
  417. /* Enable FRE */
  418. writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
  419. &port_mmio->cmd);
  420. /* Wait device ready */
  421. while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
  422. SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
  423. && --timeout)
  424. ;
  425. if (timeout <= 0) {
  426. debug("Device not ready for BSY, DRQ and"
  427. "ERR in TFD!\n");
  428. return -1;
  429. }
  430. writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  431. PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  432. PORT_CMD_START, &port_mmio->cmd);
  433. debug("Exit start port %d\n", port);
  434. return 0;
  435. }
  436. static void dwc_ahsata_print_info(struct blk_desc *pdev)
  437. {
  438. printf("SATA Device Info:\n\r");
  439. printf("S/N: %s\n\rProduct model number: %s\n\r"
  440. "Firmware version: %s\n\rCapacity: " LBAFU " sectors\n\r",
  441. pdev->product, pdev->vendor, pdev->revision, pdev->lba);
  442. }
  443. static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
  444. {
  445. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  446. struct sata_fis_h2d *cfis = &h2d;
  447. u8 port = uc_priv->hard_port_no;
  448. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  449. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  450. cfis->pm_port_c = 0x80; /* is command */
  451. cfis->command = ATA_CMD_ID_ATA;
  452. ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
  453. READ_CMD);
  454. ata_swap_buf_le16(id, ATA_ID_WORDS);
  455. }
  456. static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
  457. {
  458. uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
  459. uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
  460. debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
  461. }
  462. static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
  463. u32 blkcnt, u8 *buffer, int is_write)
  464. {
  465. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  466. struct sata_fis_h2d *cfis = &h2d;
  467. u8 port = uc_priv->hard_port_no;
  468. u32 block;
  469. block = start;
  470. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  471. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  472. cfis->pm_port_c = 0x80; /* is command */
  473. cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
  474. cfis->device = ATA_LBA;
  475. cfis->device |= (block >> 24) & 0xf;
  476. cfis->lba_high = (block >> 16) & 0xff;
  477. cfis->lba_mid = (block >> 8) & 0xff;
  478. cfis->lba_low = block & 0xff;
  479. cfis->sector_count = (u8)(blkcnt & 0xff);
  480. if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
  481. ATA_SECT_SIZE * blkcnt, is_write) > 0)
  482. return blkcnt;
  483. else
  484. return 0;
  485. }
  486. static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
  487. {
  488. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  489. struct sata_fis_h2d *cfis = &h2d;
  490. u8 port = uc_priv->hard_port_no;
  491. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  492. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  493. cfis->pm_port_c = 0x80; /* is command */
  494. cfis->command = ATA_CMD_FLUSH;
  495. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
  496. }
  497. static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
  498. lbaint_t blkcnt, u8 *buffer, int is_write)
  499. {
  500. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  501. struct sata_fis_h2d *cfis = &h2d;
  502. u8 port = uc_priv->hard_port_no;
  503. u64 block;
  504. block = (u64)start;
  505. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  506. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  507. cfis->pm_port_c = 0x80; /* is command */
  508. cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
  509. : ATA_CMD_READ_EXT;
  510. cfis->lba_high_exp = (block >> 40) & 0xff;
  511. cfis->lba_mid_exp = (block >> 32) & 0xff;
  512. cfis->lba_low_exp = (block >> 24) & 0xff;
  513. cfis->lba_high = (block >> 16) & 0xff;
  514. cfis->lba_mid = (block >> 8) & 0xff;
  515. cfis->lba_low = block & 0xff;
  516. cfis->device = ATA_LBA;
  517. cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
  518. cfis->sector_count = blkcnt & 0xff;
  519. if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
  520. ATA_SECT_SIZE * blkcnt, is_write) > 0)
  521. return blkcnt;
  522. else
  523. return 0;
  524. }
  525. static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
  526. {
  527. struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
  528. struct sata_fis_h2d *cfis = &h2d;
  529. u8 port = uc_priv->hard_port_no;
  530. memset(cfis, 0, sizeof(struct sata_fis_h2d));
  531. cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
  532. cfis->pm_port_c = 0x80; /* is command */
  533. cfis->command = ATA_CMD_FLUSH_EXT;
  534. ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
  535. }
  536. static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
  537. {
  538. if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
  539. uc_priv->flags |= SATA_FLAG_WCACHE;
  540. if (ata_id_has_flush(id))
  541. uc_priv->flags |= SATA_FLAG_FLUSH;
  542. if (ata_id_has_flush_ext(id))
  543. uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
  544. }
  545. static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
  546. lbaint_t blkcnt, const void *buffer,
  547. int is_write)
  548. {
  549. u32 start, blks;
  550. u8 *addr;
  551. int max_blks;
  552. start = blknr;
  553. blks = blkcnt;
  554. addr = (u8 *)buffer;
  555. max_blks = ATA_MAX_SECTORS_LBA48;
  556. do {
  557. if (blks > max_blks) {
  558. if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
  559. max_blks, addr,
  560. is_write))
  561. return 0;
  562. start += max_blks;
  563. blks -= max_blks;
  564. addr += ATA_SECT_SIZE * max_blks;
  565. } else {
  566. if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
  567. addr, is_write))
  568. return 0;
  569. start += blks;
  570. blks = 0;
  571. addr += ATA_SECT_SIZE * blks;
  572. }
  573. } while (blks != 0);
  574. return blkcnt;
  575. }
  576. static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
  577. lbaint_t blkcnt, const void *buffer,
  578. int is_write)
  579. {
  580. u32 start, blks;
  581. u8 *addr;
  582. int max_blks;
  583. start = blknr;
  584. blks = blkcnt;
  585. addr = (u8 *)buffer;
  586. max_blks = ATA_MAX_SECTORS;
  587. do {
  588. if (blks > max_blks) {
  589. if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
  590. max_blks, addr,
  591. is_write))
  592. return 0;
  593. start += max_blks;
  594. blks -= max_blks;
  595. addr += ATA_SECT_SIZE * max_blks;
  596. } else {
  597. if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
  598. addr, is_write))
  599. return 0;
  600. start += blks;
  601. blks = 0;
  602. addr += ATA_SECT_SIZE * blks;
  603. }
  604. } while (blks != 0);
  605. return blkcnt;
  606. }
  607. static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
  608. {
  609. u32 linkmap;
  610. int i;
  611. linkmap = uc_priv->link_port_map;
  612. if (0 == linkmap) {
  613. printf("No port device detected!\n");
  614. return -ENXIO;
  615. }
  616. for (i = 0; i < uc_priv->n_ports; i++) {
  617. if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
  618. if (ahci_port_start(uc_priv, (u8)i)) {
  619. printf("Can not start port %d\n", i);
  620. return 1;
  621. }
  622. uc_priv->hard_port_no = i;
  623. break;
  624. }
  625. }
  626. return 0;
  627. }
  628. static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
  629. struct blk_desc *pdev)
  630. {
  631. u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
  632. u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
  633. u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
  634. u8 port = uc_priv->hard_port_no;
  635. ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
  636. /* Identify device to get information */
  637. dwc_ahsata_identify(uc_priv, id);
  638. /* Serial number */
  639. ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
  640. memcpy(pdev->product, serial, sizeof(serial));
  641. /* Firmware version */
  642. ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
  643. memcpy(pdev->revision, firmware, sizeof(firmware));
  644. /* Product model */
  645. ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
  646. memcpy(pdev->vendor, product, sizeof(product));
  647. /* Total sectors */
  648. pdev->lba = ata_id_n_sectors(id);
  649. pdev->type = DEV_TYPE_HARDDISK;
  650. pdev->blksz = ATA_SECT_SIZE;
  651. pdev->lun = 0;
  652. /* Check if support LBA48 */
  653. if (ata_id_has_lba48(id)) {
  654. pdev->lba48 = 1;
  655. debug("Device support LBA48\n\r");
  656. }
  657. /* Get the NCQ queue depth from device */
  658. uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
  659. uc_priv->flags |= ata_id_queue_depth(id);
  660. /* Get the xfer mode from device */
  661. dwc_ahsata_xfer_mode(uc_priv, id);
  662. /* Get the write cache status from device */
  663. dwc_ahsata_init_wcache(uc_priv, id);
  664. /* Set the xfer mode to highest speed */
  665. ahci_set_feature(uc_priv, port);
  666. dwc_ahsata_print_info(pdev);
  667. return 0;
  668. }
  669. /*
  670. * SATA interface between low level driver and command layer
  671. */
  672. static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
  673. struct blk_desc *desc, ulong blknr,
  674. lbaint_t blkcnt, void *buffer)
  675. {
  676. u32 rc;
  677. if (desc->lba48)
  678. rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
  679. READ_CMD);
  680. else
  681. rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
  682. READ_CMD);
  683. return rc;
  684. }
  685. static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
  686. struct blk_desc *desc, ulong blknr,
  687. lbaint_t blkcnt, const void *buffer)
  688. {
  689. u32 rc;
  690. u32 flags = uc_priv->flags;
  691. if (desc->lba48) {
  692. rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
  693. WRITE_CMD);
  694. if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
  695. dwc_ahsata_flush_cache_ext(uc_priv);
  696. } else {
  697. rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
  698. WRITE_CMD);
  699. if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
  700. dwc_ahsata_flush_cache(uc_priv);
  701. }
  702. return rc;
  703. }
  704. #if !CONFIG_IS_ENABLED(AHCI)
  705. static int ahci_init_one(int pdev)
  706. {
  707. int rc;
  708. struct ahci_uc_priv *uc_priv = NULL;
  709. uc_priv = malloc(sizeof(struct ahci_uc_priv));
  710. if (!uc_priv)
  711. return -ENOMEM;
  712. memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
  713. uc_priv->dev = pdev;
  714. uc_priv->host_flags = ATA_FLAG_SATA
  715. | ATA_FLAG_NO_LEGACY
  716. | ATA_FLAG_MMIO
  717. | ATA_FLAG_PIO_DMA
  718. | ATA_FLAG_NO_ATAPI;
  719. uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
  720. /* initialize adapter */
  721. rc = ahci_host_init(uc_priv);
  722. if (rc)
  723. goto err_out;
  724. ahci_print_info(uc_priv);
  725. /* Save the uc_private struct to block device struct */
  726. sata_dev_desc[pdev].priv = uc_priv;
  727. return 0;
  728. err_out:
  729. if (uc_priv)
  730. free(uc_priv);
  731. return rc;
  732. }
  733. int init_sata(int dev)
  734. {
  735. struct ahci_uc_priv *uc_priv = NULL;
  736. #if defined(CONFIG_MX6)
  737. if (!is_mx6dq() && !is_mx6dqp())
  738. return 1;
  739. #endif
  740. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  741. printf("The sata index %d is out of ranges\n\r", dev);
  742. return -1;
  743. }
  744. ahci_init_one(dev);
  745. uc_priv = sata_dev_desc[dev].priv;
  746. return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
  747. }
  748. int reset_sata(int dev)
  749. {
  750. struct ahci_uc_priv *uc_priv;
  751. struct sata_host_regs *host_mmio;
  752. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
  753. printf("The sata index %d is out of ranges\n\r", dev);
  754. return -1;
  755. }
  756. uc_priv = sata_dev_desc[dev].priv;
  757. if (NULL == uc_priv)
  758. /* not initialized, so nothing to reset */
  759. return 0;
  760. host_mmio = uc_priv->mmio_base;
  761. setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
  762. while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
  763. udelay(100);
  764. free(uc_priv);
  765. memset(&sata_dev_desc[dev], 0, sizeof(struct blk_desc));
  766. return 0;
  767. }
  768. int sata_port_status(int dev, int port)
  769. {
  770. struct sata_port_regs *port_mmio;
  771. struct ahci_uc_priv *uc_priv = NULL;
  772. if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
  773. return -EINVAL;
  774. if (sata_dev_desc[dev].priv == NULL)
  775. return -ENODEV;
  776. uc_priv = sata_dev_desc[dev].priv;
  777. port_mmio = uc_priv->port[port].port_mmio;
  778. return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
  779. }
  780. /*
  781. * SATA interface between low level driver and command layer
  782. */
  783. ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
  784. {
  785. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  786. return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
  787. buffer);
  788. }
  789. ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
  790. {
  791. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  792. return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
  793. buffer);
  794. }
  795. int scan_sata(int dev)
  796. {
  797. struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
  798. struct blk_desc *pdev = &sata_dev_desc[dev];
  799. return dwc_ahsata_scan_common(uc_priv, pdev);
  800. }
  801. #endif /* CONFIG_IS_ENABLED(AHCI) */
  802. #if CONFIG_IS_ENABLED(AHCI)
  803. int dwc_ahsata_port_status(struct udevice *dev, int port)
  804. {
  805. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  806. struct sata_port_regs *port_mmio;
  807. port_mmio = uc_priv->port[port].port_mmio;
  808. return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
  809. }
  810. int dwc_ahsata_bus_reset(struct udevice *dev)
  811. {
  812. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  813. struct sata_host_regs *host_mmio = uc_priv->mmio_base;
  814. setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
  815. while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
  816. udelay(100);
  817. return 0;
  818. }
  819. int dwc_ahsata_scan(struct udevice *dev)
  820. {
  821. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  822. struct blk_desc *desc;
  823. struct udevice *blk;
  824. int ret;
  825. /*
  826. * Create only one block device and do detection
  827. * to make sure that there won't be a lot of
  828. * block devices created
  829. */
  830. device_find_first_child(dev, &blk);
  831. if (!blk) {
  832. ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
  833. IF_TYPE_SATA, -1, 512, 0, &blk);
  834. if (ret) {
  835. debug("Can't create device\n");
  836. return ret;
  837. }
  838. }
  839. desc = dev_get_uclass_platdata(blk);
  840. ret = dwc_ahsata_scan_common(uc_priv, desc);
  841. if (ret) {
  842. debug("%s: Failed to scan bus\n", __func__);
  843. return ret;
  844. }
  845. return 0;
  846. }
  847. int dwc_ahsata_probe(struct udevice *dev)
  848. {
  849. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  850. int ret;
  851. #if defined(CONFIG_MX6)
  852. setup_sata();
  853. #endif
  854. uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
  855. ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
  856. uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
  857. /* initialize adapter */
  858. ret = ahci_host_init(uc_priv);
  859. if (ret)
  860. return ret;
  861. ahci_print_info(uc_priv);
  862. return dwc_ahci_start_ports(uc_priv);
  863. }
  864. static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
  865. lbaint_t blkcnt, void *buffer)
  866. {
  867. struct blk_desc *desc = dev_get_uclass_platdata(blk);
  868. struct udevice *dev = dev_get_parent(blk);
  869. struct ahci_uc_priv *uc_priv;
  870. uc_priv = dev_get_uclass_priv(dev);
  871. return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
  872. }
  873. static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
  874. lbaint_t blkcnt, const void *buffer)
  875. {
  876. struct blk_desc *desc = dev_get_uclass_platdata(blk);
  877. struct udevice *dev = dev_get_parent(blk);
  878. struct ahci_uc_priv *uc_priv;
  879. uc_priv = dev_get_uclass_priv(dev);
  880. return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
  881. }
  882. static const struct blk_ops dwc_ahsata_blk_ops = {
  883. .read = dwc_ahsata_read,
  884. .write = dwc_ahsata_write,
  885. };
  886. U_BOOT_DRIVER(dwc_ahsata_blk) = {
  887. .name = "dwc_ahsata_blk",
  888. .id = UCLASS_BLK,
  889. .ops = &dwc_ahsata_blk_ops,
  890. };
  891. #if CONFIG_IS_ENABLED(DWC_AHSATA_AHCI)
  892. struct ahci_ops dwc_ahsata_ahci_ops = {
  893. .port_status = dwc_ahsata_port_status,
  894. .reset = dwc_ahsata_bus_reset,
  895. .scan = dwc_ahsata_scan,
  896. };
  897. static const struct udevice_id dwc_ahsata_ahci_ids[] = {
  898. { .compatible = "fsl,imx6q-ahci" },
  899. { }
  900. };
  901. U_BOOT_DRIVER(dwc_ahsata_ahci) = {
  902. .name = "dwc_ahsata_ahci",
  903. .id = UCLASS_AHCI,
  904. .of_match = dwc_ahsata_ahci_ids,
  905. .ops = &dwc_ahsata_ahci_ops,
  906. .probe = dwc_ahsata_probe,
  907. };
  908. #endif
  909. #endif