ahci.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. * Author: Jason Jin<Jason.jin@freescale.com>
  5. * Zhang Wei<wei.zhang@freescale.com>
  6. *
  7. * with the reference on libata and ahci drvier in kernel
  8. *
  9. * This driver provides a SCSI interface to SATA.
  10. */
  11. #include <common.h>
  12. #include <blk.h>
  13. #include <cpu_func.h>
  14. #include <command.h>
  15. #include <dm.h>
  16. #include <pci.h>
  17. #include <asm/processor.h>
  18. #include <linux/errno.h>
  19. #include <asm/io.h>
  20. #include <malloc.h>
  21. #include <memalign.h>
  22. #include <pci.h>
  23. #include <scsi.h>
  24. #include <libata.h>
  25. #include <linux/ctype.h>
  26. #include <ahci.h>
  27. #include <dm/device-internal.h>
  28. #include <dm/lists.h>
  29. static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
  30. #ifndef CONFIG_DM_SCSI
  31. struct ahci_uc_priv *probe_ent = NULL;
  32. #endif
  33. #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
  34. /*
  35. * Some controllers limit number of blocks they can read/write at once.
  36. * Contemporary SSD devices work much faster if the read/write size is aligned
  37. * to a power of 2. Let's set default to 128 and allowing to be overwritten if
  38. * needed.
  39. */
  40. #ifndef MAX_SATA_BLOCKS_READ_WRITE
  41. #define MAX_SATA_BLOCKS_READ_WRITE 0x80
  42. #endif
  43. /* Maximum timeouts for each event */
  44. #define WAIT_MS_SPINUP 20000
  45. #define WAIT_MS_DATAIO 10000
  46. #define WAIT_MS_FLUSH 5000
  47. #define WAIT_MS_LINKUP 200
  48. #define AHCI_CAP_S64A BIT(31)
  49. __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
  50. {
  51. return base + 0x100 + (port * 0x80);
  52. }
  53. #define msleep(a) udelay(a * 1000)
  54. static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
  55. {
  56. const unsigned long start = begin;
  57. const unsigned long end = start + len;
  58. debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
  59. flush_dcache_range(start, end);
  60. }
  61. /*
  62. * SATA controller DMAs to physical RAM. Ensure data from the
  63. * controller is invalidated from dcache; next access comes from
  64. * physical RAM.
  65. */
  66. static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
  67. {
  68. const unsigned long start = begin;
  69. const unsigned long end = start + len;
  70. debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
  71. invalidate_dcache_range(start, end);
  72. }
  73. /*
  74. * Ensure data for SATA controller is flushed out of dcache and
  75. * written to physical memory.
  76. */
  77. static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
  78. {
  79. ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
  80. AHCI_PORT_PRIV_DMA_SZ);
  81. }
  82. static int waiting_for_cmd_completed(void __iomem *offset,
  83. int timeout_msec,
  84. u32 sign)
  85. {
  86. int i;
  87. u32 status;
  88. for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
  89. msleep(1);
  90. return (i < timeout_msec) ? 0 : -1;
  91. }
  92. int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
  93. {
  94. u32 tmp;
  95. int j = 0;
  96. void __iomem *port_mmio = uc_priv->port[port].port_mmio;
  97. /*
  98. * Bring up SATA link.
  99. * SATA link bringup time is usually less than 1 ms; only very
  100. * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
  101. */
  102. while (j < WAIT_MS_LINKUP) {
  103. tmp = readl(port_mmio + PORT_SCR_STAT);
  104. tmp &= PORT_SCR_STAT_DET_MASK;
  105. if (tmp == PORT_SCR_STAT_DET_PHYRDY)
  106. return 0;
  107. udelay(1000);
  108. j++;
  109. }
  110. return 1;
  111. }
  112. #ifdef CONFIG_SUNXI_AHCI
  113. /* The sunxi AHCI controller requires this undocumented setup */
  114. static void sunxi_dma_init(void __iomem *port_mmio)
  115. {
  116. clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
  117. }
  118. #endif
  119. int ahci_reset(void __iomem *base)
  120. {
  121. int i = 1000;
  122. u32 __iomem *host_ctl_reg = base + HOST_CTL;
  123. u32 tmp = readl(host_ctl_reg); /* global controller reset */
  124. if ((tmp & HOST_RESET) == 0)
  125. writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
  126. /*
  127. * reset must complete within 1 second, or
  128. * the hardware should be considered fried.
  129. */
  130. do {
  131. udelay(1000);
  132. tmp = readl(host_ctl_reg);
  133. i--;
  134. } while ((i > 0) && (tmp & HOST_RESET));
  135. if (i == 0) {
  136. printf("controller reset failed (0x%x)\n", tmp);
  137. return -1;
  138. }
  139. return 0;
  140. }
  141. static int ahci_host_init(struct ahci_uc_priv *uc_priv)
  142. {
  143. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  144. # ifdef CONFIG_DM_PCI
  145. struct udevice *dev = uc_priv->dev;
  146. struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);
  147. # else
  148. pci_dev_t pdev = uc_priv->dev;
  149. unsigned short vendor;
  150. # endif
  151. u16 tmp16;
  152. #endif
  153. void __iomem *mmio = uc_priv->mmio_base;
  154. u32 tmp, cap_save, cmd;
  155. int i, j, ret;
  156. void __iomem *port_mmio;
  157. u32 port_map;
  158. debug("ahci_host_init: start\n");
  159. cap_save = readl(mmio + HOST_CAP);
  160. cap_save &= ((1 << 28) | (1 << 17));
  161. cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
  162. ret = ahci_reset(uc_priv->mmio_base);
  163. if (ret)
  164. return ret;
  165. writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
  166. writel(cap_save, mmio + HOST_CAP);
  167. writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
  168. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  169. # ifdef CONFIG_DM_PCI
  170. if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
  171. u16 tmp16;
  172. dm_pci_read_config16(dev, 0x92, &tmp16);
  173. dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
  174. }
  175. # else
  176. pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
  177. if (vendor == PCI_VENDOR_ID_INTEL) {
  178. u16 tmp16;
  179. pci_read_config_word(pdev, 0x92, &tmp16);
  180. tmp16 |= 0xf;
  181. pci_write_config_word(pdev, 0x92, tmp16);
  182. }
  183. # endif
  184. #endif
  185. uc_priv->cap = readl(mmio + HOST_CAP);
  186. uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
  187. port_map = uc_priv->port_map;
  188. uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
  189. debug("cap 0x%x port_map 0x%x n_ports %d\n",
  190. uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
  191. #if !defined(CONFIG_DM_SCSI)
  192. if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
  193. uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
  194. #endif
  195. for (i = 0; i < uc_priv->n_ports; i++) {
  196. if (!(port_map & (1 << i)))
  197. continue;
  198. uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
  199. port_mmio = (u8 *)uc_priv->port[i].port_mmio;
  200. /* make sure port is not active */
  201. tmp = readl(port_mmio + PORT_CMD);
  202. if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  203. PORT_CMD_FIS_RX | PORT_CMD_START)) {
  204. debug("Port %d is active. Deactivating.\n", i);
  205. tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
  206. PORT_CMD_FIS_RX | PORT_CMD_START);
  207. writel_with_flush(tmp, port_mmio + PORT_CMD);
  208. /* spec says 500 msecs for each bit, so
  209. * this is slightly incorrect.
  210. */
  211. msleep(500);
  212. }
  213. #ifdef CONFIG_SUNXI_AHCI
  214. sunxi_dma_init(port_mmio);
  215. #endif
  216. /* Add the spinup command to whatever mode bits may
  217. * already be on in the command register.
  218. */
  219. cmd = readl(port_mmio + PORT_CMD);
  220. cmd |= PORT_CMD_SPIN_UP;
  221. writel_with_flush(cmd, port_mmio + PORT_CMD);
  222. /* Bring up SATA link. */
  223. ret = ahci_link_up(uc_priv, i);
  224. if (ret) {
  225. printf("SATA link %d timeout.\n", i);
  226. continue;
  227. } else {
  228. debug("SATA link ok.\n");
  229. }
  230. /* Clear error status */
  231. tmp = readl(port_mmio + PORT_SCR_ERR);
  232. if (tmp)
  233. writel(tmp, port_mmio + PORT_SCR_ERR);
  234. debug("Spinning up device on SATA port %d... ", i);
  235. j = 0;
  236. while (j < WAIT_MS_SPINUP) {
  237. tmp = readl(port_mmio + PORT_TFDATA);
  238. if (!(tmp & (ATA_BUSY | ATA_DRQ)))
  239. break;
  240. udelay(1000);
  241. tmp = readl(port_mmio + PORT_SCR_STAT);
  242. tmp &= PORT_SCR_STAT_DET_MASK;
  243. if (tmp == PORT_SCR_STAT_DET_PHYRDY)
  244. break;
  245. j++;
  246. }
  247. tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
  248. if (tmp == PORT_SCR_STAT_DET_COMINIT) {
  249. debug("SATA link %d down (COMINIT received), retrying...\n", i);
  250. i--;
  251. continue;
  252. }
  253. printf("Target spinup took %d ms.\n", j);
  254. if (j == WAIT_MS_SPINUP)
  255. debug("timeout.\n");
  256. else
  257. debug("ok.\n");
  258. tmp = readl(port_mmio + PORT_SCR_ERR);
  259. debug("PORT_SCR_ERR 0x%x\n", tmp);
  260. writel(tmp, port_mmio + PORT_SCR_ERR);
  261. /* ack any pending irq events for this port */
  262. tmp = readl(port_mmio + PORT_IRQ_STAT);
  263. debug("PORT_IRQ_STAT 0x%x\n", tmp);
  264. if (tmp)
  265. writel(tmp, port_mmio + PORT_IRQ_STAT);
  266. writel(1 << i, mmio + HOST_IRQ_STAT);
  267. /* register linkup ports */
  268. tmp = readl(port_mmio + PORT_SCR_STAT);
  269. debug("SATA port %d status: 0x%x\n", i, tmp);
  270. if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
  271. uc_priv->link_port_map |= (0x01 << i);
  272. }
  273. tmp = readl(mmio + HOST_CTL);
  274. debug("HOST_CTL 0x%x\n", tmp);
  275. writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
  276. tmp = readl(mmio + HOST_CTL);
  277. debug("HOST_CTL 0x%x\n", tmp);
  278. #if !defined(CONFIG_DM_SCSI)
  279. #ifndef CONFIG_SCSI_AHCI_PLAT
  280. # ifdef CONFIG_DM_PCI
  281. dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
  282. tmp |= PCI_COMMAND_MASTER;
  283. dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
  284. # else
  285. pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
  286. tmp |= PCI_COMMAND_MASTER;
  287. pci_write_config_word(pdev, PCI_COMMAND, tmp16);
  288. # endif
  289. #endif
  290. #endif
  291. return 0;
  292. }
  293. static void ahci_print_info(struct ahci_uc_priv *uc_priv)
  294. {
  295. #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
  296. # if defined(CONFIG_DM_PCI)
  297. struct udevice *dev = uc_priv->dev;
  298. # else
  299. pci_dev_t pdev = uc_priv->dev;
  300. # endif
  301. u16 cc;
  302. #endif
  303. void __iomem *mmio = uc_priv->mmio_base;
  304. u32 vers, cap, cap2, impl, speed;
  305. const char *speed_s;
  306. const char *scc_s;
  307. vers = readl(mmio + HOST_VERSION);
  308. cap = uc_priv->cap;
  309. cap2 = readl(mmio + HOST_CAP2);
  310. impl = uc_priv->port_map;
  311. speed = (cap >> 20) & 0xf;
  312. if (speed == 1)
  313. speed_s = "1.5";
  314. else if (speed == 2)
  315. speed_s = "3";
  316. else if (speed == 3)
  317. speed_s = "6";
  318. else
  319. speed_s = "?";
  320. #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
  321. scc_s = "SATA";
  322. #else
  323. # ifdef CONFIG_DM_PCI
  324. dm_pci_read_config16(dev, 0x0a, &cc);
  325. # else
  326. pci_read_config_word(pdev, 0x0a, &cc);
  327. # endif
  328. if (cc == 0x0101)
  329. scc_s = "IDE";
  330. else if (cc == 0x0106)
  331. scc_s = "SATA";
  332. else if (cc == 0x0104)
  333. scc_s = "RAID";
  334. else
  335. scc_s = "unknown";
  336. #endif
  337. printf("AHCI %02x%02x.%02x%02x "
  338. "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
  339. (vers >> 24) & 0xff,
  340. (vers >> 16) & 0xff,
  341. (vers >> 8) & 0xff,
  342. vers & 0xff,
  343. ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
  344. printf("flags: "
  345. "%s%s%s%s%s%s%s"
  346. "%s%s%s%s%s%s%s"
  347. "%s%s%s%s%s%s\n",
  348. cap & (1 << 31) ? "64bit " : "",
  349. cap & (1 << 30) ? "ncq " : "",
  350. cap & (1 << 28) ? "ilck " : "",
  351. cap & (1 << 27) ? "stag " : "",
  352. cap & (1 << 26) ? "pm " : "",
  353. cap & (1 << 25) ? "led " : "",
  354. cap & (1 << 24) ? "clo " : "",
  355. cap & (1 << 19) ? "nz " : "",
  356. cap & (1 << 18) ? "only " : "",
  357. cap & (1 << 17) ? "pmp " : "",
  358. cap & (1 << 16) ? "fbss " : "",
  359. cap & (1 << 15) ? "pio " : "",
  360. cap & (1 << 14) ? "slum " : "",
  361. cap & (1 << 13) ? "part " : "",
  362. cap & (1 << 7) ? "ccc " : "",
  363. cap & (1 << 6) ? "ems " : "",
  364. cap & (1 << 5) ? "sxs " : "",
  365. cap2 & (1 << 2) ? "apst " : "",
  366. cap2 & (1 << 1) ? "nvmp " : "",
  367. cap2 & (1 << 0) ? "boh " : "");
  368. }
  369. #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
  370. # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
  371. static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
  372. # else
  373. static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
  374. # endif
  375. {
  376. #if !defined(CONFIG_DM_SCSI)
  377. u16 vendor;
  378. #endif
  379. int rc;
  380. uc_priv->dev = dev;
  381. uc_priv->host_flags = ATA_FLAG_SATA
  382. | ATA_FLAG_NO_LEGACY
  383. | ATA_FLAG_MMIO
  384. | ATA_FLAG_PIO_DMA
  385. | ATA_FLAG_NO_ATAPI;
  386. uc_priv->pio_mask = 0x1f;
  387. uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  388. #if !defined(CONFIG_DM_SCSI)
  389. #ifdef CONFIG_DM_PCI
  390. uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
  391. PCI_REGION_MEM);
  392. /* Take from kernel:
  393. * JMicron-specific fixup:
  394. * make sure we're in AHCI mode
  395. */
  396. dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
  397. if (vendor == 0x197b)
  398. dm_pci_write_config8(dev, 0x41, 0xa1);
  399. #else
  400. uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
  401. PCI_REGION_MEM);
  402. /* Take from kernel:
  403. * JMicron-specific fixup:
  404. * make sure we're in AHCI mode
  405. */
  406. pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
  407. if (vendor == 0x197b)
  408. pci_write_config_byte(dev, 0x41, 0xa1);
  409. #endif
  410. #else
  411. struct scsi_platdata *plat = dev_get_uclass_platdata(dev);
  412. uc_priv->mmio_base = (void *)plat->base;
  413. #endif
  414. debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
  415. /* initialize adapter */
  416. rc = ahci_host_init(uc_priv);
  417. if (rc)
  418. goto err_out;
  419. ahci_print_info(uc_priv);
  420. return 0;
  421. err_out:
  422. return rc;
  423. }
  424. #endif
  425. #define MAX_DATA_BYTE_COUNT (4*1024*1024)
  426. static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
  427. unsigned char *buf, int buf_len)
  428. {
  429. struct ahci_ioports *pp = &(uc_priv->port[port]);
  430. struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
  431. u32 sg_count;
  432. int i;
  433. sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
  434. if (sg_count > AHCI_MAX_SG) {
  435. printf("Error:Too much sg!\n");
  436. return -1;
  437. }
  438. for (i = 0; i < sg_count; i++) {
  439. /* We assume virt=phys */
  440. phys_addr_t pa = (unsigned long)buf + i * MAX_DATA_BYTE_COUNT;
  441. ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
  442. ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
  443. if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
  444. printf("Error: DMA address too high\n");
  445. return -1;
  446. }
  447. ahci_sg->flags_size = cpu_to_le32(0x3fffff &
  448. (buf_len < MAX_DATA_BYTE_COUNT
  449. ? (buf_len - 1)
  450. : (MAX_DATA_BYTE_COUNT - 1)));
  451. ahci_sg++;
  452. buf_len -= MAX_DATA_BYTE_COUNT;
  453. }
  454. return sg_count;
  455. }
  456. static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
  457. {
  458. pp->cmd_slot->opts = cpu_to_le32(opts);
  459. pp->cmd_slot->status = 0;
  460. pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
  461. #ifdef CONFIG_PHYS_64BIT
  462. pp->cmd_slot->tbl_addr_hi =
  463. cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
  464. #endif
  465. }
  466. static int wait_spinup(void __iomem *port_mmio)
  467. {
  468. ulong start;
  469. u32 tf_data;
  470. start = get_timer(0);
  471. do {
  472. tf_data = readl(port_mmio + PORT_TFDATA);
  473. if (!(tf_data & ATA_BUSY))
  474. return 0;
  475. } while (get_timer(start) < WAIT_MS_SPINUP);
  476. return -ETIMEDOUT;
  477. }
  478. static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
  479. {
  480. struct ahci_ioports *pp = &(uc_priv->port[port]);
  481. void __iomem *port_mmio = pp->port_mmio;
  482. u64 dma_addr;
  483. u32 port_status;
  484. void __iomem *mem;
  485. debug("Enter start port: %d\n", port);
  486. port_status = readl(port_mmio + PORT_SCR_STAT);
  487. debug("Port %d status: %x\n", port, port_status);
  488. if ((port_status & 0xf) != 0x03) {
  489. printf("No Link on this port!\n");
  490. return -1;
  491. }
  492. mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
  493. if (!mem) {
  494. free(pp);
  495. printf("%s: No mem for table!\n", __func__);
  496. return -ENOMEM;
  497. }
  498. memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
  499. /*
  500. * First item in chunk of DMA memory: 32-slot command table,
  501. * 32 bytes each in size
  502. */
  503. pp->cmd_slot =
  504. (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
  505. debug("cmd_slot = %p\n", pp->cmd_slot);
  506. mem += (AHCI_CMD_SLOT_SZ + 224);
  507. /*
  508. * Second item: Received-FIS area
  509. */
  510. pp->rx_fis = virt_to_phys((void *)mem);
  511. mem += AHCI_RX_FIS_SZ;
  512. /*
  513. * Third item: data area for storing a single command
  514. * and its scatter-gather table
  515. */
  516. pp->cmd_tbl = virt_to_phys((void *)mem);
  517. debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
  518. mem += AHCI_CMD_TBL_HDR;
  519. pp->cmd_tbl_sg =
  520. (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
  521. dma_addr = (ulong)pp->cmd_slot;
  522. writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
  523. writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
  524. dma_addr = (ulong)pp->rx_fis;
  525. writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
  526. writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
  527. #ifdef CONFIG_SUNXI_AHCI
  528. sunxi_dma_init(port_mmio);
  529. #endif
  530. writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
  531. PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
  532. PORT_CMD_START, port_mmio + PORT_CMD);
  533. debug("Exit start port %d\n", port);
  534. /*
  535. * Make sure interface is not busy based on error and status
  536. * information from task file data register before proceeding
  537. */
  538. return wait_spinup(port_mmio);
  539. }
  540. static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
  541. int fis_len, u8 *buf, int buf_len, u8 is_write)
  542. {
  543. struct ahci_ioports *pp = &(uc_priv->port[port]);
  544. void __iomem *port_mmio = pp->port_mmio;
  545. u32 opts;
  546. u32 port_status;
  547. int sg_count;
  548. debug("Enter %s: for port %d\n", __func__, port);
  549. if (port > uc_priv->n_ports) {
  550. printf("Invalid port number %d\n", port);
  551. return -1;
  552. }
  553. port_status = readl(port_mmio + PORT_SCR_STAT);
  554. if ((port_status & 0xf) != 0x03) {
  555. debug("No Link on port %d!\n", port);
  556. return -1;
  557. }
  558. memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
  559. sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
  560. opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
  561. ahci_fill_cmd_slot(pp, opts);
  562. ahci_dcache_flush_sata_cmd(pp);
  563. ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
  564. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  565. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  566. WAIT_MS_DATAIO, 0x1)) {
  567. printf("timeout exit!\n");
  568. return -1;
  569. }
  570. ahci_dcache_invalidate_range((unsigned long)buf,
  571. (unsigned long)buf_len);
  572. debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
  573. return 0;
  574. }
  575. static char *ata_id_strcpy(u16 *target, u16 *src, int len)
  576. {
  577. int i;
  578. for (i = 0; i < len / 2; i++)
  579. target[i] = swab16(src[i]);
  580. return (char *)target;
  581. }
  582. /*
  583. * SCSI INQUIRY command operation.
  584. */
  585. static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
  586. struct scsi_cmd *pccb)
  587. {
  588. static const u8 hdr[] = {
  589. 0,
  590. 0,
  591. 0x5, /* claim SPC-3 version compatibility */
  592. 2,
  593. 95 - 4,
  594. };
  595. u8 fis[20];
  596. u16 *idbuf;
  597. ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
  598. u8 port;
  599. /* Clean ccb data buffer */
  600. memset(pccb->pdata, 0, pccb->datalen);
  601. memcpy(pccb->pdata, hdr, sizeof(hdr));
  602. if (pccb->datalen <= 35)
  603. return 0;
  604. memset(fis, 0, sizeof(fis));
  605. /* Construct the FIS */
  606. fis[0] = 0x27; /* Host to device FIS. */
  607. fis[1] = 1 << 7; /* Command FIS. */
  608. fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
  609. /* Read id from sata */
  610. port = pccb->target;
  611. if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
  612. (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
  613. debug("scsi_ahci: SCSI inquiry command failure.\n");
  614. return -EIO;
  615. }
  616. if (!uc_priv->ataid[port]) {
  617. uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
  618. if (!uc_priv->ataid[port]) {
  619. printf("%s: No memory for ataid[port]\n", __func__);
  620. return -ENOMEM;
  621. }
  622. }
  623. idbuf = uc_priv->ataid[port];
  624. memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
  625. ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
  626. memcpy(&pccb->pdata[8], "ATA ", 8);
  627. ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
  628. ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
  629. #ifdef DEBUG
  630. ata_dump_id(idbuf);
  631. #endif
  632. return 0;
  633. }
  634. /*
  635. * SCSI READ10/WRITE10 command operation.
  636. */
  637. static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
  638. struct scsi_cmd *pccb, u8 is_write)
  639. {
  640. lbaint_t lba = 0;
  641. u16 blocks = 0;
  642. u8 fis[20];
  643. u8 *user_buffer = pccb->pdata;
  644. u32 user_buffer_size = pccb->datalen;
  645. /* Retrieve the base LBA number from the ccb structure. */
  646. if (pccb->cmd[0] == SCSI_READ16) {
  647. memcpy(&lba, pccb->cmd + 2, 8);
  648. lba = be64_to_cpu(lba);
  649. } else {
  650. u32 temp;
  651. memcpy(&temp, pccb->cmd + 2, 4);
  652. lba = be32_to_cpu(temp);
  653. }
  654. /*
  655. * Retrieve the base LBA number and the block count from
  656. * the ccb structure.
  657. *
  658. * For 10-byte and 16-byte SCSI R/W commands, transfer
  659. * length 0 means transfer 0 block of data.
  660. * However, for ATA R/W commands, sector count 0 means
  661. * 256 or 65536 sectors, not 0 sectors as in SCSI.
  662. *
  663. * WARNING: one or two older ATA drives treat 0 as 0...
  664. */
  665. if (pccb->cmd[0] == SCSI_READ16)
  666. blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
  667. else
  668. blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
  669. debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
  670. is_write ? "write" : "read", blocks, lba);
  671. /* Preset the FIS */
  672. memset(fis, 0, sizeof(fis));
  673. fis[0] = 0x27; /* Host to device FIS. */
  674. fis[1] = 1 << 7; /* Command FIS. */
  675. /* Command byte (read/write). */
  676. fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
  677. while (blocks) {
  678. u16 now_blocks; /* number of blocks per iteration */
  679. u32 transfer_size; /* number of bytes per iteration */
  680. now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
  681. transfer_size = ATA_SECT_SIZE * now_blocks;
  682. if (transfer_size > user_buffer_size) {
  683. printf("scsi_ahci: Error: buffer too small.\n");
  684. return -EIO;
  685. }
  686. /*
  687. * LBA48 SATA command but only use 32bit address range within
  688. * that (unless we've enabled 64bit LBA support). The next
  689. * smaller command range (28bit) is too small.
  690. */
  691. fis[4] = (lba >> 0) & 0xff;
  692. fis[5] = (lba >> 8) & 0xff;
  693. fis[6] = (lba >> 16) & 0xff;
  694. fis[7] = 1 << 6; /* device reg: set LBA mode */
  695. fis[8] = ((lba >> 24) & 0xff);
  696. #ifdef CONFIG_SYS_64BIT_LBA
  697. if (pccb->cmd[0] == SCSI_READ16) {
  698. fis[9] = ((lba >> 32) & 0xff);
  699. fis[10] = ((lba >> 40) & 0xff);
  700. }
  701. #endif
  702. fis[3] = 0xe0; /* features */
  703. /* Block (sector) count */
  704. fis[12] = (now_blocks >> 0) & 0xff;
  705. fis[13] = (now_blocks >> 8) & 0xff;
  706. /* Read/Write from ahci */
  707. if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
  708. sizeof(fis), user_buffer, transfer_size,
  709. is_write)) {
  710. debug("scsi_ahci: SCSI %s10 command failure.\n",
  711. is_write ? "WRITE" : "READ");
  712. return -EIO;
  713. }
  714. /* If this transaction is a write, do a following flush.
  715. * Writes in u-boot are so rare, and the logic to know when is
  716. * the last write and do a flush only there is sufficiently
  717. * difficult. Just do a flush after every write. This incurs,
  718. * usually, one extra flush when the rare writes do happen.
  719. */
  720. if (is_write) {
  721. if (-EIO == ata_io_flush(uc_priv, pccb->target))
  722. return -EIO;
  723. }
  724. user_buffer += transfer_size;
  725. user_buffer_size -= transfer_size;
  726. blocks -= now_blocks;
  727. lba += now_blocks;
  728. }
  729. return 0;
  730. }
  731. /*
  732. * SCSI READ CAPACITY10 command operation.
  733. */
  734. static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
  735. struct scsi_cmd *pccb)
  736. {
  737. u32 cap;
  738. u64 cap64;
  739. u32 block_size;
  740. if (!uc_priv->ataid[pccb->target]) {
  741. printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
  742. "\tNo ATA info!\n"
  743. "\tPlease run SCSI command INQUIRY first!\n");
  744. return -EPERM;
  745. }
  746. cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  747. if (cap64 > 0x100000000ULL)
  748. cap64 = 0xffffffff;
  749. cap = cpu_to_be32(cap64);
  750. memcpy(pccb->pdata, &cap, sizeof(cap));
  751. block_size = cpu_to_be32((u32)512);
  752. memcpy(&pccb->pdata[4], &block_size, 4);
  753. return 0;
  754. }
  755. /*
  756. * SCSI READ CAPACITY16 command operation.
  757. */
  758. static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
  759. struct scsi_cmd *pccb)
  760. {
  761. u64 cap;
  762. u64 block_size;
  763. if (!uc_priv->ataid[pccb->target]) {
  764. printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
  765. "\tNo ATA info!\n"
  766. "\tPlease run SCSI command INQUIRY first!\n");
  767. return -EPERM;
  768. }
  769. cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
  770. cap = cpu_to_be64(cap);
  771. memcpy(pccb->pdata, &cap, sizeof(cap));
  772. block_size = cpu_to_be64((u64)512);
  773. memcpy(&pccb->pdata[8], &block_size, 8);
  774. return 0;
  775. }
  776. /*
  777. * SCSI TEST UNIT READY command operation.
  778. */
  779. static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
  780. struct scsi_cmd *pccb)
  781. {
  782. return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
  783. }
  784. static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
  785. {
  786. struct ahci_uc_priv *uc_priv;
  787. #ifdef CONFIG_DM_SCSI
  788. uc_priv = dev_get_uclass_priv(dev->parent);
  789. #else
  790. uc_priv = probe_ent;
  791. #endif
  792. int ret;
  793. switch (pccb->cmd[0]) {
  794. case SCSI_READ16:
  795. case SCSI_READ10:
  796. ret = ata_scsiop_read_write(uc_priv, pccb, 0);
  797. break;
  798. case SCSI_WRITE10:
  799. ret = ata_scsiop_read_write(uc_priv, pccb, 1);
  800. break;
  801. case SCSI_RD_CAPAC10:
  802. ret = ata_scsiop_read_capacity10(uc_priv, pccb);
  803. break;
  804. case SCSI_RD_CAPAC16:
  805. ret = ata_scsiop_read_capacity16(uc_priv, pccb);
  806. break;
  807. case SCSI_TST_U_RDY:
  808. ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
  809. break;
  810. case SCSI_INQUIRY:
  811. ret = ata_scsiop_inquiry(uc_priv, pccb);
  812. break;
  813. default:
  814. printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
  815. return -ENOTSUPP;
  816. }
  817. if (ret) {
  818. debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
  819. return ret;
  820. }
  821. return 0;
  822. }
  823. static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
  824. {
  825. u32 linkmap;
  826. int i;
  827. linkmap = uc_priv->link_port_map;
  828. for (i = 0; i < uc_priv->n_ports; i++) {
  829. if (((linkmap >> i) & 0x01)) {
  830. if (ahci_port_start(uc_priv, (u8) i)) {
  831. printf("Can not start port %d\n", i);
  832. continue;
  833. }
  834. }
  835. }
  836. return 0;
  837. }
  838. #ifndef CONFIG_DM_SCSI
  839. void scsi_low_level_init(int busdevfunc)
  840. {
  841. struct ahci_uc_priv *uc_priv;
  842. #ifndef CONFIG_SCSI_AHCI_PLAT
  843. probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
  844. if (!probe_ent) {
  845. printf("%s: No memory for uc_priv\n", __func__);
  846. return;
  847. }
  848. uc_priv = probe_ent;
  849. # if defined(CONFIG_DM_PCI)
  850. struct udevice *dev;
  851. int ret;
  852. ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
  853. if (ret)
  854. return;
  855. ahci_init_one(uc_priv, dev);
  856. # else
  857. ahci_init_one(uc_priv, busdevfunc);
  858. # endif
  859. #else
  860. uc_priv = probe_ent;
  861. #endif
  862. ahci_start_ports(uc_priv);
  863. }
  864. #endif
  865. #ifndef CONFIG_SCSI_AHCI_PLAT
  866. # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
  867. int ahci_init_one_dm(struct udevice *dev)
  868. {
  869. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  870. return ahci_init_one(uc_priv, dev);
  871. }
  872. #endif
  873. #endif
  874. int ahci_start_ports_dm(struct udevice *dev)
  875. {
  876. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  877. return ahci_start_ports(uc_priv);
  878. }
  879. #ifdef CONFIG_SCSI_AHCI_PLAT
  880. static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
  881. {
  882. int rc;
  883. uc_priv->host_flags = ATA_FLAG_SATA
  884. | ATA_FLAG_NO_LEGACY
  885. | ATA_FLAG_MMIO
  886. | ATA_FLAG_PIO_DMA
  887. | ATA_FLAG_NO_ATAPI;
  888. uc_priv->pio_mask = 0x1f;
  889. uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
  890. uc_priv->mmio_base = base;
  891. /* initialize adapter */
  892. rc = ahci_host_init(uc_priv);
  893. if (rc)
  894. goto err_out;
  895. ahci_print_info(uc_priv);
  896. rc = ahci_start_ports(uc_priv);
  897. err_out:
  898. return rc;
  899. }
  900. #ifndef CONFIG_DM_SCSI
  901. int ahci_init(void __iomem *base)
  902. {
  903. struct ahci_uc_priv *uc_priv;
  904. probe_ent = malloc(sizeof(struct ahci_uc_priv));
  905. if (!probe_ent) {
  906. printf("%s: No memory for uc_priv\n", __func__);
  907. return -ENOMEM;
  908. }
  909. uc_priv = probe_ent;
  910. memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
  911. return ahci_init_common(uc_priv, base);
  912. }
  913. #endif
  914. int ahci_init_dm(struct udevice *dev, void __iomem *base)
  915. {
  916. struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
  917. return ahci_init_common(uc_priv, base);
  918. }
  919. void __weak scsi_init(void)
  920. {
  921. }
  922. #endif /* CONFIG_SCSI_AHCI_PLAT */
  923. /*
  924. * In the general case of generic rotating media it makes sense to have a
  925. * flush capability. It probably even makes sense in the case of SSDs because
  926. * one cannot always know for sure what kind of internal cache/flush mechanism
  927. * is embodied therein. At first it was planned to invoke this after the last
  928. * write to disk and before rebooting. In practice, knowing, a priori, which
  929. * is the last write is difficult. Because writing to the disk in u-boot is
  930. * very rare, this flush command will be invoked after every block write.
  931. */
  932. static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
  933. {
  934. u8 fis[20];
  935. struct ahci_ioports *pp = &(uc_priv->port[port]);
  936. void __iomem *port_mmio = pp->port_mmio;
  937. u32 cmd_fis_len = 5; /* five dwords */
  938. /* Preset the FIS */
  939. memset(fis, 0, 20);
  940. fis[0] = 0x27; /* Host to device FIS. */
  941. fis[1] = 1 << 7; /* Command FIS. */
  942. fis[2] = ATA_CMD_FLUSH_EXT;
  943. memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
  944. ahci_fill_cmd_slot(pp, cmd_fis_len);
  945. ahci_dcache_flush_sata_cmd(pp);
  946. writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
  947. if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
  948. WAIT_MS_FLUSH, 0x1)) {
  949. debug("scsi_ahci: flush command timeout on port %d.\n", port);
  950. return -EIO;
  951. }
  952. return 0;
  953. }
  954. static int ahci_scsi_bus_reset(struct udevice *dev)
  955. {
  956. /* Not implemented */
  957. return 0;
  958. }
  959. #ifdef CONFIG_DM_SCSI
  960. int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
  961. {
  962. struct udevice *dev;
  963. int ret;
  964. ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
  965. if (ret)
  966. return ret;
  967. *devp = dev;
  968. return 0;
  969. }
  970. int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
  971. {
  972. struct ahci_uc_priv *uc_priv;
  973. struct scsi_platdata *uc_plat;
  974. struct udevice *dev;
  975. int ret;
  976. device_find_first_child(ahci_dev, &dev);
  977. if (!dev)
  978. return -ENODEV;
  979. uc_plat = dev_get_uclass_platdata(dev);
  980. uc_plat->base = base;
  981. uc_plat->max_lun = 1;
  982. uc_plat->max_id = 2;
  983. uc_priv = dev_get_uclass_priv(ahci_dev);
  984. ret = ahci_init_one(uc_priv, dev);
  985. if (ret)
  986. return ret;
  987. ret = ahci_start_ports(uc_priv);
  988. if (ret)
  989. return ret;
  990. /*
  991. * scsi_scan_dev() scans devices up-to the number of max_id.
  992. * Update max_id if the number of detected ports exceeds max_id.
  993. * This allows SCSI to scan all detected ports.
  994. */
  995. uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
  996. uc_plat->max_id);
  997. return 0;
  998. }
  999. #ifdef CONFIG_DM_PCI
  1000. int ahci_probe_scsi_pci(struct udevice *ahci_dev)
  1001. {
  1002. ulong base;
  1003. base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
  1004. PCI_REGION_MEM);
  1005. return ahci_probe_scsi(ahci_dev, base);
  1006. }
  1007. #endif
  1008. struct scsi_ops scsi_ops = {
  1009. .exec = ahci_scsi_exec,
  1010. .bus_reset = ahci_scsi_bus_reset,
  1011. };
  1012. U_BOOT_DRIVER(ahci_scsi) = {
  1013. .name = "ahci_scsi",
  1014. .id = UCLASS_SCSI,
  1015. .ops = &scsi_ops,
  1016. };
  1017. #else
  1018. int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
  1019. {
  1020. return ahci_scsi_exec(dev, pccb);
  1021. }
  1022. __weak int scsi_bus_reset(struct udevice *dev)
  1023. {
  1024. return ahci_scsi_bus_reset(dev);
  1025. return 0;
  1026. }
  1027. #endif