M54418TWR.h 9.5 KB

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  1. /*
  2. * Configuation settings for the Freescale MCF54418 TWR board.
  3. *
  4. * Copyright 2010-2012 Freescale Semiconductor, Inc.
  5. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  6. *
  7. * SPDX-License-Identifier: GPL-2.0+
  8. */
  9. /*
  10. * board/config.h - configuration options, board specific
  11. */
  12. #ifndef _M54418TWR_H
  13. #define _M54418TWR_H
  14. /*
  15. * High Level Configuration Options
  16. * (easy to change)
  17. */
  18. #define CONFIG_MCFUART
  19. #define CONFIG_SYS_UART_PORT (0)
  20. #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
  21. #define LDS_BOARD_TEXT board/freescale/m54418twr/sbf_dram_init.o (.text*)
  22. #undef CONFIG_WATCHDOG
  23. #define CONFIG_TIMESTAMP /* Print image info with timestamp */
  24. /*
  25. * BOOTP options
  26. */
  27. #define CONFIG_BOOTP_BOOTFILESIZE
  28. #define CONFIG_BOOTP_BOOTPATH
  29. #define CONFIG_BOOTP_GATEWAY
  30. #define CONFIG_BOOTP_HOSTNAME
  31. /*
  32. * NAND FLASH
  33. */
  34. #ifdef CONFIG_CMD_NAND
  35. #define CONFIG_JFFS2_NAND
  36. #define CONFIG_NAND_FSL_NFC
  37. #define CONFIG_SYS_NAND_BASE 0xFC0FC000
  38. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  39. #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
  40. #define CONFIG_SYS_NAND_SELECT_DEVICE
  41. #endif
  42. /* Network configuration */
  43. #define CONFIG_MCFFEC
  44. #ifdef CONFIG_MCFFEC
  45. #define CONFIG_MII 1
  46. #define CONFIG_MII_INIT 1
  47. #define CONFIG_SYS_DISCOVER_PHY
  48. #define CONFIG_SYS_RX_ETH_BUFFER 2
  49. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  50. #define CONFIG_SYS_TX_ETH_BUFFER 2
  51. #define CONFIG_HAS_ETH1
  52. #define CONFIG_SYS_FEC0_PINMUX 0
  53. #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
  54. #define CONFIG_SYS_FEC1_PINMUX 0
  55. #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE
  56. #define MCFFEC_TOUT_LOOP 50000
  57. #define CONFIG_SYS_FEC0_PHYADDR 0
  58. #define CONFIG_SYS_FEC1_PHYADDR 1
  59. #define CONFIG_ETHPRIME "FEC0"
  60. #define CONFIG_IPADDR 192.168.1.2
  61. #define CONFIG_NETMASK 255.255.255.0
  62. #define CONFIG_SERVERIP 192.168.1.1
  63. #define CONFIG_GATEWAYIP 192.168.1.1
  64. #define CONFIG_SYS_FEC_BUF_USE_SRAM
  65. /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  66. #ifndef CONFIG_SYS_DISCOVER_PHY
  67. #define FECDUPLEX FULL
  68. #define FECSPEED _100BASET
  69. #define LINKSTATUS 1
  70. #else
  71. #define LINKSTATUS 0
  72. #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  73. #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  74. #endif
  75. #endif /* CONFIG_SYS_DISCOVER_PHY */
  76. #endif
  77. #define CONFIG_HOSTNAME M54418TWR
  78. #if defined(CONFIG_CF_SBF)
  79. /* ST Micro serial flash */
  80. #define CONFIG_SYS_LOAD_ADDR2 0x40010007
  81. #define CONFIG_EXTRA_ENV_SETTINGS \
  82. "netdev=eth0\0" \
  83. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  84. "loadaddr=0x40010000\0" \
  85. "sbfhdr=sbfhdr.bin\0" \
  86. "uboot=u-boot.bin\0" \
  87. "load=tftp ${loadaddr} ${sbfhdr};" \
  88. "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
  89. "upd=run load; run prog\0" \
  90. "prog=sf probe 0:1 1000000 3;" \
  91. "sf erase 0 40000;" \
  92. "sf write ${loadaddr} 0 40000;" \
  93. "save\0" \
  94. ""
  95. #elif defined(CONFIG_SYS_NAND_BOOT)
  96. #define CONFIG_EXTRA_ENV_SETTINGS \
  97. "netdev=eth0\0" \
  98. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  99. "loadaddr=0x40010000\0" \
  100. "u-boot=u-boot.bin\0" \
  101. "load=tftp ${loadaddr} ${u-boot};\0" \
  102. "upd=run load; run prog\0" \
  103. "prog=nand device 0;" \
  104. "nand erase 0 40000;" \
  105. "nb_update ${loadaddr} ${filesize};" \
  106. "save\0" \
  107. ""
  108. #else
  109. #define CONFIG_SYS_UBOOT_END 0x3FFFF
  110. #define CONFIG_EXTRA_ENV_SETTINGS \
  111. "netdev=eth0\0" \
  112. "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
  113. "loadaddr=40010000\0" \
  114. "u-boot=u-boot.bin\0" \
  115. "load=tftp ${loadaddr) ${u-boot}\0" \
  116. "upd=run load; run prog\0" \
  117. "prog=prot off mram" " ;" \
  118. "cp.b ${loadaddr} 0 ${filesize};" \
  119. "save\0" \
  120. ""
  121. #endif
  122. /* Realtime clock */
  123. #undef CONFIG_MCFRTC
  124. #define CONFIG_RTC_MCFRRTC
  125. #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000
  126. /* Timer */
  127. #define CONFIG_MCFTMR
  128. #undef CONFIG_MCFPIT
  129. /* I2c */
  130. #undef CONFIG_SYS_FSL_I2C
  131. #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
  132. /* I2C speed and slave address */
  133. #define CONFIG_SYS_I2C_SPEED 80000
  134. #define CONFIG_SYS_I2C_SLAVE 0x7F
  135. #define CONFIG_SYS_I2C_OFFSET 0x58000
  136. #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
  137. /* DSPI and Serial Flash */
  138. #define CONFIG_CF_SPI
  139. #define CONFIG_CF_DSPI
  140. #define CONFIG_SERIAL_FLASH
  141. #define CONFIG_HARD_SPI
  142. #define CONFIG_SYS_SBFHDR_SIZE 0x7
  143. #ifdef CONFIG_CMD_SPI
  144. # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
  145. DSPI_CTAR_PCSSCK_1CLK | \
  146. DSPI_CTAR_PASC(0) | \
  147. DSPI_CTAR_PDT(0) | \
  148. DSPI_CTAR_CSSCK(0) | \
  149. DSPI_CTAR_ASC(0) | \
  150. DSPI_CTAR_DT(1))
  151. # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
  152. # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
  153. #endif
  154. /* Input, PCI, Flexbus, and VCO */
  155. #define CONFIG_EXTRA_CLOCK
  156. #define CONFIG_PRAM 2048 /* 2048 KB */
  157. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  158. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
  159. #define CONFIG_SYS_MBAR 0xFC000000
  160. /*
  161. * Low Level Configuration Settings
  162. * (address mappings, register initial values, etc.)
  163. * You should know what you are doing if you make changes here.
  164. */
  165. /*-----------------------------------------------------------------------
  166. * Definitions for initial stack pointer and data area (in DPRAM)
  167. */
  168. #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
  169. /* End of used area in internal SRAM */
  170. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000
  171. #define CONFIG_SYS_INIT_RAM_CTRL 0x221
  172. #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \
  173. GENERATED_GBL_DATA_SIZE) - 32)
  174. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  175. #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
  176. /*-----------------------------------------------------------------------
  177. * Start addresses for the final memory configuration
  178. * (Set up by the startup code)
  179. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  180. */
  181. #define CONFIG_SYS_SDRAM_BASE 0x40000000
  182. #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
  183. #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400)
  184. #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
  185. #define CONFIG_SYS_DRAM_TEST
  186. #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
  187. #define CONFIG_SERIAL_BOOT
  188. #endif
  189. #if defined(CONFIG_SERIAL_BOOT)
  190. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
  191. #else
  192. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  193. #endif
  194. #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024)
  195. /* Reserve 256 kB for Monitor */
  196. #define CONFIG_SYS_MONITOR_LEN (256 << 10)
  197. /* Reserve 256 kB for malloc() */
  198. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  199. /*
  200. * For booting Linux, the board info and command line data
  201. * have to be in the first 8 MB of memory, since this is
  202. * the maximum mapped by the Linux kernel during initialization ??
  203. */
  204. /* Initial Memory map for Linux */
  205. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \
  206. (CONFIG_SYS_SDRAM_SIZE << 20))
  207. /* Configuration for environment
  208. * Environment is embedded in u-boot in the second sector of the flash
  209. */
  210. #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/
  211. #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/
  212. #define CONFIG_ENV_SIZE 0x1000
  213. #endif
  214. #if defined(CONFIG_CF_SBF)
  215. #define CONFIG_ENV_SPI_CS 1
  216. #define CONFIG_ENV_OFFSET 0x40000
  217. #define CONFIG_ENV_SIZE 0x2000
  218. #define CONFIG_ENV_SECT_SIZE 0x10000
  219. #endif
  220. #if defined(CONFIG_SYS_NAND_BOOT)
  221. #define CONFIG_ENV_OFFSET 0x80000
  222. #define CONFIG_ENV_SIZE 0x20000
  223. #define CONFIG_ENV_SECT_SIZE 0x20000
  224. #endif
  225. #undef CONFIG_ENV_OVERWRITE
  226. /* FLASH organization */
  227. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  228. #undef CONFIG_SYS_FLASH_CFI
  229. #ifdef CONFIG_SYS_FLASH_CFI
  230. #define CONFIG_FLASH_CFI_DRIVER 1
  231. /* Max size that the board might have */
  232. #define CONFIG_SYS_FLASH_SIZE 0x1000000
  233. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  234. /* max number of memory banks */
  235. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  236. /* max number of sectors on one chip */
  237. #define CONFIG_SYS_MAX_FLASH_SECT 270
  238. /* "Real" (hardware) sectors protection */
  239. #define CONFIG_SYS_FLASH_PROTECTION
  240. #define CONFIG_SYS_FLASH_CHECKSUM
  241. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
  242. #else
  243. /* max number of sectors on one chip */
  244. #define CONFIG_SYS_MAX_FLASH_SECT 270
  245. /* max number of sectors on one chip */
  246. #define CONFIG_SYS_MAX_FLASH_BANKS 0
  247. #endif
  248. /*
  249. * This is setting for JFFS2 support in u-boot.
  250. * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
  251. */
  252. #ifdef CONFIG_CMD_JFFS2
  253. #define CONFIG_JFFS2_DEV "nand0"
  254. #define CONFIG_JFFS2_PART_OFFSET (0x800000)
  255. #define CONFIG_MTD_DEVICE
  256. #endif
  257. #ifdef CONFIG_CMD_UBI
  258. #define CONFIG_MTD_DEVICE /* needed for mtdparts command */
  259. #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */
  260. #endif
  261. /* Cache Configuration */
  262. #define CONFIG_SYS_CACHELINE_SIZE 16
  263. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  264. CONFIG_SYS_INIT_RAM_SIZE - 8)
  265. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  266. CONFIG_SYS_INIT_RAM_SIZE - 4)
  267. #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
  268. #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
  269. #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
  270. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  271. CF_ACR_EN | CF_ACR_SM_ALL)
  272. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
  273. CF_CACR_ICINVA | CF_CACR_EUSP)
  274. #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
  275. CF_CACR_DEC | CF_CACR_DDCM_P | \
  276. CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
  277. #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  278. CONFIG_SYS_INIT_RAM_SIZE - 12)
  279. /*-----------------------------------------------------------------------
  280. * Memory bank definitions
  281. */
  282. /*
  283. * CS0 - NOR Flash 16MB
  284. * CS1 - Available
  285. * CS2 - Available
  286. * CS3 - Available
  287. * CS4 - Available
  288. * CS5 - Available
  289. */
  290. /* Flash */
  291. #define CONFIG_SYS_CS0_BASE 0x00000000
  292. #define CONFIG_SYS_CS0_MASK 0x000F0101
  293. #define CONFIG_SYS_CS0_CTRL 0x00001D60
  294. #endif /* _M54418TWR_H */