M5253EVBE.h 5.1 KB

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  1. /*
  2. * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  3. * Hayden Fraser (Hayden.Fraser@freescale.com)
  4. *
  5. * SPDX-License-Identifier: GPL-2.0+
  6. */
  7. #ifndef _M5253EVBE_H
  8. #define _M5253EVBE_H
  9. #define CONFIG_MCFTMR
  10. #define CONFIG_MCFUART
  11. #define CONFIG_SYS_UART_PORT (0)
  12. #undef CONFIG_WATCHDOG /* disable watchdog */
  13. /* Configuration for environment
  14. * Environment is embedded in u-boot in the second sector of the flash
  15. */
  16. #ifndef CONFIG_MONITOR_IS_IN_RAM
  17. #define CONFIG_ENV_OFFSET 0x4000
  18. #define CONFIG_ENV_SECT_SIZE 0x2000
  19. #else
  20. #define CONFIG_ENV_ADDR 0xffe04000
  21. #define CONFIG_ENV_SECT_SIZE 0x2000
  22. #endif
  23. #define LDS_BOARD_TEXT \
  24. . = DEFINED(env_offset) ? env_offset : .; \
  25. env/embedded.o(.text)
  26. /*
  27. * BOOTP options
  28. */
  29. #undef CONFIG_BOOTP_BOOTFILESIZE
  30. #undef CONFIG_BOOTP_BOOTPATH
  31. #undef CONFIG_BOOTP_GATEWAY
  32. #undef CONFIG_BOOTP_HOSTNAME
  33. /*
  34. * Command line configuration.
  35. */
  36. /* ATA */
  37. #define CONFIG_IDE_RESET 1
  38. #define CONFIG_IDE_PREINIT 1
  39. #define CONFIG_ATAPI
  40. #undef CONFIG_LBA48
  41. #define CONFIG_SYS_IDE_MAXBUS 1
  42. #define CONFIG_SYS_IDE_MAXDEVICE 2
  43. #define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
  44. #define CONFIG_SYS_ATA_IDE0_OFFSET 0
  45. #define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
  46. #define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
  47. #define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
  48. #define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
  49. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  50. #define CONFIG_SYS_LOAD_ADDR 0x00100000
  51. #define CONFIG_SYS_MEMTEST_START 0x400
  52. #define CONFIG_SYS_MEMTEST_END 0x380000
  53. #undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
  54. #define CONFIG_SYS_FAST_CLK
  55. #ifdef CONFIG_SYS_FAST_CLK
  56. # define CONFIG_SYS_PLLCR 0x1243E054
  57. # define CONFIG_SYS_CLK 140000000
  58. #else
  59. # define CONFIG_SYS_PLLCR 0x135a4140
  60. # define CONFIG_SYS_CLK 70000000
  61. #endif
  62. /*
  63. * Low Level Configuration Settings
  64. * (address mappings, register initial values, etc.)
  65. * You should know what you are doing if you make changes here.
  66. */
  67. #define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
  68. #define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
  69. /*
  70. * Definitions for initial stack pointer and data area (in DPRAM)
  71. */
  72. #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
  73. #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
  74. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  75. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  76. /*
  77. * Start addresses for the final memory configuration
  78. * (Set up by the startup code)
  79. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  80. */
  81. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  82. #define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */
  83. #ifdef CONFIG_MONITOR_IS_IN_RAM
  84. #define CONFIG_SYS_MONITOR_BASE 0x20000
  85. #else
  86. #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
  87. #endif
  88. #define CONFIG_SYS_MONITOR_LEN 0x40000
  89. #define CONFIG_SYS_MALLOC_LEN (256 << 10)
  90. #define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
  91. /*
  92. * For booting Linux, the board info and command line data
  93. * have to be in the first 8 MB of memory, since this is
  94. * the maximum mapped by the Linux kernel during initialization ??
  95. */
  96. #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
  97. #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
  98. /* FLASH organization */
  99. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
  100. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  101. #define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
  102. #define CONFIG_SYS_FLASH_ERASE_TOUT 1000
  103. #define CONFIG_SYS_FLASH_CFI 1
  104. #define CONFIG_FLASH_CFI_DRIVER 1
  105. #define CONFIG_SYS_FLASH_SIZE 0x200000
  106. #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
  107. /* Cache Configuration */
  108. #define CONFIG_SYS_CACHELINE_SIZE 16
  109. #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  110. CONFIG_SYS_INIT_RAM_SIZE - 8)
  111. #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
  112. CONFIG_SYS_INIT_RAM_SIZE - 4)
  113. #define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
  114. #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE | \
  115. CF_ADDRMASK(2) | \
  116. CF_ACR_EN | CF_ACR_SM_ALL)
  117. #define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE | \
  118. CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
  119. CF_ACR_EN | CF_ACR_SM_ALL)
  120. #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CEIB | \
  121. CF_CACR_DBWE)
  122. /* Port configuration */
  123. #define CONFIG_SYS_FECI2C 0xF0
  124. #define CONFIG_SYS_CS0_BASE 0xFFE00000
  125. #define CONFIG_SYS_CS0_MASK 0x001F0021
  126. #define CONFIG_SYS_CS0_CTRL 0x00001D80
  127. /*-----------------------------------------------------------------------
  128. * Port configuration
  129. */
  130. #define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
  131. #define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
  132. #define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
  133. #define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
  134. #define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
  135. #define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
  136. #define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
  137. #endif /* _M5253EVB_H */