spl.c 3.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Copyright 2014 Freescale Semiconductor, Inc.
  3. */
  4. #include <common.h>
  5. #include <clock_legacy.h>
  6. #include <console.h>
  7. #include <env_internal.h>
  8. #include <init.h>
  9. #include <malloc.h>
  10. #include <ns16550.h>
  11. #include <nand.h>
  12. #include <i2c.h>
  13. #include <mmc.h>
  14. #include <fsl_esdhc.h>
  15. #include <spi_flash.h>
  16. #include "../common/sleep.h"
  17. #include "../common/spl.h"
  18. DECLARE_GLOBAL_DATA_PTR;
  19. phys_size_t get_effective_memsize(void)
  20. {
  21. return CONFIG_SYS_L3_SIZE;
  22. }
  23. unsigned long get_board_sys_clk(void)
  24. {
  25. return CONFIG_SYS_CLK_FREQ;
  26. }
  27. unsigned long get_board_ddr_clk(void)
  28. {
  29. return CONFIG_DDR_CLK_FREQ;
  30. }
  31. #if defined(CONFIG_SPL_MMC_BOOT)
  32. #define GPIO1_SD_SEL 0x00020000
  33. int board_mmc_getcd(struct mmc *mmc)
  34. {
  35. ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  36. u32 val = in_be32(&pgpio->gpdat);
  37. /* GPIO1_14, 0: eMMC, 1: SD */
  38. val &= GPIO1_SD_SEL;
  39. return val ? -1 : 1;
  40. }
  41. int board_mmc_getwp(struct mmc *mmc)
  42. {
  43. ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  44. u32 val = in_be32(&pgpio->gpdat);
  45. val &= GPIO1_SD_SEL;
  46. return val ? -1 : 0;
  47. }
  48. #endif
  49. void board_init_f(ulong bootflag)
  50. {
  51. u32 plat_ratio, sys_clk, ccb_clk;
  52. ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  53. /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
  54. memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
  55. /* Update GD pointer */
  56. gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
  57. console_init_f();
  58. #ifdef CONFIG_DEEP_SLEEP
  59. /* disable the console if boot from deep sleep */
  60. if (is_warm_boot())
  61. fsl_dp_disable_console();
  62. #endif
  63. /* initialize selected port with appropriate baud rate */
  64. sys_clk = get_board_sys_clk();
  65. plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
  66. ccb_clk = sys_clk * plat_ratio / 2;
  67. NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  68. ccb_clk / 16 / CONFIG_BAUDRATE);
  69. #if defined(CONFIG_SPL_MMC_BOOT)
  70. puts("\nSD boot...\n");
  71. #elif defined(CONFIG_SPL_SPI_BOOT)
  72. puts("\nSPI boot...\n");
  73. #elif defined(CONFIG_SPL_NAND_BOOT)
  74. puts("\nNAND boot...\n");
  75. #endif
  76. relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
  77. }
  78. void board_init_r(gd_t *gd, ulong dest_addr)
  79. {
  80. struct bd_info *bd;
  81. bd = (struct bd_info *)(gd + sizeof(gd_t));
  82. memset(bd, 0, sizeof(struct bd_info));
  83. gd->bd = bd;
  84. arch_cpu_init();
  85. get_clocks();
  86. mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  87. CONFIG_SPL_RELOC_MALLOC_SIZE);
  88. gd->flags |= GD_FLG_FULL_MALLOC_INIT;
  89. #ifdef CONFIG_SPL_NAND_BOOT
  90. nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  91. (uchar *)SPL_ENV_ADDR);
  92. #endif
  93. #ifdef CONFIG_SPL_MMC_BOOT
  94. mmc_initialize(bd);
  95. mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  96. (uchar *)SPL_ENV_ADDR);
  97. #endif
  98. #ifdef CONFIG_SPL_SPI_BOOT
  99. fsl_spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  100. (uchar *)SPL_ENV_ADDR);
  101. #endif
  102. gd->env_addr = (ulong)(SPL_ENV_ADDR);
  103. gd->env_valid = ENV_VALID;
  104. i2c_init_all();
  105. dram_init();
  106. #ifdef CONFIG_SPL_MMC_BOOT
  107. mmc_boot();
  108. #elif defined(CONFIG_SPL_SPI_BOOT)
  109. fsl_spi_boot();
  110. #elif defined(CONFIG_SPL_NAND_BOOT)
  111. nand_boot();
  112. #endif
  113. }