gpe.h 3.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * Copyright 2016 Intel Corporation
  4. * Copyright 2020 Google LLC
  5. *
  6. * Taken from coreboot apl gpe.h
  7. */
  8. #ifndef _ASM_ARCH_GPE_H_
  9. #define _ASM_ARCH_GPE_H_
  10. /* bit position in GPE0a_STS register */
  11. #define GPE0A_PCIE_SCI_STS 0
  12. #define GPE0A_SWGPE_STS 2
  13. #define GPE0A_PCIE_WAKE0_STS 3
  14. #define GPE0A_PUNIT_SCI_STS 4
  15. #define GPE0A_PCIE_WAKE1_STS 6
  16. #define GPE0A_PCIE_WAKE2_STS 7
  17. #define GPE0A_PCIE_WAKE3_STS 8
  18. #define GPE0A_PCIE_GPE_STS 9
  19. #define GPE0A_BATLOW_STS 10
  20. #define GPE0A_CSE_PME_STS 11
  21. #define GPE0A_XDCI_PME_STS 12
  22. #define GPE0A_XHCI_PME_STS 13
  23. #define GPE0A_AVS_PME_STS 14
  24. #define GPE0A_GPIO_TIER1_SCI_STS 15
  25. #define GPE0A_SMB_WAK_STS 16
  26. #define GPE0A_SATA_PME_STS 17
  27. #define GPE0A_CNVI_PME_STS 18
  28. /* Group DW0 is reserved in Apollolake */
  29. /* GPE_63_32 */
  30. #define GPE0_DW1_00 32
  31. #define GPE0_DW1_01 33
  32. #define GPE0_DW1_02 34
  33. #define GPE0_DW1_03 36
  34. #define GPE0_DW1_04 36
  35. #define GPE0_DW1_05 37
  36. #define GPE0_DW1_06 38
  37. #define GPE0_DW1_07 39
  38. #define GPE0_DW1_08 40
  39. #define GPE0_DW1_09 41
  40. #define GPE0_DW1_10 42
  41. #define GPE0_DW1_11 43
  42. #define GPE0_DW1_12 44
  43. #define GPE0_DW1_13 45
  44. #define GPE0_DW1_14 46
  45. #define GPE0_DW1_15 47
  46. #define GPE0_DW1_16 48
  47. #define GPE0_DW1_17 49
  48. #define GPE0_DW1_18 50
  49. #define GPE0_DW1_19 51
  50. #define GPE0_DW1_20 52
  51. #define GPE0_DW1_21 53
  52. #define GPE0_DW1_22 54
  53. #define GPE0_DW1_23 55
  54. #define GPE0_DW1_24 56
  55. #define GPE0_DW1_25 57
  56. #define GPE0_DW1_26 58
  57. #define GPE0_DW1_27 59
  58. #define GPE0_DW1_28 60
  59. #define GPE0_DW1_29 61
  60. #define GPE0_DW1_30 62
  61. #define GPE0_DW1_31 63
  62. /* GPE_95_64 */
  63. #define GPE0_DW2_00 64
  64. #define GPE0_DW2_01 65
  65. #define GPE0_DW2_02 66
  66. #define GPE0_DW2_03 67
  67. #define GPE0_DW2_04 68
  68. #define GPE0_DW2_05 69
  69. #define GPE0_DW2_06 70
  70. #define GPE0_DW2_07 71
  71. #define GPE0_DW2_08 72
  72. #define GPE0_DW2_09 73
  73. #define GPE0_DW2_10 74
  74. #define GPE0_DW2_11 75
  75. #define GPE0_DW2_12 76
  76. #define GPE0_DW2_13 77
  77. #define GPE0_DW2_14 78
  78. #define GPE0_DW2_15 79
  79. #define GPE0_DW2_16 80
  80. #define GPE0_DW2_17 81
  81. #define GPE0_DW2_18 82
  82. #define GPE0_DW2_19 83
  83. #define GPE0_DW2_20 84
  84. #define GPE0_DW2_21 85
  85. #define GPE0_DW2_22 86
  86. #define GPE0_DW2_23 87
  87. #define GPE0_DW2_24 88
  88. #define GPE0_DW2_25 89
  89. #define GPE0_DW2_26 90
  90. #define GPE0_DW2_27 91
  91. #define GPE0_DW2_28 92
  92. #define GPE0_DW2_29 93
  93. #define GPE0_DW2_30 94
  94. #define GPE0_DW2_31 95
  95. /* GPE_127_96 */
  96. #define GPE0_DW3_00 96
  97. #define GPE0_DW3_01 97
  98. #define GPE0_DW3_02 98
  99. #define GPE0_DW3_03 99
  100. #define GPE0_DW3_04 100
  101. #define GPE0_DW3_05 101
  102. #define GPE0_DW3_06 102
  103. #define GPE0_DW3_07 103
  104. #define GPE0_DW3_08 104
  105. #define GPE0_DW3_09 105
  106. #define GPE0_DW3_10 106
  107. #define GPE0_DW3_11 107
  108. #define GPE0_DW3_12 108
  109. #define GPE0_DW3_13 109
  110. #define GPE0_DW3_14 110
  111. #define GPE0_DW3_15 111
  112. #define GPE0_DW3_16 112
  113. #define GPE0_DW3_17 113
  114. #define GPE0_DW3_18 114
  115. #define GPE0_DW3_19 115
  116. #define GPE0_DW3_20 116
  117. #define GPE0_DW3_21 117
  118. #define GPE0_DW3_22 118
  119. #define GPE0_DW3_23 119
  120. #define GPE0_DW3_24 120
  121. #define GPE0_DW3_25 121
  122. #define GPE0_DW3_26 122
  123. #define GPE0_DW3_27 123
  124. #define GPE0_DW3_28 124
  125. #define GPE0_DW3_29 125
  126. #define GPE0_DW3_30 126
  127. #define GPE0_DW3_31 127
  128. #define GPE_MAX GPE0_DW3_31
  129. #endif