clock-ipq4019.c 1.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Clock drivers for Qualcomm IPQ40xx
  4. *
  5. * Copyright (c) 2019 Sartura Ltd.
  6. *
  7. * Author: Robert Marko <robert.marko@sartura.hr>
  8. *
  9. */
  10. #include <common.h>
  11. #include <clk-uclass.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. struct msm_clk_priv {
  15. phys_addr_t base;
  16. };
  17. ulong msm_set_rate(struct clk *clk, ulong rate)
  18. {
  19. switch (clk->id) {
  20. case 26: /*UART1*/
  21. /* This clock is already initialized by SBL1 */
  22. return 0;
  23. break;
  24. default:
  25. return 0;
  26. }
  27. }
  28. static int msm_clk_probe(struct udevice *dev)
  29. {
  30. struct msm_clk_priv *priv = dev_get_priv(dev);
  31. priv->base = devfdt_get_addr(dev);
  32. if (priv->base == FDT_ADDR_T_NONE)
  33. return -EINVAL;
  34. return 0;
  35. }
  36. static ulong msm_clk_set_rate(struct clk *clk, ulong rate)
  37. {
  38. return msm_set_rate(clk, rate);
  39. }
  40. static struct clk_ops msm_clk_ops = {
  41. .set_rate = msm_clk_set_rate,
  42. };
  43. static const struct udevice_id msm_clk_ids[] = {
  44. { .compatible = "qcom,gcc-ipq4019" },
  45. { }
  46. };
  47. U_BOOT_DRIVER(clk_msm) = {
  48. .name = "clk_msm",
  49. .id = UCLASS_CLK,
  50. .of_match = msm_clk_ids,
  51. .ops = &msm_clk_ops,
  52. .priv_auto_alloc_size = sizeof(struct msm_clk_priv),
  53. .probe = msm_clk_probe,
  54. };