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- // SPDX-License-Identifier: GPL-2.0+
- /*
- * Copyright (C) 2015-2019 Variscite Ltd.
- * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
- */
- #include <asm/arch/clock.h>
- #include <asm/arch/crm_regs.h>
- #include <asm/arch/mx6-pins.h>
- #include <asm/arch/sys_proto.h>
- #include <asm/mach-imx/iomux-v3.h>
- #include <asm/mach-imx/mxc_i2c.h>
- #include <fsl_esdhc_imx.h>
- #include <linux/bitops.h>
- #include <miiphy.h>
- #include <netdev.h>
- #include <usb.h>
- #include <usb/ehci-ci.h>
- DECLARE_GLOBAL_DATA_PTR;
- int dram_init(void)
- {
- gd->ram_size = imx_ddr_size();
- return 0;
- }
- #ifdef CONFIG_NAND_MXS
- #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
- #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
- PAD_CTL_SRE_FAST)
- #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
- static iomux_v3_cfg_t const nand_pads[] = {
- MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
- };
- static void setup_gpmi_nand(void)
- {
- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
- /* config gpmi nand iomux */
- imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
- clrbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
- /*
- * config gpmi and bch clock to 100 MHz
- * bch/gpmi select PLL2 PFD2 400M
- * 100M = 400M / 4
- */
- clrbits_le32(&mxc_ccm->cscmr1,
- MXC_CCM_CSCMR1_BCH_CLK_SEL |
- MXC_CCM_CSCMR1_GPMI_CLK_SEL);
- clrsetbits_le32(&mxc_ccm->cscdr1,
- MXC_CCM_CSCDR1_BCH_PODF_MASK |
- MXC_CCM_CSCDR1_GPMI_PODF_MASK,
- (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
- (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
- /* enable gpmi and bch clock gating */
- setbits_le32(&mxc_ccm->CCGR4,
- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
- /* enable apbh clock gating */
- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
- }
- #endif
- #ifdef CONFIG_FEC_MXC
- #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
- #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
- PAD_CTL_SRE_FAST)
- #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
- PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \
- PAD_CTL_ODE)
- /*
- * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
- * be used for ENET1 or ENET2, cannot be used for both.
- */
- static iomux_v3_cfg_t const fec1_pads[] = {
- MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
- MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
- MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- };
- static iomux_v3_cfg_t const fec2_pads[] = {
- MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
- MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
- MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
- };
- static void setup_iomux_fec(int fec_id)
- {
- if (fec_id == 0)
- imx_iomux_v3_setup_multiple_pads(fec1_pads,
- ARRAY_SIZE(fec1_pads));
- else
- imx_iomux_v3_setup_multiple_pads(fec2_pads,
- ARRAY_SIZE(fec2_pads));
- }
- int board_eth_init(bd_t *bis)
- {
- int ret = 0;
- ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
- CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
- #if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
- /* USB Ethernet Gadget */
- usb_eth_initialize(bis);
- #endif
- return ret;
- }
- static int setup_fec(int fec_id)
- {
- struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
- int ret;
- if (fec_id == 0) {
- /*
- * Use 50M anatop loopback REF_CLK1 for ENET1,
- * clear gpr1[13], set gpr1[17].
- */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
- IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
- } else {
- /*
- * Use 50M anatop loopback REF_CLK2 for ENET2,
- * clear gpr1[14], set gpr1[18].
- */
- clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
- IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
- }
- ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
- if (ret)
- return ret;
- enable_enet_clk(1);
- return 0;
- }
- int board_phy_config(struct phy_device *phydev)
- {
- /*
- * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
- * 50 MHz RMII clock mode.
- */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
- if (phydev->drv->config)
- phydev->drv->config(phydev);
- return 0;
- }
- #endif /* CONFIG_FEC_MXC */
- int board_early_init_f(void)
- {
- setup_iomux_fec(CONFIG_FEC_ENET_DEV);
- return 0;
- }
- int board_init(void)
- {
- /* Address of boot parameters */
- gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- #ifdef CONFIG_FEC_MXC
- setup_fec(CONFIG_FEC_ENET_DEV);
- #endif
- #ifdef CONFIG_NAND_MXS
- setup_gpmi_nand();
- #endif
- return 0;
- }
- int checkboard(void)
- {
- puts("Board: Variscite DART-6UL Evaluation Kit\n");
- return 0;
- }
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