dart_6ul.c 7.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2019 Variscite Ltd.
  4. * Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
  5. */
  6. #include <asm/arch/clock.h>
  7. #include <asm/arch/crm_regs.h>
  8. #include <asm/arch/mx6-pins.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/mach-imx/iomux-v3.h>
  11. #include <asm/mach-imx/mxc_i2c.h>
  12. #include <fsl_esdhc_imx.h>
  13. #include <linux/bitops.h>
  14. #include <miiphy.h>
  15. #include <netdev.h>
  16. #include <usb.h>
  17. #include <usb/ehci-ci.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. int dram_init(void)
  20. {
  21. gd->ram_size = imx_ddr_size();
  22. return 0;
  23. }
  24. #ifdef CONFIG_NAND_MXS
  25. #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  26. #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  27. PAD_CTL_SRE_FAST)
  28. #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  29. static iomux_v3_cfg_t const nand_pads[] = {
  30. MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  31. MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  32. MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  33. MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  34. MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  35. MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  36. MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  37. MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  38. MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  39. MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  40. MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  41. MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  42. MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  43. MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  44. MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  45. MX6_PAD_NAND_DQS__RAWNAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  46. };
  47. static void setup_gpmi_nand(void)
  48. {
  49. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  50. /* config gpmi nand iomux */
  51. imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  52. clrbits_le32(&mxc_ccm->CCGR4,
  53. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  54. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  55. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  56. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  57. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  58. /*
  59. * config gpmi and bch clock to 100 MHz
  60. * bch/gpmi select PLL2 PFD2 400M
  61. * 100M = 400M / 4
  62. */
  63. clrbits_le32(&mxc_ccm->cscmr1,
  64. MXC_CCM_CSCMR1_BCH_CLK_SEL |
  65. MXC_CCM_CSCMR1_GPMI_CLK_SEL);
  66. clrsetbits_le32(&mxc_ccm->cscdr1,
  67. MXC_CCM_CSCDR1_BCH_PODF_MASK |
  68. MXC_CCM_CSCDR1_GPMI_PODF_MASK,
  69. (3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) |
  70. (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET));
  71. /* enable gpmi and bch clock gating */
  72. setbits_le32(&mxc_ccm->CCGR4,
  73. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  74. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  75. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  76. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  77. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
  78. /* enable apbh clock gating */
  79. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  80. }
  81. #endif
  82. #ifdef CONFIG_FEC_MXC
  83. #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  84. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  85. PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | \
  86. PAD_CTL_SRE_FAST)
  87. #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  88. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | \
  89. PAD_CTL_ODE)
  90. /*
  91. * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
  92. * be used for ENET1 or ENET2, cannot be used for both.
  93. */
  94. static iomux_v3_cfg_t const fec1_pads[] = {
  95. MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  96. MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97. MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98. MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99. MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  100. MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  101. MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  102. MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  103. MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  104. MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  105. };
  106. static iomux_v3_cfg_t const fec2_pads[] = {
  107. MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  108. MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  109. MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  110. MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  111. MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  112. MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  113. MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  114. MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  115. MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  116. MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  117. };
  118. static void setup_iomux_fec(int fec_id)
  119. {
  120. if (fec_id == 0)
  121. imx_iomux_v3_setup_multiple_pads(fec1_pads,
  122. ARRAY_SIZE(fec1_pads));
  123. else
  124. imx_iomux_v3_setup_multiple_pads(fec2_pads,
  125. ARRAY_SIZE(fec2_pads));
  126. }
  127. int board_eth_init(bd_t *bis)
  128. {
  129. int ret = 0;
  130. ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
  131. CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  132. #if defined(CONFIG_CI_UDC) && defined(CONFIG_USB_ETHER)
  133. /* USB Ethernet Gadget */
  134. usb_eth_initialize(bis);
  135. #endif
  136. return ret;
  137. }
  138. static int setup_fec(int fec_id)
  139. {
  140. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  141. int ret;
  142. if (fec_id == 0) {
  143. /*
  144. * Use 50M anatop loopback REF_CLK1 for ENET1,
  145. * clear gpr1[13], set gpr1[17].
  146. */
  147. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  148. IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  149. } else {
  150. /*
  151. * Use 50M anatop loopback REF_CLK2 for ENET2,
  152. * clear gpr1[14], set gpr1[18].
  153. */
  154. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
  155. IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
  156. }
  157. ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
  158. if (ret)
  159. return ret;
  160. enable_enet_clk(1);
  161. return 0;
  162. }
  163. int board_phy_config(struct phy_device *phydev)
  164. {
  165. /*
  166. * Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
  167. * 50 MHz RMII clock mode.
  168. */
  169. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  170. if (phydev->drv->config)
  171. phydev->drv->config(phydev);
  172. return 0;
  173. }
  174. #endif /* CONFIG_FEC_MXC */
  175. int board_early_init_f(void)
  176. {
  177. setup_iomux_fec(CONFIG_FEC_ENET_DEV);
  178. return 0;
  179. }
  180. int board_init(void)
  181. {
  182. /* Address of boot parameters */
  183. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  184. #ifdef CONFIG_FEC_MXC
  185. setup_fec(CONFIG_FEC_ENET_DEV);
  186. #endif
  187. #ifdef CONFIG_NAND_MXS
  188. setup_gpmi_nand();
  189. #endif
  190. return 0;
  191. }
  192. int checkboard(void)
  193. {
  194. puts("Board: Variscite DART-6UL Evaluation Kit\n");
  195. return 0;
  196. }