tqma6_wru4.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  5. *
  6. * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
  7. * Author: Markus Niebel <markus.niebel@tq-group.com>
  8. *
  9. * Copyright (C) 2015 Stefan Roese <sr@denx.de>
  10. */
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <asm/arch/imx-regs.h>
  15. #include <asm/arch/iomux.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <linux/errno.h>
  18. #include <asm/gpio.h>
  19. #include <asm/mach-imx/boot_mode.h>
  20. #include <asm/mach-imx/mxc_i2c.h>
  21. #include <common.h>
  22. #include <fsl_esdhc_imx.h>
  23. #include <linux/libfdt.h>
  24. #include <malloc.h>
  25. #include <i2c.h>
  26. #include <micrel.h>
  27. #include <miiphy.h>
  28. #include <mmc.h>
  29. #include <netdev.h>
  30. #include "tqma6_bb.h"
  31. /* UART */
  32. #define UART4_PAD_CTRL ( \
  33. PAD_CTL_HYS | \
  34. PAD_CTL_PUS_100K_UP | \
  35. PAD_CTL_PUE | \
  36. PAD_CTL_PKE | \
  37. PAD_CTL_SPEED_MED | \
  38. PAD_CTL_DSE_40ohm | \
  39. PAD_CTL_SRE_SLOW \
  40. )
  41. static iomux_v3_cfg_t const uart4_pads[] = {
  42. NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL),
  43. NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL),
  44. NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL),
  45. NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL),
  46. };
  47. static void setup_iomuxc_uart4(void)
  48. {
  49. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  50. }
  51. /* MMC */
  52. #define USDHC2_PAD_CTRL ( \
  53. PAD_CTL_HYS | \
  54. PAD_CTL_PUS_47K_UP | \
  55. PAD_CTL_SPEED_LOW | \
  56. PAD_CTL_DSE_80ohm | \
  57. PAD_CTL_SRE_FAST \
  58. )
  59. #define USDHC2_CLK_PAD_CTRL ( \
  60. PAD_CTL_HYS | \
  61. PAD_CTL_PUS_47K_UP | \
  62. PAD_CTL_SPEED_LOW | \
  63. PAD_CTL_DSE_40ohm | \
  64. PAD_CTL_SRE_FAST \
  65. )
  66. static iomux_v3_cfg_t const usdhc2_pads[] = {
  67. NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL),
  68. NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL),
  69. NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL),
  70. NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL),
  71. NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL),
  72. NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL),
  73. NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */
  74. NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */
  75. };
  76. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  77. #define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
  78. static struct fsl_esdhc_cfg usdhc2_cfg = {
  79. .esdhc_base = USDHC2_BASE_ADDR,
  80. .max_bus_width = 4,
  81. };
  82. int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
  83. {
  84. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  85. int ret = 0;
  86. if (cfg->esdhc_base == USDHC2_BASE_ADDR)
  87. ret = !gpio_get_value(USDHC2_CD_GPIO);
  88. return ret;
  89. }
  90. int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
  91. {
  92. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  93. int ret = 0;
  94. if (cfg->esdhc_base == USDHC2_BASE_ADDR)
  95. ret = gpio_get_value(USDHC2_WP_GPIO);
  96. return ret;
  97. }
  98. int tqma6_bb_board_mmc_init(bd_t *bis)
  99. {
  100. int ret;
  101. imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  102. ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd");
  103. if (!ret)
  104. gpio_direction_input(USDHC2_CD_GPIO);
  105. ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp");
  106. if (!ret)
  107. gpio_direction_input(USDHC2_WP_GPIO);
  108. usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  109. if(fsl_esdhc_initialize(bis, &usdhc2_cfg))
  110. puts("WARNING: failed to initialize SD\n");
  111. return 0;
  112. }
  113. /* Ethernet */
  114. #define ENET_PAD_CTRL ( \
  115. PAD_CTL_HYS | \
  116. PAD_CTL_PUS_100K_UP | \
  117. PAD_CTL_PUE | \
  118. PAD_CTL_PKE | \
  119. PAD_CTL_SPEED_MED | \
  120. PAD_CTL_DSE_40ohm | \
  121. PAD_CTL_SRE_SLOW \
  122. )
  123. static iomux_v3_cfg_t const enet_pads[] = {
  124. NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
  125. NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
  126. NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL),
  127. NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL),
  128. NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL),
  129. NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL),
  130. NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL),
  131. NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL),
  132. NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL),
  133. NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL),
  134. NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL),
  135. /* ENET1 reset */
  136. NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL),
  137. /* ENET1 interrupt */
  138. NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL),
  139. };
  140. #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8)
  141. static void setup_iomuxc_enet(void)
  142. {
  143. int ret;
  144. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  145. /* Reset LAN8720 PHY */
  146. ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
  147. if (!ret)
  148. gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
  149. udelay(25000);
  150. gpio_set_value(ENET_PHY_RESET_GPIO, 1);
  151. }
  152. int board_eth_init(bd_t *bis)
  153. {
  154. return cpu_eth_init(bis);
  155. }
  156. /* GPIO */
  157. #define GPIO_PAD_CTRL ( \
  158. PAD_CTL_HYS | \
  159. PAD_CTL_PUS_100K_UP | \
  160. PAD_CTL_PUE | \
  161. PAD_CTL_SPEED_MED | \
  162. PAD_CTL_DSE_40ohm | \
  163. PAD_CTL_SRE_SLOW \
  164. )
  165. #define GPIO_OD_PAD_CTRL ( \
  166. PAD_CTL_HYS | \
  167. PAD_CTL_PUS_100K_UP | \
  168. PAD_CTL_PUE | \
  169. PAD_CTL_ODE | \
  170. PAD_CTL_SPEED_MED | \
  171. PAD_CTL_DSE_40ohm | \
  172. PAD_CTL_SRE_SLOW \
  173. )
  174. static iomux_v3_cfg_t const gpio_pads[] = {
  175. /* USB_H_PWR */
  176. NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL),
  177. /* USB_OTG_PWR */
  178. NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL),
  179. /* PCIE_RST */
  180. NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL),
  181. /* UART1_PWRON */
  182. NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL),
  183. /* UART2_PWRON */
  184. NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL),
  185. /* UART3_PWRON */
  186. NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL),
  187. };
  188. #define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0)
  189. #define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22)
  190. #define GPIO_PCIE_RST IMX_GPIO_NR(6, 7)
  191. #define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8)
  192. #define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10)
  193. #define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12)
  194. static void gpio_init(void)
  195. {
  196. int ret;
  197. imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
  198. ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr");
  199. if (!ret)
  200. gpio_direction_output(GPIO_USB_H_PWR, 1);
  201. ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr");
  202. if (!ret)
  203. gpio_direction_output(GPIO_USB_OTG_PWR, 1);
  204. ret = gpio_request(GPIO_PCIE_RST, "pcie-reset");
  205. if (!ret)
  206. gpio_direction_output(GPIO_PCIE_RST, 1);
  207. ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr");
  208. if (!ret)
  209. gpio_direction_output(GPIO_UART1_PWRON, 0);
  210. ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr");
  211. if (!ret)
  212. gpio_direction_output(GPIO_UART2_PWRON, 0);
  213. ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr");
  214. if (!ret)
  215. gpio_direction_output(GPIO_UART3_PWRON, 0);
  216. }
  217. void tqma6_iomuxc_spi(void)
  218. {
  219. /* No SPI on this baseboard */
  220. }
  221. int tqma6_bb_board_early_init_f(void)
  222. {
  223. setup_iomuxc_uart4();
  224. return 0;
  225. }
  226. int tqma6_bb_board_init(void)
  227. {
  228. setup_iomuxc_enet();
  229. gpio_init();
  230. /* Turn the UART-couplers on one-after-another */
  231. gpio_set_value(GPIO_UART1_PWRON, 1);
  232. mdelay(10);
  233. gpio_set_value(GPIO_UART2_PWRON, 1);
  234. mdelay(10);
  235. gpio_set_value(GPIO_UART3_PWRON, 1);
  236. return 0;
  237. }
  238. int tqma6_bb_board_late_init(void)
  239. {
  240. return 0;
  241. }
  242. const char *tqma6_bb_get_boardname(void)
  243. {
  244. return "WRU-IV";
  245. }
  246. static const struct boot_mode board_boot_modes[] = {
  247. /* 4 bit bus width */
  248. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  249. /* 8 bit bus width */
  250. {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  251. { NULL, 0 },
  252. };
  253. int misc_init_r(void)
  254. {
  255. add_board_boot_modes(board_boot_modes);
  256. return 0;
  257. }
  258. #define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0)
  259. #define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22)
  260. int board_ehci_hcd_init(int port)
  261. {
  262. int ret;
  263. ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr");
  264. if (!ret)
  265. gpio_direction_output(WRU4_USB_H1_PWR, 1);
  266. ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr");
  267. if (!ret)
  268. gpio_direction_output(WRU4_USB_OTG_PWR, 1);
  269. return 0;
  270. }
  271. int board_ehci_power(int port, int on)
  272. {
  273. if (port)
  274. gpio_set_value(WRU4_USB_OTG_PWR, on);
  275. else
  276. gpio_set_value(WRU4_USB_H1_PWR, on);
  277. return 0;
  278. }
  279. /*
  280. * Device Tree Support
  281. */
  282. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  283. void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
  284. {
  285. /* TBD */
  286. }
  287. #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */