tqma6.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  5. *
  6. * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
  7. * Author: Markus Niebel <markus.niebel@tq-group.com>
  8. */
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/imx-regs.h>
  12. #include <asm/arch/iomux.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <linux/errno.h>
  15. #include <asm/gpio.h>
  16. #include <asm/io.h>
  17. #include <asm/mach-imx/mxc_i2c.h>
  18. #include <asm/mach-imx/spi.h>
  19. #include <common.h>
  20. #include <fsl_esdhc_imx.h>
  21. #include <linux/libfdt.h>
  22. #include <i2c.h>
  23. #include <mmc.h>
  24. #include <power/pfuze100_pmic.h>
  25. #include <power/pmic.h>
  26. #include <spi_flash.h>
  27. #include "tqma6_bb.h"
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  30. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  31. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  32. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33. #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  34. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  35. #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  36. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  37. #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  38. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  39. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  40. PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
  41. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  42. int dram_init(void)
  43. {
  44. gd->ram_size = imx_ddr_size();
  45. return 0;
  46. }
  47. static const uint16_t tqma6_emmc_dsr = 0x0100;
  48. /* eMMC on USDHCI3 always present */
  49. static iomux_v3_cfg_t const tqma6_usdhc3_pads[] = {
  50. NEW_PAD_CTRL(MX6_PAD_SD3_CLK__SD3_CLK, USDHC_PAD_CTRL),
  51. NEW_PAD_CTRL(MX6_PAD_SD3_CMD__SD3_CMD, USDHC_PAD_CTRL),
  52. NEW_PAD_CTRL(MX6_PAD_SD3_DAT0__SD3_DATA0, USDHC_PAD_CTRL),
  53. NEW_PAD_CTRL(MX6_PAD_SD3_DAT1__SD3_DATA1, USDHC_PAD_CTRL),
  54. NEW_PAD_CTRL(MX6_PAD_SD3_DAT2__SD3_DATA2, USDHC_PAD_CTRL),
  55. NEW_PAD_CTRL(MX6_PAD_SD3_DAT3__SD3_DATA3, USDHC_PAD_CTRL),
  56. NEW_PAD_CTRL(MX6_PAD_SD3_DAT4__SD3_DATA4, USDHC_PAD_CTRL),
  57. NEW_PAD_CTRL(MX6_PAD_SD3_DAT5__SD3_DATA5, USDHC_PAD_CTRL),
  58. NEW_PAD_CTRL(MX6_PAD_SD3_DAT6__SD3_DATA6, USDHC_PAD_CTRL),
  59. NEW_PAD_CTRL(MX6_PAD_SD3_DAT7__SD3_DATA7, USDHC_PAD_CTRL),
  60. /* eMMC reset */
  61. NEW_PAD_CTRL(MX6_PAD_SD3_RST__SD3_RESET, GPIO_OUT_PAD_CTRL),
  62. };
  63. /*
  64. * According to board_mmc_init() the following map is done:
  65. * (U-Boot device node) (Physical Port)
  66. * mmc0 eMMC (SD3) on TQMa6
  67. * mmc1 .. n optional slots used on baseboard
  68. */
  69. struct fsl_esdhc_cfg tqma6_usdhc_cfg = {
  70. .esdhc_base = USDHC3_BASE_ADDR,
  71. .max_bus_width = 8,
  72. };
  73. int board_mmc_getcd(struct mmc *mmc)
  74. {
  75. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  76. int ret = 0;
  77. if (cfg->esdhc_base == USDHC3_BASE_ADDR)
  78. /* eMMC/uSDHC3 is always present */
  79. ret = 1;
  80. else
  81. ret = tqma6_bb_board_mmc_getcd(mmc);
  82. return ret;
  83. }
  84. int board_mmc_getwp(struct mmc *mmc)
  85. {
  86. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  87. int ret = 0;
  88. if (cfg->esdhc_base == USDHC3_BASE_ADDR)
  89. /* eMMC/uSDHC3 is always present */
  90. ret = 0;
  91. else
  92. ret = tqma6_bb_board_mmc_getwp(mmc);
  93. return ret;
  94. }
  95. int board_mmc_init(bd_t *bis)
  96. {
  97. imx_iomux_v3_setup_multiple_pads(tqma6_usdhc3_pads,
  98. ARRAY_SIZE(tqma6_usdhc3_pads));
  99. tqma6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  100. if (fsl_esdhc_initialize(bis, &tqma6_usdhc_cfg)) {
  101. puts("Warning: failed to initialize eMMC dev\n");
  102. } else {
  103. struct mmc *mmc = find_mmc_device(0);
  104. if (mmc)
  105. mmc_set_dsr(mmc, tqma6_emmc_dsr);
  106. }
  107. tqma6_bb_board_mmc_init(bis);
  108. return 0;
  109. }
  110. static iomux_v3_cfg_t const tqma6_ecspi1_pads[] = {
  111. /* SS1 */
  112. NEW_PAD_CTRL(MX6_PAD_EIM_D19__GPIO3_IO19, SPI_PAD_CTRL),
  113. NEW_PAD_CTRL(MX6_PAD_EIM_D16__ECSPI1_SCLK, SPI_PAD_CTRL),
  114. NEW_PAD_CTRL(MX6_PAD_EIM_D17__ECSPI1_MISO, SPI_PAD_CTRL),
  115. NEW_PAD_CTRL(MX6_PAD_EIM_D18__ECSPI1_MOSI, SPI_PAD_CTRL),
  116. };
  117. #define TQMA6_SF_CS_GPIO IMX_GPIO_NR(3, 19)
  118. static unsigned const tqma6_ecspi1_cs[] = {
  119. TQMA6_SF_CS_GPIO,
  120. };
  121. __weak void tqma6_iomuxc_spi(void)
  122. {
  123. unsigned i;
  124. for (i = 0; i < ARRAY_SIZE(tqma6_ecspi1_cs); ++i)
  125. gpio_direction_output(tqma6_ecspi1_cs[i], 1);
  126. imx_iomux_v3_setup_multiple_pads(tqma6_ecspi1_pads,
  127. ARRAY_SIZE(tqma6_ecspi1_pads));
  128. }
  129. #if defined(CONFIG_SF_DEFAULT_BUS) && defined(CONFIG_SF_DEFAULT_CS)
  130. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  131. {
  132. return ((bus == CONFIG_SF_DEFAULT_BUS) &&
  133. (cs == CONFIG_SF_DEFAULT_CS)) ? TQMA6_SF_CS_GPIO : -1;
  134. }
  135. #endif
  136. static struct i2c_pads_info tqma6_i2c3_pads = {
  137. /* I2C3: on board LM75, M24C64, */
  138. .scl = {
  139. .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__I2C3_SCL,
  140. I2C_PAD_CTRL),
  141. .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_5__GPIO1_IO05,
  142. I2C_PAD_CTRL),
  143. .gp = IMX_GPIO_NR(1, 5)
  144. },
  145. .sda = {
  146. .i2c_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__I2C3_SDA,
  147. I2C_PAD_CTRL),
  148. .gpio_mode = NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06,
  149. I2C_PAD_CTRL),
  150. .gp = IMX_GPIO_NR(1, 6)
  151. }
  152. };
  153. static void tqma6_setup_i2c(void)
  154. {
  155. int ret;
  156. /*
  157. * use logical index for bus, e.g. I2C1 -> 0
  158. * warn on error
  159. */
  160. ret = setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &tqma6_i2c3_pads);
  161. if (ret)
  162. printf("setup I2C3 failed: %d\n", ret);
  163. }
  164. int board_early_init_f(void)
  165. {
  166. return tqma6_bb_board_early_init_f();
  167. }
  168. int board_init(void)
  169. {
  170. /* address of boot parameters */
  171. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  172. tqma6_iomuxc_spi();
  173. tqma6_setup_i2c();
  174. tqma6_bb_board_init();
  175. return 0;
  176. }
  177. static const char *tqma6_get_boardname(void)
  178. {
  179. u32 cpurev = get_cpu_rev();
  180. switch ((cpurev & 0xFF000) >> 12) {
  181. case MXC_CPU_MX6SOLO:
  182. return "TQMa6S";
  183. break;
  184. case MXC_CPU_MX6DL:
  185. return "TQMa6DL";
  186. break;
  187. case MXC_CPU_MX6D:
  188. return "TQMa6D";
  189. break;
  190. case MXC_CPU_MX6Q:
  191. return "TQMa6Q";
  192. break;
  193. default:
  194. return "??";
  195. };
  196. }
  197. /* setup board specific PMIC */
  198. int power_init_board(void)
  199. {
  200. struct pmic *p;
  201. u32 reg, rev;
  202. power_pfuze100_init(TQMA6_PFUZE100_I2C_BUS);
  203. p = pmic_get("PFUZE100");
  204. if (p && !pmic_probe(p)) {
  205. pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  206. pmic_reg_read(p, PFUZE100_REVID, &rev);
  207. printf("PMIC: PFUZE100 ID=0x%02x REV=0x%02x\n", reg, rev);
  208. }
  209. return 0;
  210. }
  211. int board_late_init(void)
  212. {
  213. env_set("board_name", tqma6_get_boardname());
  214. tqma6_bb_board_late_init();
  215. return 0;
  216. }
  217. int checkboard(void)
  218. {
  219. printf("Board: %s on a %s\n", tqma6_get_boardname(),
  220. tqma6_bb_get_boardname());
  221. return 0;
  222. }
  223. /*
  224. * Device Tree Support
  225. */
  226. #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
  227. #define MODELSTRLEN 32u
  228. int ft_board_setup(void *blob, bd_t *bd)
  229. {
  230. char modelstr[MODELSTRLEN];
  231. snprintf(modelstr, MODELSTRLEN, "TQ %s on %s", tqma6_get_boardname(),
  232. tqma6_bb_get_boardname());
  233. do_fixup_by_path_string(blob, "/", "model", modelstr);
  234. fdt_fixup_memory(blob, (u64)PHYS_SDRAM, (u64)gd->ram_size);
  235. /* bring in eMMC dsr settings */
  236. do_fixup_by_path_u32(blob,
  237. "/soc/aips-bus@02100000/usdhc@02198000",
  238. "dsr", tqma6_emmc_dsr, 2);
  239. tqma6_bb_ft_board_setup(blob, bd);
  240. return 0;
  241. }
  242. #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */