spl.c 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Technexion Ltd.
  4. *
  5. * Author: Richard Hu <richard.hu@technexion.com>
  6. */
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/mx7-pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/arch-mx7/mx7-ddr.h>
  13. #include <asm/mach-imx/iomux-v3.h>
  14. #include <asm/gpio.h>
  15. #include <fsl_esdhc_imx.h>
  16. #include <spl.h>
  17. #if defined(CONFIG_SPL_BUILD)
  18. #ifdef CONFIG_SPL_OS_BOOT
  19. int spl_start_uboot(void)
  20. {
  21. return 0;
  22. }
  23. #endif
  24. static struct ddrc ddrc_regs_val = {
  25. .mstr = 0x01040001,
  26. .rfshtmg = 0x00400046,
  27. .init1 = 0x00690000,
  28. .init0 = 0x00020083,
  29. .init3 = 0x09300004,
  30. .init4 = 0x04080000,
  31. .init5 = 0x00100004,
  32. .rankctl = 0x0000033F,
  33. .dramtmg0 = 0x09081109,
  34. .dramtmg1 = 0x0007020d,
  35. .dramtmg2 = 0x03040407,
  36. .dramtmg3 = 0x00002006,
  37. .dramtmg4 = 0x04020205,
  38. .dramtmg5 = 0x03030202,
  39. .dramtmg8 = 0x00000803,
  40. .zqctl0 = 0x00800020,
  41. .dfitmg0 = 0x02098204,
  42. .dfitmg1 = 0x00030303,
  43. .dfiupd0 = 0x80400003,
  44. .dfiupd1 = 0x00100020,
  45. .dfiupd2 = 0x80100004,
  46. .addrmap4 = 0x00000F0F,
  47. .odtcfg = 0x06000604,
  48. .odtmap = 0x00000001,
  49. .rfshtmg = 0x00400046,
  50. .dramtmg0 = 0x09081109,
  51. .addrmap0 = 0x0000001f,
  52. .addrmap1 = 0x00080808,
  53. .addrmap4 = 0x00000f0f,
  54. .addrmap5 = 0x07070707,
  55. .addrmap6 = 0x0f0f0707,
  56. };
  57. static struct ddrc_mp ddrc_mp_val = {
  58. .pctrl_0 = 0x00000001,
  59. };
  60. static struct ddr_phy ddr_phy_regs_val = {
  61. .phy_con0 = 0x17420f40,
  62. .phy_con1 = 0x10210100,
  63. .phy_con4 = 0x00060807,
  64. .mdll_con0 = 0x1010007e,
  65. .drvds_con0 = 0x00000d6e,
  66. .cmd_sdll_con0 = 0x00000010,
  67. .offset_lp_con0 = 0x0000000f,
  68. .offset_rd_con0 = 0x08080808,
  69. .offset_wr_con0 = 0x08080808,
  70. };
  71. static struct mx7_calibration calib_param = {
  72. .num_val = 5,
  73. .values = {
  74. 0x0E407304,
  75. 0x0E447304,
  76. 0x0E447306,
  77. 0x0E447304,
  78. 0x0E447304,
  79. },
  80. };
  81. static void gpr_init(void)
  82. {
  83. struct iomuxc_gpr_base_regs *gpr_regs =
  84. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  85. writel(0x4F400005, &gpr_regs->gpr[1]);
  86. }
  87. static bool is_1g(void)
  88. {
  89. gpio_direction_input(IMX_GPIO_NR(1, 12));
  90. return !gpio_get_value(IMX_GPIO_NR(1, 12));
  91. }
  92. static void ddr_init(void)
  93. {
  94. if (is_1g())
  95. ddrc_regs_val.addrmap6 = 0x0f070707;
  96. mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val,
  97. &calib_param);
  98. }
  99. void board_init_f(ulong dummy)
  100. {
  101. arch_cpu_init();
  102. gpr_init();
  103. board_early_init_f();
  104. timer_init();
  105. preloader_console_init();
  106. ddr_init();
  107. memset(__bss_start, 0, __bss_end - __bss_start);
  108. board_init_r(NULL, 0);
  109. }
  110. void reset_cpu(ulong addr)
  111. {
  112. }
  113. #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  114. PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  115. static iomux_v3_cfg_t const usdhc3_pads[] = {
  116. MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118. MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  119. MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  120. MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  121. MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  122. MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123. MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124. MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125. MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126. MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  127. };
  128. static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  129. {USDHC3_BASE_ADDR},
  130. };
  131. int board_mmc_getcd(struct mmc *mmc)
  132. {
  133. /* Assume uSDHC3 emmc is always present */
  134. return 1;
  135. }
  136. int board_mmc_init(bd_t *bis)
  137. {
  138. imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  139. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  140. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  141. }
  142. #endif