spl.c 4.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. #include <asm/arch/clock.h>
  3. #include <asm/arch/iomux.h>
  4. #include <asm/arch/imx-regs.h>
  5. #include <asm/arch/crm_regs.h>
  6. #include <asm/arch/mx6ul_pins.h>
  7. #include <asm/arch/mx6-pins.h>
  8. #include <asm/arch/sys_proto.h>
  9. #include <asm/gpio.h>
  10. #include <asm/mach-imx/iomux-v3.h>
  11. #include <asm/mach-imx/boot_mode.h>
  12. #include <fsl_esdhc_imx.h>
  13. #include <linux/libfdt.h>
  14. #include <spl.h>
  15. #if defined(CONFIG_SPL_BUILD)
  16. #ifdef CONFIG_SPL_OS_BOOT
  17. int spl_start_uboot(void)
  18. {
  19. return 0;
  20. }
  21. #endif
  22. #include <asm/arch/mx6-ddr.h>
  23. static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  24. .grp_addds = 0x00000030,
  25. .grp_ddrmode_ctl = 0x00020000,
  26. .grp_b0ds = 0x00000030,
  27. .grp_ctlds = 0x00000030,
  28. .grp_b1ds = 0x00000030,
  29. .grp_ddrpke = 0x00000000,
  30. .grp_ddrmode = 0x00020000,
  31. .grp_ddr_type = 0x00080000,
  32. };
  33. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  34. .dram_dqm0 = 0x00000030,
  35. .dram_dqm1 = 0x00000030,
  36. .dram_ras = 0x00000030,
  37. .dram_cas = 0x00000030,
  38. .dram_odt0 = 0x00000030,
  39. .dram_odt1 = 0x00000030,
  40. .dram_sdba2 = 0x00000000,
  41. .dram_sdclk_0 = 0x00000030,
  42. .dram_sdqs0 = 0x00000030,
  43. .dram_sdqs1 = 0x00000030,
  44. .dram_reset = 0x00000030,
  45. };
  46. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  47. .p0_mpwldectrl0 = 0x00000000,
  48. .p0_mpdgctrl0 = 0x01380134,
  49. .p0_mprddlctl = 0x40404244,
  50. .p0_mpwrdlctl = 0x40405050,
  51. };
  52. static struct mx6_ddr_sysinfo ddr_sysinfo = {
  53. .dsize = 0,
  54. .cs1_mirror = 0,
  55. .cs_density = 32,
  56. .ncs = 1,
  57. .bi_on = 1,
  58. .rtt_nom = 1,
  59. .rtt_wr = 0,
  60. .ralat = 5,
  61. .walat = 0,
  62. .mif3_mode = 3,
  63. .rst_to_cke = 0x23,
  64. .sde_to_rst = 0x10,
  65. .refsel = 1,
  66. .refr = 3,
  67. };
  68. static struct mx6_ddr3_cfg mem_ddr = {
  69. .mem_speed = 1333,
  70. .density = 2,
  71. .width = 16,
  72. .banks = 8,
  73. .coladdr = 10,
  74. .pagesz = 2,
  75. .trcd = 1350,
  76. .trcmin = 4950,
  77. .trasmin = 3600,
  78. };
  79. static void ccgr_init(void)
  80. {
  81. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  82. writel(0xFFFFFFFF, &ccm->CCGR0);
  83. writel(0xFFFFFFFF, &ccm->CCGR1);
  84. writel(0xFFFFFFFF, &ccm->CCGR2);
  85. writel(0xFFFFFFFF, &ccm->CCGR3);
  86. writel(0xFFFFFFFF, &ccm->CCGR4);
  87. writel(0xFFFFFFFF, &ccm->CCGR5);
  88. writel(0xFFFFFFFF, &ccm->CCGR6);
  89. }
  90. static void imx6ul_spl_dram_cfg_size(u32 ram_size)
  91. {
  92. if (ram_size == SZ_256M)
  93. mem_ddr.rowaddr = 14;
  94. else
  95. mem_ddr.rowaddr = 15;
  96. mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  97. mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  98. }
  99. static void imx6ul_spl_dram_cfg(void)
  100. {
  101. ulong ram_size_test, ram_size = 0;
  102. for (ram_size = SZ_512M; ram_size >= SZ_256M; ram_size >>= 1) {
  103. imx6ul_spl_dram_cfg_size(ram_size);
  104. ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
  105. if (ram_size_test == ram_size)
  106. break;
  107. }
  108. if (ram_size < SZ_256M) {
  109. puts("ERROR: DRAM size detection failed\n");
  110. hang();
  111. }
  112. }
  113. void board_init_f(ulong dummy)
  114. {
  115. ccgr_init();
  116. arch_cpu_init();
  117. board_early_init_f();
  118. timer_init();
  119. preloader_console_init();
  120. imx6ul_spl_dram_cfg();
  121. memset(__bss_start, 0, __bss_end - __bss_start);
  122. board_init_r(NULL, 0);
  123. }
  124. void reset_cpu(ulong addr)
  125. {
  126. }
  127. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  128. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  129. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  130. static iomux_v3_cfg_t const usdhc1_pads[] = {
  131. MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132. MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  133. MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  134. MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135. MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  136. MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  137. MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  138. MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  139. MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  140. MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  141. };
  142. static struct fsl_esdhc_cfg usdhc_cfg[1] = {
  143. {USDHC1_BASE_ADDR},
  144. };
  145. int board_mmc_getcd(struct mmc *mmc)
  146. {
  147. return 1;
  148. }
  149. int board_mmc_init(bd_t *bis)
  150. {
  151. imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  152. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  153. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  154. }
  155. #endif