tbs2910.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Soeren Moch <smoch@web.de>
  4. */
  5. #include <asm/arch/clock.h>
  6. #include <asm/arch/imx-regs.h>
  7. #include <asm/arch/iomux.h>
  8. #include <asm/arch/mx6-pins.h>
  9. #include <linux/errno.h>
  10. #include <asm/gpio.h>
  11. #include <asm/mach-imx/iomux-v3.h>
  12. #include <asm/mach-imx/boot_mode.h>
  13. #include <asm/mach-imx/video.h>
  14. #include <mmc.h>
  15. #include <fsl_esdhc_imx.h>
  16. #include <miiphy.h>
  17. #include <netdev.h>
  18. #include <asm/arch/mxc_hdmi.h>
  19. #include <asm/arch/crm_regs.h>
  20. #include <asm/io.h>
  21. #include <asm/arch/sys_proto.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \
  24. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  25. PAD_CTL_SRE_SLOW)
  26. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  27. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  28. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  29. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  30. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  31. static iomux_v3_cfg_t const uart1_pads[] = {
  32. MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  33. MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  34. };
  35. static iomux_v3_cfg_t const uart2_pads[] = {
  36. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  37. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  38. };
  39. static iomux_v3_cfg_t const enet_pads[] = {
  40. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  41. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  42. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  43. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  44. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  45. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  46. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  47. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  48. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  49. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  50. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  51. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  52. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  53. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  54. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  55. /* AR8035 PHY Reset */
  56. MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  57. };
  58. static iomux_v3_cfg_t const pcie_pads[] = {
  59. /* W_DISABLE# */
  60. MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
  61. /* PERST# */
  62. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  63. };
  64. int dram_init(void)
  65. {
  66. gd->ram_size = 2048ul * 1024 * 1024;
  67. return 0;
  68. }
  69. static void setup_iomux_enet(void)
  70. {
  71. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  72. /* Reset AR8035 PHY */
  73. gpio_request(IMX_GPIO_NR(1, 25), "ETH_PHY_RESET");
  74. gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
  75. udelay(500);
  76. gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  77. }
  78. static void setup_pcie(void)
  79. {
  80. imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  81. }
  82. static void setup_iomux_uart(void)
  83. {
  84. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  85. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  86. }
  87. #ifdef CONFIG_FSL_ESDHC_IMX
  88. /* set environment device to boot device when booting from SD */
  89. int board_mmc_get_env_dev(int devno)
  90. {
  91. return devno - 1;
  92. }
  93. int board_mmc_get_env_part(int devno)
  94. {
  95. return (devno == 3) ? 1 : 0; /* part 0 for SD2 / SD3, part 1 for eMMC */
  96. }
  97. #endif /* CONFIG_FSL_ESDHC_IMX */
  98. #ifdef CONFIG_VIDEO_IPUV3
  99. static void do_enable_hdmi(struct display_info_t const *dev)
  100. {
  101. imx_enable_hdmi_phy();
  102. }
  103. struct display_info_t const displays[] = {{
  104. .bus = -1,
  105. .addr = 0,
  106. .pixfmt = IPU_PIX_FMT_RGB24,
  107. .detect = detect_hdmi,
  108. .enable = do_enable_hdmi,
  109. .mode = {
  110. .name = "HDMI",
  111. /* 1024x768@60Hz (VESA)*/
  112. .refresh = 60,
  113. .xres = 1024,
  114. .yres = 768,
  115. .pixclock = 15384,
  116. .left_margin = 160,
  117. .right_margin = 24,
  118. .upper_margin = 29,
  119. .lower_margin = 3,
  120. .hsync_len = 136,
  121. .vsync_len = 6,
  122. .sync = FB_SYNC_EXT,
  123. .vmode = FB_VMODE_NONINTERLACED
  124. } } };
  125. size_t display_count = ARRAY_SIZE(displays);
  126. static void setup_display(void)
  127. {
  128. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  129. int reg;
  130. s32 timeout = 100000;
  131. enable_ipu_clock();
  132. imx_setup_hdmi();
  133. /* set video pll to 455MHz (24MHz * (37+11/12) / 2) */
  134. reg = readl(&ccm->analog_pll_video);
  135. reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
  136. writel(reg, &ccm->analog_pll_video);
  137. reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
  138. reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(37);
  139. reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
  140. reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(1);
  141. writel(reg, &ccm->analog_pll_video);
  142. writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
  143. writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
  144. reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
  145. writel(reg, &ccm->analog_pll_video);
  146. while (timeout--)
  147. if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
  148. break;
  149. if (timeout < 0)
  150. printf("Warning: video pll lock timeout!\n");
  151. reg = readl(&ccm->analog_pll_video);
  152. reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
  153. reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
  154. writel(reg, &ccm->analog_pll_video);
  155. /* gate ipu1_di0_clk */
  156. reg = readl(&ccm->CCGR3);
  157. reg &= ~MXC_CCM_CCGR3_LDB_DI0_MASK;
  158. writel(reg, &ccm->CCGR3);
  159. /* select video_pll clock / 7 for ipu1_di0_clk -> 65MHz pixclock */
  160. reg = readl(&ccm->chsccdr);
  161. reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK |
  162. MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK |
  163. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
  164. reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET) |
  165. (6 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) |
  166. (0 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  167. writel(reg, &ccm->chsccdr);
  168. /* enable ipu1_di0_clk */
  169. reg = readl(&ccm->CCGR3);
  170. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  171. writel(reg, &ccm->CCGR3);
  172. }
  173. #endif /* CONFIG_VIDEO_IPUV3 */
  174. static int ar8035_phy_fixup(struct phy_device *phydev)
  175. {
  176. unsigned short val;
  177. /* To enable AR8035 ouput a 125MHz clk from CLK_25M */
  178. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  179. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  180. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  181. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  182. val &= 0xffe3;
  183. val |= 0x18;
  184. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  185. /* introduce tx clock delay */
  186. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  187. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  188. val |= 0x0100;
  189. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  190. return 0;
  191. }
  192. int board_phy_config(struct phy_device *phydev)
  193. {
  194. ar8035_phy_fixup(phydev);
  195. if (phydev->drv->config)
  196. phydev->drv->config(phydev);
  197. return 0;
  198. }
  199. int board_eth_init(bd_t *bis)
  200. {
  201. setup_iomux_enet();
  202. setup_pcie();
  203. return cpu_eth_init(bis);
  204. }
  205. int board_early_init_f(void)
  206. {
  207. setup_iomux_uart();
  208. return 0;
  209. }
  210. #ifdef CONFIG_CMD_BMODE
  211. static const struct boot_mode board_boot_modes[] = {
  212. /* 4 bit bus width */
  213. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  214. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  215. /* 8 bit bus width */
  216. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  217. {NULL, 0},
  218. };
  219. #endif
  220. int board_init(void)
  221. {
  222. /* address of boot parameters */
  223. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  224. #ifdef CONFIG_VIDEO_IPUV3
  225. setup_display();
  226. #endif
  227. #ifdef CONFIG_CMD_BMODE
  228. add_board_boot_modes(board_boot_modes);
  229. #endif
  230. return 0;
  231. }