sksimx6.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Stefano Babic <sbabic@denx.de>
  4. */
  5. #include <asm/arch/clock.h>
  6. #include <asm/arch/imx-regs.h>
  7. #include <asm/arch/iomux.h>
  8. #include <asm/arch/mx6-pins.h>
  9. #include <linux/errno.h>
  10. #include <asm/gpio.h>
  11. #include <asm/mach-imx/iomux-v3.h>
  12. #include <asm/mach-imx/video.h>
  13. #include <mmc.h>
  14. #include <fsl_esdhc_imx.h>
  15. #include <asm/arch/crm_regs.h>
  16. #include <asm/io.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <spl.h>
  19. #include <netdev.h>
  20. #include <miiphy.h>
  21. #include <micrel.h>
  22. #include <common.h>
  23. #include <malloc.h>
  24. #include <fuse.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  27. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  28. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  29. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  30. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  31. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  32. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  33. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  34. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  35. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  36. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  37. static iomux_v3_cfg_t const uart1_pads[] = {
  38. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  39. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  40. };
  41. static iomux_v3_cfg_t const gpios_pads[] = {
  42. IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  43. };
  44. static iomux_v3_cfg_t const usdhc2_pads[] = {
  45. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  46. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  47. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  48. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  49. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  50. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  51. IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),/* CD */
  52. };
  53. static iomux_v3_cfg_t const enet_pads[] = {
  54. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  55. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  56. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  57. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  58. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  59. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  61. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  67. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  69. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  71. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72. IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  73. };
  74. iomux_v3_cfg_t const enet_pads1[] = {
  75. /* pin 35 - 1 (PHY_AD2) on reset */
  76. IOMUX_PADS(PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  77. /* pin 32 - 1 - (MODE0) all */
  78. IOMUX_PADS(PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  79. /* pin 31 - 1 - (MODE1) all */
  80. IOMUX_PADS(PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  81. /* pin 28 - 1 - (MODE2) all */
  82. IOMUX_PADS(PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  83. /* pin 27 - 1 - (MODE3) all */
  84. IOMUX_PADS(PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  86. IOMUX_PADS(PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87. /* pin 42 PHY nRST */
  88. IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89. };
  90. static int mx6_rgmii_rework(struct phy_device *phydev)
  91. {
  92. /* min rx data delay */
  93. ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
  94. 0x0);
  95. /* min tx data delay */
  96. ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
  97. 0x0);
  98. /* max rx/tx clock delay, min rx/tx control */
  99. ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
  100. 0xf0f0);
  101. return 0;
  102. }
  103. int board_phy_config(struct phy_device *phydev)
  104. {
  105. mx6_rgmii_rework(phydev);
  106. if (phydev->drv->config)
  107. return phydev->drv->config(phydev);
  108. return 0;
  109. }
  110. #define ENET_NRST IMX_GPIO_NR(1, 25)
  111. void setup_iomux_enet(void)
  112. {
  113. SETUP_IOMUX_PADS(enet_pads);
  114. }
  115. int board_eth_init(bd_t *bis)
  116. {
  117. uint32_t base = IMX_FEC_BASE;
  118. struct mii_dev *bus = NULL;
  119. struct phy_device *phydev = NULL;
  120. int ret;
  121. setup_iomux_enet();
  122. bus = fec_get_miibus(base, -1);
  123. if (!bus)
  124. return -EINVAL;
  125. /* scan phy */
  126. phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR),
  127. PHY_INTERFACE_MODE_RGMII);
  128. if (!phydev) {
  129. ret = -EINVAL;
  130. goto free_bus;
  131. }
  132. ret = fec_probe(bis, -1, base, bus, phydev);
  133. if (ret)
  134. goto free_phydev;
  135. return 0;
  136. free_phydev:
  137. free(phydev);
  138. free_bus:
  139. free(bus);
  140. return ret;
  141. }
  142. int board_early_init_f(void)
  143. {
  144. SETUP_IOMUX_PADS(uart1_pads);
  145. return 0;
  146. }
  147. int board_init(void)
  148. {
  149. /* Address of boot parameters */
  150. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  151. /* Take in reset the ATMega processor */
  152. SETUP_IOMUX_PADS(gpios_pads);
  153. gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
  154. return 0;
  155. }
  156. int dram_init(void)
  157. {
  158. gd->ram_size = imx_ddr_size();
  159. return 0;
  160. }
  161. struct fsl_esdhc_cfg usdhc_cfg[1] = {
  162. {USDHC2_BASE_ADDR, 0},
  163. };
  164. #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 0)
  165. int board_mmc_getcd(struct mmc *mmc)
  166. {
  167. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  168. int ret = 0;
  169. if (cfg->esdhc_base == USDHC2_BASE_ADDR)
  170. ret = 1;
  171. return ret;
  172. }
  173. int board_mmc_init(bd_t *bis)
  174. {
  175. int ret;
  176. SETUP_IOMUX_PADS(usdhc2_pads);
  177. gpio_direction_input(USDHC2_CD_GPIO);
  178. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  179. usdhc_cfg[0].max_bus_width = 4;
  180. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  181. if (ret) {
  182. printf("Warning: failed to initialize mmc dev \n");
  183. return ret;
  184. }
  185. return 0;
  186. }
  187. #if defined(CONFIG_SPL_BUILD)
  188. #include <asm/arch/mx6-ddr.h>
  189. /*
  190. * Driving strength:
  191. * 0x30 == 40 Ohm
  192. * 0x28 == 48 Ohm
  193. */
  194. #define IMX6SDL_DRIVE_STRENGTH 0x230
  195. /* configure MX6SOLO/DUALLITE mmdc DDR io registers */
  196. struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
  197. .dram_sdclk_0 = IMX6SDL_DRIVE_STRENGTH,
  198. .dram_sdclk_1 = IMX6SDL_DRIVE_STRENGTH,
  199. .dram_cas = IMX6SDL_DRIVE_STRENGTH,
  200. .dram_ras = IMX6SDL_DRIVE_STRENGTH,
  201. .dram_reset = IMX6SDL_DRIVE_STRENGTH,
  202. .dram_sdcke0 = IMX6SDL_DRIVE_STRENGTH,
  203. .dram_sdcke1 = IMX6SDL_DRIVE_STRENGTH,
  204. .dram_sdba2 = 0x00000000,
  205. .dram_sdodt0 = IMX6SDL_DRIVE_STRENGTH,
  206. .dram_sdodt1 = IMX6SDL_DRIVE_STRENGTH,
  207. .dram_sdqs0 = IMX6SDL_DRIVE_STRENGTH,
  208. .dram_sdqs1 = IMX6SDL_DRIVE_STRENGTH,
  209. .dram_sdqs2 = IMX6SDL_DRIVE_STRENGTH,
  210. .dram_sdqs3 = IMX6SDL_DRIVE_STRENGTH,
  211. .dram_sdqs4 = IMX6SDL_DRIVE_STRENGTH,
  212. .dram_sdqs5 = IMX6SDL_DRIVE_STRENGTH,
  213. .dram_sdqs6 = IMX6SDL_DRIVE_STRENGTH,
  214. .dram_sdqs7 = IMX6SDL_DRIVE_STRENGTH,
  215. .dram_dqm0 = IMX6SDL_DRIVE_STRENGTH,
  216. .dram_dqm1 = IMX6SDL_DRIVE_STRENGTH,
  217. .dram_dqm2 = IMX6SDL_DRIVE_STRENGTH,
  218. .dram_dqm3 = IMX6SDL_DRIVE_STRENGTH,
  219. .dram_dqm4 = IMX6SDL_DRIVE_STRENGTH,
  220. .dram_dqm5 = IMX6SDL_DRIVE_STRENGTH,
  221. .dram_dqm6 = IMX6SDL_DRIVE_STRENGTH,
  222. .dram_dqm7 = IMX6SDL_DRIVE_STRENGTH,
  223. };
  224. /* configure MX6SOLO/DUALLITE mmdc GRP io registers */
  225. struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
  226. .grp_ddr_type = 0x000c0000,
  227. .grp_ddrmode_ctl = 0x00020000,
  228. .grp_ddrpke = 0x00000000,
  229. .grp_addds = IMX6SDL_DRIVE_STRENGTH,
  230. .grp_ctlds = IMX6SDL_DRIVE_STRENGTH,
  231. .grp_ddrmode = 0x00020000,
  232. .grp_b0ds = IMX6SDL_DRIVE_STRENGTH,
  233. .grp_b1ds = IMX6SDL_DRIVE_STRENGTH,
  234. .grp_b2ds = IMX6SDL_DRIVE_STRENGTH,
  235. .grp_b3ds = IMX6SDL_DRIVE_STRENGTH,
  236. .grp_b4ds = IMX6SDL_DRIVE_STRENGTH,
  237. .grp_b5ds = IMX6SDL_DRIVE_STRENGTH,
  238. .grp_b6ds = IMX6SDL_DRIVE_STRENGTH,
  239. .grp_b7ds = IMX6SDL_DRIVE_STRENGTH,
  240. };
  241. /* MT41K128M16JT-125 */
  242. static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
  243. /* quad = 1066, duallite = 800 */
  244. .mem_speed = 1066,
  245. .density = 2,
  246. .width = 16,
  247. .banks = 8,
  248. .rowaddr = 14,
  249. .coladdr = 10,
  250. .pagesz = 2,
  251. .trcd = 1375,
  252. .trcmin = 4875,
  253. .trasmin = 3500,
  254. .SRT = 0,
  255. };
  256. static struct mx6_mmdc_calibration mx6dl_1g_mmdc_calib = {
  257. .p0_mpwldectrl0 = 0x0043004E,
  258. .p0_mpwldectrl1 = 0x003D003F,
  259. .p1_mpwldectrl0 = 0x00230021,
  260. .p1_mpwldectrl1 = 0x0028003E,
  261. .p0_mpdgctrl0 = 0x42580250,
  262. .p0_mpdgctrl1 = 0x0238023C,
  263. .p1_mpdgctrl0 = 0x422C0238,
  264. .p1_mpdgctrl1 = 0x02180228,
  265. .p0_mprddlctl = 0x44464A46,
  266. .p1_mprddlctl = 0x44464A42,
  267. .p0_mpwrdlctl = 0x36343236,
  268. .p1_mpwrdlctl = 0x36343230,
  269. };
  270. /* DDR 64bit 1GB */
  271. static struct mx6_ddr_sysinfo mem_qdl = {
  272. .dsize = 2,
  273. .cs1_mirror = 0,
  274. /* config for full 4GB range so that get_mem_size() works */
  275. .cs_density = 32,
  276. .ncs = 1,
  277. .bi_on = 1,
  278. .rtt_nom = 1,
  279. .rtt_wr = 1,
  280. .ralat = 5,
  281. .walat = 0,
  282. .mif3_mode = 3,
  283. .rst_to_cke = 0x23,
  284. .sde_to_rst = 0x10,
  285. .refsel = 1, /* Refresh cycles at 32KHz */
  286. .refr = 7, /* 8 refresh commands per refresh cycle */
  287. };
  288. static void ccgr_init(void)
  289. {
  290. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  291. /* set the default clock gate to save power */
  292. writel(0x00C03F3F, &ccm->CCGR0);
  293. writel(0x0030FC03, &ccm->CCGR1);
  294. writel(0x0FFFC000, &ccm->CCGR2);
  295. writel(0x3FF00000, &ccm->CCGR3);
  296. writel(0x00FFF300, &ccm->CCGR4);
  297. writel(0xFFFFFFFF, &ccm->CCGR5);
  298. writel(0x000003FF, &ccm->CCGR6);
  299. }
  300. static void spl_dram_init(void)
  301. {
  302. if (is_cpu_type(MXC_CPU_MX6DL)) {
  303. mt41k128m16jt_125.mem_speed = 800;
  304. mem_qdl.rtt_nom = 1;
  305. mem_qdl.rtt_wr = 1;
  306. mx6sdl_dram_iocfg(64, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs);
  307. mx6_dram_cfg(&mem_qdl, &mx6dl_1g_mmdc_calib, &mt41k128m16jt_125);
  308. } else {
  309. printf("Wrong CPU for this board\n");
  310. return;
  311. }
  312. udelay(100);
  313. #ifdef CONFIG_MX6_DDRCAL
  314. /* Perform DDR DRAM calibration */
  315. mmdc_do_write_level_calibration(&mem_qdl);
  316. mmdc_do_dqs_calibration(&mem_qdl);
  317. #endif
  318. }
  319. static void check_bootcfg(void)
  320. {
  321. u32 val5, val6;
  322. fuse_sense(0, 5, &val5);
  323. fuse_sense(0, 6, &val6);
  324. /* Check if boot from MMC */
  325. if (val6 & 0x10) {
  326. puts("BT_FUSE_SEL already fused, will do nothing\n");
  327. return;
  328. }
  329. fuse_prog(0, 5, 0x00000840);
  330. /* BT_FUSE_SEL */
  331. fuse_prog(0, 6, 0x00000010);
  332. do_reset(NULL, 0, 0, NULL);
  333. }
  334. void board_init_f(ulong dummy)
  335. {
  336. ccgr_init();
  337. /* setup AIPS and disable watchdog */
  338. arch_cpu_init();
  339. gpr_init();
  340. /* iomux */
  341. board_early_init_f();
  342. /* setup GP timer */
  343. timer_init();
  344. /* UART clocks enabled and gd valid - init serial console */
  345. preloader_console_init();
  346. /* DDR initialization */
  347. spl_dram_init();
  348. /* Set fuses for new boards and reboot if not set */
  349. check_bootcfg();
  350. /* Clear the BSS. */
  351. memset(__bss_start, 0, __bss_end - __bss_start);
  352. /* load/boot image from boot device */
  353. board_init_r(NULL, 0);
  354. }
  355. #endif