mx6.c 4.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2015 ECA Sinters
  5. *
  6. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  7. * Modified by: Boris Brezillon <boris.brezillon@free-electrons.com>
  8. */
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/iomux.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <linux/errno.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <mmc.h>
  18. #include <fsl_esdhc_imx.h>
  19. #include <miiphy.h>
  20. #include <netdev.h>
  21. #include <asm/arch/mxc_hdmi.h>
  22. #include <asm/arch/crm_regs.h>
  23. #include <linux/fb.h>
  24. #include <ipu_pixfmt.h>
  25. #include <asm/io.h>
  26. #include <asm/arch/sys_proto.h>
  27. #include <micrel.h>
  28. #include <asm/mach-imx/mxc_i2c.h>
  29. #include <i2c.h>
  30. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  31. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  32. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33. static iomux_v3_cfg_t const uart2_pads[] = {
  34. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  35. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  36. };
  37. void seco_mx6_setup_uart_iomux(void)
  38. {
  39. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  40. }
  41. #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  42. PAD_CTL_SPEED_MED | \
  43. PAD_CTL_DSE_40ohm | \
  44. PAD_CTL_HYS)
  45. static iomux_v3_cfg_t const enet_pads[] = {
  46. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  47. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  48. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  49. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  50. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  51. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  52. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  53. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  54. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  55. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  56. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  57. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  58. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61. };
  62. void seco_mx6_setup_enet_iomux(void)
  63. {
  64. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  65. }
  66. int seco_mx6_rgmii_rework(struct phy_device *phydev)
  67. {
  68. /* control data pad skew - devaddr = 0x02, register = 0x04 */
  69. ksz9031_phy_extended_write(phydev, 0x02,
  70. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  71. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  72. /* rx data pad skew - devaddr = 0x02, register = 0x05 */
  73. ksz9031_phy_extended_write(phydev, 0x02,
  74. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  75. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  76. /* tx data pad skew - devaddr = 0x02, register = 0x05 */
  77. ksz9031_phy_extended_write(phydev, 0x02,
  78. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  79. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
  80. /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
  81. ksz9031_phy_extended_write(phydev, 0x02,
  82. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  83. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
  84. return 0;
  85. }
  86. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  87. PAD_CTL_SPEED_LOW | \
  88. PAD_CTL_DSE_80ohm | \
  89. PAD_CTL_SRE_FAST | \
  90. PAD_CTL_HYS)
  91. static iomux_v3_cfg_t const usdhc3_pads[] = {
  92. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98. };
  99. static iomux_v3_cfg_t const usdhc4_pads[] = {
  100. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  101. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  102. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  103. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  104. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  105. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  106. };
  107. void seco_mx6_setup_usdhc_iomux(int id)
  108. {
  109. switch (id) {
  110. case 3:
  111. imx_iomux_v3_setup_multiple_pads(usdhc3_pads,
  112. ARRAY_SIZE(usdhc3_pads));
  113. break;
  114. case 4:
  115. imx_iomux_v3_setup_multiple_pads(usdhc4_pads,
  116. ARRAY_SIZE(usdhc4_pads));
  117. break;
  118. default:
  119. printf("Warning: invalid usdhc id (%d)\n", id);
  120. break;
  121. }
  122. }