spl.c 5.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Collabora Ltd.
  4. *
  5. * Based on board/ccv/xpress/spl.c:
  6. * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
  7. */
  8. #include <common.h>
  9. #include <spl.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/mx6-ddr.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <asm/arch/crm_regs.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <fsl_esdhc_imx.h>
  17. /* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
  18. static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  19. .grp_addds = 0x00000030,
  20. .grp_ddrmode_ctl = 0x00020000,
  21. .grp_b0ds = 0x00000030,
  22. .grp_ctlds = 0x00000030,
  23. .grp_b1ds = 0x00000030,
  24. .grp_ddrpke = 0x00000000,
  25. .grp_ddrmode = 0x00020000,
  26. .grp_ddr_type = 0x000c0000,
  27. };
  28. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  29. .dram_dqm0 = 0x00000030,
  30. .dram_dqm1 = 0x00000030,
  31. .dram_ras = 0x00000030,
  32. .dram_cas = 0x00000030,
  33. .dram_odt0 = 0x00000030,
  34. .dram_odt1 = 0x00000030,
  35. .dram_sdba2 = 0x00000000,
  36. .dram_sdclk_0 = 0x00000030,
  37. .dram_sdqs0 = 0x00000030,
  38. .dram_sdqs1 = 0x00000030,
  39. .dram_reset = 0x00000030,
  40. };
  41. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  42. .p0_mpwldectrl0 = 0x00000000,
  43. .p0_mpdgctrl0 = 0x41480148,
  44. .p0_mprddlctl = 0x40403E42,
  45. .p0_mpwrdlctl = 0x40405852,
  46. };
  47. struct mx6_ddr_sysinfo ddr_sysinfo = {
  48. .dsize = 0, /* Bus size = 16bit */
  49. .cs_density = 18,
  50. .ncs = 1,
  51. .cs1_mirror = 0,
  52. .rtt_wr = 1,
  53. .rtt_nom = 1,
  54. .walat = 1, /* Write additional latency */
  55. .ralat = 5, /* Read additional latency */
  56. .mif3_mode = 3, /* Command prediction working mode */
  57. .bi_on = 1, /* Bank interleaving enabled */
  58. .pd_fast_exit = 1,
  59. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  60. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  61. .ddr_type = DDR_TYPE_DDR3,
  62. .refsel = 1, /* Refresh cycles at 32KHz */
  63. .refr = 7, /* 8 refresh commands per refresh cycle */
  64. };
  65. static struct mx6_ddr3_cfg mem_ddr = {
  66. .mem_speed = 933,
  67. .density = 4,
  68. .width = 16,
  69. .banks = 8,
  70. .rowaddr = 14,
  71. .coladdr = 10,
  72. .pagesz = 1,
  73. .trcd = 1391,
  74. .trcmin = 4791,
  75. .trasmin = 3400,
  76. };
  77. static void ccgr_init(void)
  78. {
  79. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  80. writel(0xFFFFFFFF, &ccm->CCGR0);
  81. writel(0xFFFFFFFF, &ccm->CCGR1);
  82. writel(0xFFFFFFFF, &ccm->CCGR2);
  83. writel(0xFFFFFFFF, &ccm->CCGR3);
  84. writel(0xFFFFFFFF, &ccm->CCGR4);
  85. writel(0xFFFFFFFF, &ccm->CCGR5);
  86. writel(0xFFFFFFFF, &ccm->CCGR6);
  87. }
  88. static void spl_dram_init(void)
  89. {
  90. mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  91. mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  92. }
  93. #ifdef CONFIG_FSL_ESDHC_IMX
  94. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  95. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  96. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
  97. PAD_CTL_HYS)
  98. static iomux_v3_cfg_t const usdhc1_pads[] = {
  99. MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  100. MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  101. MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  102. MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  103. MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  104. MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  105. MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  106. };
  107. #ifndef CONFIG_NAND_MXS
  108. static iomux_v3_cfg_t const usdhc2_pads[] = {
  109. MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110. MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111. MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112. MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  113. MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  114. MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  115. MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  116. MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118. MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  119. };
  120. #endif
  121. static struct fsl_esdhc_cfg usdhc_cfg[] = {
  122. {
  123. .esdhc_base = USDHC1_BASE_ADDR,
  124. .max_bus_width = 4,
  125. },
  126. #ifndef CONFIG_NAND_MXS
  127. {
  128. .esdhc_base = USDHC2_BASE_ADDR,
  129. .max_bus_width = 8,
  130. },
  131. #endif
  132. };
  133. int board_mmc_getcd(struct mmc *mmc)
  134. {
  135. return 1;
  136. }
  137. int board_mmc_init(bd_t *bis)
  138. {
  139. int i, ret;
  140. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  141. switch (i) {
  142. case 0:
  143. SETUP_IOMUX_PADS(usdhc1_pads);
  144. usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  145. break;
  146. #ifndef CONFIG_NAND_MXS
  147. case 1:
  148. SETUP_IOMUX_PADS(usdhc2_pads);
  149. usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  150. break;
  151. #endif
  152. default:
  153. printf("Warning - USDHC%d controller not supporting\n",
  154. i + 1);
  155. return 0;
  156. }
  157. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  158. if (ret) {
  159. printf("Warning: failed to initialize mmc dev %d\n", i);
  160. return ret;
  161. }
  162. }
  163. return 0;
  164. }
  165. void board_boot_order(u32 *spl_boot_list)
  166. {
  167. u32 bmode = imx6_src_get_boot_mode();
  168. u8 boot_dev = BOOT_DEVICE_MMC1;
  169. switch ((bmode & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT) {
  170. case IMX6_BMODE_SD:
  171. case IMX6_BMODE_ESD:
  172. boot_dev = BOOT_DEVICE_MMC1;
  173. break;
  174. case IMX6_BMODE_MMC:
  175. case IMX6_BMODE_EMMC:
  176. boot_dev = BOOT_DEVICE_MMC2;
  177. break;
  178. default:
  179. /* Default - BOOT_DEVICE_MMC1 */
  180. printf("Wrong board boot order\n");
  181. break;
  182. }
  183. spl_boot_list[0] = boot_dev;
  184. }
  185. #endif /* CONFIG_FSL_ESDHC_IMX */
  186. void board_init_f(ulong dummy)
  187. {
  188. ccgr_init();
  189. /* Setup AIPS and disable watchdog */
  190. arch_cpu_init();
  191. /* Setup iomux and fec */
  192. board_early_init_f();
  193. /* Setup GP timer */
  194. timer_init();
  195. /* UART clocks enabled and gd valid - init serial console */
  196. preloader_console_init();
  197. /* DDR initialization */
  198. spl_dram_init();
  199. }