imx6logic.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Logic PD, Inc.
  4. *
  5. * Author: Adam Ford <aford173@gmail.com>
  6. *
  7. * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
  8. * and updates by Jagan Teki <jagan@amarulasolutions.com>
  9. */
  10. #include <common.h>
  11. #include <miiphy.h>
  12. #include <input.h>
  13. #include <mmc.h>
  14. #include <fsl_esdhc_imx.h>
  15. #include <asm/io.h>
  16. #include <asm/gpio.h>
  17. #include <linux/sizes.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/crm_regs.h>
  20. #include <asm/arch/iomux.h>
  21. #include <asm/arch/mxc_hdmi.h>
  22. #include <asm/arch/mx6-pins.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <asm/mach-imx/boot_mode.h>
  25. #include <asm/mach-imx/iomux-v3.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  28. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  29. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  30. #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  31. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  32. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  33. int dram_init(void)
  34. {
  35. gd->ram_size = imx_ddr_size();
  36. return 0;
  37. }
  38. static iomux_v3_cfg_t const uart1_pads[] = {
  39. MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  40. MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  41. };
  42. static iomux_v3_cfg_t const uart2_pads[] = {
  43. MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  44. MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  45. MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  46. MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  47. };
  48. static iomux_v3_cfg_t const uart3_pads[] = {
  49. MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  50. MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  51. MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  52. MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  53. };
  54. static void setup_iomux_uart(void)
  55. {
  56. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  57. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  58. imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  59. }
  60. static iomux_v3_cfg_t const nand_pads[] = {
  61. MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  62. MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  63. MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  64. MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  65. MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  66. MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  67. MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  68. MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  69. MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  70. MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  71. MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  72. MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  73. MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  74. MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  75. MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  76. };
  77. static void setup_nand_pins(void)
  78. {
  79. imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  80. }
  81. static int ar8031_phy_fixup(struct phy_device *phydev)
  82. {
  83. unsigned short val;
  84. /* To enable AR8031 output a 125MHz clk from CLK_25M */
  85. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  86. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  87. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  88. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  89. val &= 0xffe3;
  90. val |= 0x18;
  91. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  92. /* introduce tx clock delay */
  93. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  94. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  95. val |= 0x0100;
  96. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  97. return 0;
  98. }
  99. int board_phy_config(struct phy_device *phydev)
  100. {
  101. ar8031_phy_fixup(phydev);
  102. if (phydev->drv->config)
  103. phydev->drv->config(phydev);
  104. return 0;
  105. }
  106. /*
  107. * Do not overwrite the console
  108. * Use always serial for U-Boot console
  109. */
  110. int overwrite_console(void)
  111. {
  112. return 1;
  113. }
  114. int board_early_init_f(void)
  115. {
  116. setup_iomux_uart();
  117. setup_nand_pins();
  118. return 0;
  119. }
  120. int board_init(void)
  121. {
  122. /* address of boot parameters */
  123. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  124. return 0;
  125. }
  126. int board_late_init(void)
  127. {
  128. env_set("board_name", "imx6logic");
  129. if (is_mx6dq()) {
  130. env_set("board_rev", "MX6DQ");
  131. if (!env_get("fdt_file"))
  132. env_set("fdt_file", "imx6q-logicpd.dtb");
  133. }
  134. return 0;
  135. }
  136. #ifdef CONFIG_SPL_BUILD
  137. #include <asm/arch/mx6-ddr.h>
  138. #include <asm/arch/mx6q-ddr.h>
  139. #include <spl.h>
  140. #include <linux/libfdt.h>
  141. #ifdef CONFIG_SPL_OS_BOOT
  142. int spl_start_uboot(void)
  143. {
  144. /* break into full u-boot on 'c' */
  145. if (serial_tstc() && serial_getc() == 'c')
  146. return 1;
  147. return 0;
  148. }
  149. #endif
  150. /* SD interface */
  151. #define USDHC_PAD_CTRL \
  152. (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  153. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  154. static iomux_v3_cfg_t const usdhc1_pads[] = {
  155. MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  156. MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  157. MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  158. MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  159. MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  160. MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  161. };
  162. static iomux_v3_cfg_t const usdhc2_pads[] = {
  163. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  164. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  165. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  166. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  167. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  168. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  169. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  170. };
  171. #ifdef CONFIG_FSL_ESDHC_IMX
  172. struct fsl_esdhc_cfg usdhc_cfg[] = {
  173. {USDHC1_BASE_ADDR}, /* SOM */
  174. {USDHC2_BASE_ADDR} /* Baseboard */
  175. };
  176. int board_mmc_init(bd_t *bis)
  177. {
  178. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  179. unsigned int reg = readl(&psrc->sbmr1) >> 11;
  180. /*
  181. * Upon reading BOOT_CFG register the following map is done:
  182. * Bit 11 and 12 of BOOT_CFG register can determine the current
  183. * mmc port
  184. * 0x1 SD1-SOM
  185. * 0x2 SD2-Baseboard
  186. */
  187. reg &= 0x3; /* Only care about bottom 2 bits */
  188. switch (reg) {
  189. case 0:
  190. SETUP_IOMUX_PADS(usdhc1_pads);
  191. usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
  192. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  193. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  194. break;
  195. case 1:
  196. SETUP_IOMUX_PADS(usdhc2_pads);
  197. usdhc_cfg[1].esdhc_base = USDHC2_BASE_ADDR;
  198. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  199. gd->arch.sdhc_clk = usdhc_cfg[1].sdhc_clk;
  200. break;
  201. }
  202. return fsl_esdhc_initialize(bis, &usdhc_cfg[reg]);
  203. }
  204. int board_mmc_getcd(struct mmc *mmc)
  205. {
  206. return 1;
  207. }
  208. #endif
  209. static void ccgr_init(void)
  210. {
  211. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  212. writel(0x00C03F3F, &ccm->CCGR0);
  213. writel(0x0030FC03, &ccm->CCGR1);
  214. writel(0x0FFFC000, &ccm->CCGR2);
  215. writel(0x3FF00000, &ccm->CCGR3);
  216. writel(0xFFFFF300, &ccm->CCGR4);
  217. writel(0x0F0000F3, &ccm->CCGR5);
  218. writel(0x00000FFF, &ccm->CCGR6);
  219. }
  220. static int mx6q_dcd_table[] = {
  221. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  222. MX6_IOM_GRP_DDRPKE, 0x00000000,
  223. MX6_IOM_DRAM_SDCLK_0, 0x00000030,
  224. MX6_IOM_DRAM_SDCLK_1, 0x00000030,
  225. MX6_IOM_DRAM_CAS, 0x00000030,
  226. MX6_IOM_DRAM_RAS, 0x00000030,
  227. MX6_IOM_GRP_ADDDS, 0x00000030,
  228. MX6_IOM_DRAM_RESET, 0x00000030,
  229. MX6_IOM_DRAM_SDBA2, 0x00000000,
  230. MX6_IOM_DRAM_SDODT0, 0x00000030,
  231. MX6_IOM_DRAM_SDODT1, 0x00000030,
  232. MX6_IOM_GRP_CTLDS, 0x00000030,
  233. MX6_IOM_DDRMODE_CTL, 0x00020000,
  234. MX6_IOM_DRAM_SDQS0, 0x00000030,
  235. MX6_IOM_DRAM_SDQS1, 0x00000030,
  236. MX6_IOM_DRAM_SDQS2, 0x00000030,
  237. MX6_IOM_DRAM_SDQS3, 0x00000030,
  238. MX6_IOM_GRP_DDRMODE, 0x00020000,
  239. MX6_IOM_GRP_B0DS, 0x00000030,
  240. MX6_IOM_GRP_B1DS, 0x00000030,
  241. MX6_IOM_GRP_B2DS, 0x00000030,
  242. MX6_IOM_GRP_B3DS, 0x00000030,
  243. MX6_IOM_DRAM_DQM0, 0x00000030,
  244. MX6_IOM_DRAM_DQM1, 0x00000030,
  245. MX6_IOM_DRAM_DQM2, 0x00000030,
  246. MX6_IOM_DRAM_DQM3, 0x00000030,
  247. MX6_MMDC_P0_MDSCR, 0x00008000,
  248. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  249. MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
  250. MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
  251. MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
  252. MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
  253. MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
  254. MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
  255. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  256. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  257. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  258. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  259. MX6_MMDC_P0_MPMUR0, 0x00000800,
  260. MX6_MMDC_P0_MDPDC, 0x00020036,
  261. MX6_MMDC_P0_MDOTC, 0x09444040,
  262. MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
  263. MX6_MMDC_P0_MDCFG1, 0xFF328F64,
  264. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  265. MX6_MMDC_P0_MDMISC, 0x00011740,
  266. MX6_MMDC_P0_MDSCR, 0x00008000,
  267. MX6_MMDC_P0_MDRWD, 0x000026D2,
  268. MX6_MMDC_P0_MDOR, 0x00BE1023,
  269. MX6_MMDC_P0_MDASP, 0x00000047,
  270. MX6_MMDC_P0_MDCTL, 0x85190000,
  271. MX6_MMDC_P0_MDSCR, 0x00888032,
  272. MX6_MMDC_P0_MDSCR, 0x00008033,
  273. MX6_MMDC_P0_MDSCR, 0x00008031,
  274. MX6_MMDC_P0_MDSCR, 0x19408030,
  275. MX6_MMDC_P0_MDSCR, 0x04008040,
  276. MX6_MMDC_P0_MDREF, 0x00007800,
  277. MX6_MMDC_P0_MPODTCTRL, 0x00000007,
  278. MX6_MMDC_P0_MDPDC, 0x00025576,
  279. MX6_MMDC_P0_MAPSR, 0x00011006,
  280. MX6_MMDC_P0_MDSCR, 0x00000000,
  281. /* enable AXI cache for VDOA/VPU/IPU */
  282. MX6_IOMUXC_GPR4, 0xF00000CF,
  283. /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  284. MX6_IOMUXC_GPR6, 0x007F007F,
  285. MX6_IOMUXC_GPR7, 0x007F007F,
  286. };
  287. static void ddr_init(int *table, int size)
  288. {
  289. int i;
  290. for (i = 0; i < size / 2 ; i++)
  291. writel(table[2 * i + 1], table[2 * i]);
  292. }
  293. static void spl_dram_init(void)
  294. {
  295. if (is_mx6dq())
  296. ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
  297. }
  298. void board_init_f(ulong dummy)
  299. {
  300. /* DDR initialization */
  301. spl_dram_init();
  302. /* setup AIPS and disable watchdog */
  303. arch_cpu_init();
  304. ccgr_init();
  305. gpr_init();
  306. /* iomux and setup of uart and NAND pins */
  307. board_early_init_f();
  308. /* setup GP timer */
  309. timer_init();
  310. /* UART clocks enabled and gd valid - init serial console */
  311. preloader_console_init();
  312. /* Clear the BSS. */
  313. memset(__bss_start, 0, __bss_end - __bss_start);
  314. /* load/boot image from boot device */
  315. board_init_r(NULL, 0);
  316. }
  317. #endif