mccmon6.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016-2017
  4. * Lukasz Majewski, DENX Software Engineering, lukma@denx.de
  5. */
  6. #include <common.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/iomux.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/gpio.h>
  13. #include <asm/mach-imx/iomux-v3.h>
  14. #include <asm/mach-imx/mxc_i2c.h>
  15. #include <asm/mach-imx/spi.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/io.h>
  18. #include <fsl_esdhc_imx.h>
  19. #include <mmc.h>
  20. #include <netdev.h>
  21. #include <micrel.h>
  22. #include <phy.h>
  23. #include <input.h>
  24. #include <i2c.h>
  25. #include <spl.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  28. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  29. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  30. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  31. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  32. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  34. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  35. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  36. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  37. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  38. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  39. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  40. #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  41. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  42. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  43. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  44. #define ETH_PHY_RESET IMX_GPIO_NR(1, 27)
  45. #define ECSPI3_CS0 IMX_GPIO_NR(4, 24)
  46. #define ECSPI3_FLWP IMX_GPIO_NR(4, 27)
  47. #define NOR_WP IMX_GPIO_NR(1, 1)
  48. #define DISPLAY_EN IMX_GPIO_NR(1, 2)
  49. int dram_init(void)
  50. {
  51. gd->ram_size = imx_ddr_size();
  52. return 0;
  53. }
  54. static iomux_v3_cfg_t const uart1_pads[] = {
  55. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  56. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  57. };
  58. static iomux_v3_cfg_t const usdhc2_pads[] = {
  59. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  60. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  61. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  62. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  63. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  64. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  65. /* Carrier MicroSD Card Detect */
  66. IOMUX_PADS(PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  67. };
  68. static iomux_v3_cfg_t const usdhc3_pads[] = {
  69. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  70. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  71. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  72. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  73. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  74. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  75. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  76. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  77. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  78. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  79. IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  80. };
  81. static iomux_v3_cfg_t const enet_pads[] = {
  82. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  83. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  84. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  85. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  86. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  87. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  88. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  89. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL
  90. | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  91. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK
  92. | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  93. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  94. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  95. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  96. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  97. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  98. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL
  99. | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  100. /* KSZ9031 PHY Reset */
  101. IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  102. };
  103. static void setup_iomux_uart(void)
  104. {
  105. SETUP_IOMUX_PADS(uart1_pads);
  106. }
  107. static void setup_iomux_enet(void)
  108. {
  109. SETUP_IOMUX_PADS(enet_pads);
  110. /* Reset KSZ9031 PHY */
  111. gpio_direction_output(ETH_PHY_RESET, 0);
  112. mdelay(10);
  113. gpio_set_value(ETH_PHY_RESET, 1);
  114. udelay(100);
  115. }
  116. static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  117. {USDHC3_BASE_ADDR},
  118. {USDHC2_BASE_ADDR},
  119. };
  120. int board_mmc_getcd(struct mmc *mmc)
  121. {
  122. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  123. int ret = 0;
  124. switch (cfg->esdhc_base) {
  125. case USDHC2_BASE_ADDR:
  126. ret = !gpio_get_value(USDHC2_CD_GPIO);
  127. break;
  128. case USDHC3_BASE_ADDR:
  129. /*
  130. * eMMC don't have card detect pin - since it is soldered to the
  131. * PCB board
  132. */
  133. ret = 1;
  134. break;
  135. }
  136. return ret;
  137. }
  138. int board_mmc_init(bd_t *bis)
  139. {
  140. int ret;
  141. u32 index = 0;
  142. /*
  143. * MMC MAP
  144. * (U-Boot device node) (Physical Port)
  145. * mmc0 Soldered on board eMMC device
  146. * mmc1 MicroSD card
  147. */
  148. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  149. switch (index) {
  150. case 0:
  151. SETUP_IOMUX_PADS(usdhc3_pads);
  152. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  153. usdhc_cfg[0].max_bus_width = 8;
  154. break;
  155. case 1:
  156. SETUP_IOMUX_PADS(usdhc2_pads);
  157. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  158. usdhc_cfg[1].max_bus_width = 4;
  159. gpio_direction_input(USDHC2_CD_GPIO);
  160. break;
  161. default:
  162. printf("Warning: More USDHC controllers (%d) than supported (%d)\n",
  163. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  164. return -EINVAL;
  165. }
  166. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  167. if (ret)
  168. return ret;
  169. }
  170. return 0;
  171. }
  172. static iomux_v3_cfg_t const eimnor_pads[] = {
  173. IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  174. IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  175. IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  176. IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  177. IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  178. IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  179. IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  180. IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  181. IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  182. IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  183. IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  184. IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  185. IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  186. IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  187. IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  188. IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  189. IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  190. IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  191. IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  192. IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  193. IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  194. IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  195. IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  196. IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  197. IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  198. IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  199. IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  200. IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  201. IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  202. IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  203. IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  204. IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  205. IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  206. IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  207. IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  208. IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  209. IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  210. IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  211. IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  212. IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  213. IOMUX_PADS(PAD_EIM_A24__EIM_ADDR24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  214. IOMUX_PADS(PAD_EIM_A25__EIM_ADDR25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
  215. IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  216. IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
  217. IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  218. IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  219. };
  220. static void eimnor_cs_setup(void)
  221. {
  222. struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
  223. /* NOR configuration */
  224. writel(0x00620181, &weim_regs->cs0gcr1);
  225. writel(0x00000001, &weim_regs->cs0gcr2);
  226. writel(0x0b020000, &weim_regs->cs0rcr1);
  227. writel(0x0000b000, &weim_regs->cs0rcr2);
  228. writel(0x0804a240, &weim_regs->cs0wcr1);
  229. writel(0x00000000, &weim_regs->cs0wcr2);
  230. writel(0x00000120, &weim_regs->wcr);
  231. writel(0x00000010, &weim_regs->wiar);
  232. writel(0x00000000, &weim_regs->ear);
  233. set_chipselect_size(CS0_128);
  234. }
  235. static void setup_eimnor(void)
  236. {
  237. SETUP_IOMUX_PADS(eimnor_pads);
  238. gpio_direction_output(NOR_WP, 1);
  239. enable_eim_clk(1);
  240. eimnor_cs_setup();
  241. }
  242. /* mccmon6 board has SPI Flash is connected to SPI3 */
  243. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  244. {
  245. return (bus == 2 && cs == 0) ? ECSPI3_CS0 : -1;
  246. }
  247. static iomux_v3_cfg_t const ecspi3_pads[] = {
  248. /* SPI3 */
  249. IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  250. IOMUX_PADS(PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  251. IOMUX_PADS(PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  252. IOMUX_PADS(PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  253. };
  254. void setup_spi(void)
  255. {
  256. SETUP_IOMUX_PADS(ecspi3_pads);
  257. enable_spi_clk(true, 2);
  258. /* set cs0 to high */
  259. gpio_direction_output(ECSPI3_CS0, 1);
  260. /* set flwp to high */
  261. gpio_direction_output(ECSPI3_FLWP, 1);
  262. }
  263. struct i2c_pads_info mx6q_i2c1_pad_info = {
  264. .scl = {
  265. .i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL
  266. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  267. .gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27
  268. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  269. .gp = IMX_GPIO_NR(5, 27)
  270. },
  271. .sda = {
  272. .i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA
  273. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  274. .gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26
  275. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  276. .gp = IMX_GPIO_NR(5, 26)
  277. }
  278. };
  279. struct i2c_pads_info mx6q_i2c2_pad_info = {
  280. .scl = {
  281. .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL
  282. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  283. .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12
  284. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  285. .gp = IMX_GPIO_NR(4, 12)
  286. },
  287. .sda = {
  288. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA
  289. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  290. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13
  291. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  292. .gp = IMX_GPIO_NR(4, 13)
  293. }
  294. };
  295. int board_eth_init(bd_t *bis)
  296. {
  297. setup_iomux_enet();
  298. return cpu_eth_init(bis);
  299. }
  300. int board_early_init_f(void)
  301. {
  302. setup_iomux_uart();
  303. return 0;
  304. }
  305. int board_init(void)
  306. {
  307. /* address of boot parameters */
  308. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  309. gpio_direction_output(DISPLAY_EN, 1);
  310. setup_eimnor();
  311. setup_spi();
  312. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c1_pad_info);
  313. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
  314. return 0;
  315. }
  316. int board_late_init(void)
  317. {
  318. env_set("board_name", "mccmon6");
  319. return 0;
  320. }
  321. int checkboard(void)
  322. {
  323. puts("Board: MCCMON6\n");
  324. return 0;
  325. }
  326. int board_phy_config(struct phy_device *phydev)
  327. {
  328. /*
  329. * Default setting for GMII Clock Pad Skew Register 0x1EF:
  330. * MMD Address 0x2h, Register 0x8h
  331. *
  332. * GTX_CLK Pad Skew 0xF -> 0.9 nsec skew
  333. * RX_CLK Pad Skew 0xF -> 0.9 nsec skew
  334. *
  335. * Adjustment -> write 0x3FF:
  336. * GTX_CLK Pad Skew 0x1F -> 1.8 nsec skew
  337. * RX_CLK Pad Skew 0x1F -> 1.8 nsec skew
  338. *
  339. */
  340. ksz9031_phy_extended_write(phydev, 0x2,
  341. MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
  342. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x3FF);
  343. ksz9031_phy_extended_write(phydev, 0x02,
  344. MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
  345. MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x00FF);
  346. ksz9031_phy_extended_write(phydev, 0x2,
  347. MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
  348. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  349. 0x3333);
  350. ksz9031_phy_extended_write(phydev, 0x2,
  351. MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
  352. MII_KSZ9031_MOD_DATA_NO_POST_INC,
  353. 0x2052);
  354. if (phydev->drv->config)
  355. phydev->drv->config(phydev);
  356. return 0;
  357. }
  358. #ifdef CONFIG_SPL_BOARD_INIT
  359. void spl_board_init(void)
  360. {
  361. setup_eimnor();
  362. gpio_direction_output(DISPLAY_EN, 1);
  363. }
  364. #endif /* CONFIG_SPL_BOARD_INIT */
  365. #ifdef CONFIG_SPL_BUILD
  366. void board_boot_order(u32 *spl_boot_list)
  367. {
  368. switch (spl_boot_device()) {
  369. case BOOT_DEVICE_MMC2:
  370. case BOOT_DEVICE_MMC1:
  371. spl_boot_list[0] = BOOT_DEVICE_MMC2;
  372. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  373. break;
  374. case BOOT_DEVICE_NOR:
  375. spl_boot_list[0] = BOOT_DEVICE_NOR;
  376. break;
  377. }
  378. }
  379. #endif /* CONFIG_SPL_BUILD */
  380. #ifdef CONFIG_SPL_OS_BOOT
  381. int spl_start_uboot(void)
  382. {
  383. char s[16];
  384. int ret;
  385. /*
  386. * We use BOOT_DEVICE_MMC1, but SD card is connected
  387. * to MMC2
  388. *
  389. * Correct "mapping" is delivered in board defined
  390. * board_boot_order() function.
  391. *
  392. * SD card boot is regarded as a "development" one,
  393. * hence we _always_ go through the u-boot.
  394. *
  395. */
  396. if (spl_boot_device() == BOOT_DEVICE_MMC1)
  397. return 1;
  398. /* break into full u-boot on 'c' */
  399. if (serial_tstc() && serial_getc() == 'c')
  400. return 1;
  401. env_init();
  402. ret = env_get_f("boot_os", s, sizeof(s));
  403. if ((ret != -1) && (strcmp(s, "no") == 0))
  404. return 1;
  405. /*
  406. * Check if SWUpdate recovery needs to be started
  407. *
  408. * recovery_status = NULL (not set - ret == -1) -> normal operation
  409. *
  410. * recovery_status = progress or
  411. * recovery_status = failed or
  412. * recovery_status = <any value> -> start SWUpdate
  413. *
  414. */
  415. ret = env_get_f("recovery_status", s, sizeof(s));
  416. if (ret != -1)
  417. return 1;
  418. return 0;
  419. }
  420. #endif /* CONFIG_SPL_OS_BOOT */