novena_spl.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Novena SPL
  4. *
  5. * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/clock.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/mx6-ddr.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/mxc_i2c.h>
  18. #include <asm/arch/crm_regs.h>
  19. #include <i2c.h>
  20. #include <mmc.h>
  21. #include <fsl_esdhc_imx.h>
  22. #include <spl.h>
  23. #include <asm/arch/mx6-ddr.h>
  24. #include "novena.h"
  25. #define UART_PAD_CTRL \
  26. (PAD_CTL_PKE | PAD_CTL_PUE | \
  27. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  28. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  29. #define USDHC_PAD_CTRL \
  30. (PAD_CTL_PKE | PAD_CTL_PUE | \
  31. PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  32. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33. #define ENET_PAD_CTRL \
  34. (PAD_CTL_PKE | PAD_CTL_PUE | \
  35. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  36. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  37. #define ENET_PHY_CFG_PAD_CTRL \
  38. (PAD_CTL_PKE | PAD_CTL_PUE | \
  39. PAD_CTL_PUS_22K_UP | PAD_CTL_HYS)
  40. #define RGMII_PAD_CTRL \
  41. (PAD_CTL_PKE | PAD_CTL_PUE | \
  42. PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  43. #define SPI_PAD_CTRL \
  44. (PAD_CTL_HYS | \
  45. PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \
  46. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  47. #define I2C_PAD_CTRL \
  48. (PAD_CTL_PKE | PAD_CTL_PUE | \
  49. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
  50. PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \
  51. PAD_CTL_ODE)
  52. #define BUTTON_PAD_CTRL \
  53. (PAD_CTL_PKE | PAD_CTL_PUE | \
  54. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  55. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  56. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  57. /*
  58. * Audio
  59. */
  60. static iomux_v3_cfg_t audio_pads[] = {
  61. /* AUD_PWRON */
  62. MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),
  63. };
  64. static void novena_spl_setup_iomux_audio(void)
  65. {
  66. imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads));
  67. gpio_direction_output(NOVENA_AUDIO_PWRON, 1);
  68. }
  69. /*
  70. * ENET
  71. */
  72. static iomux_v3_cfg_t enet_pads1[] = {
  73. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  76. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  77. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  78. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  79. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  80. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  81. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82. /* pin 35, PHY_AD2 */
  83. MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  84. /* pin 32, MODE0 */
  85. MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  86. /* pin 31, MODE1 */
  87. MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  88. /* pin 28, MODE2 */
  89. MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  90. /* pin 27, MODE3 */
  91. MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  92. /* pin 33, CLK125_EN */
  93. MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL),
  94. /* pin 42 PHY nRST */
  95. MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  96. };
  97. static iomux_v3_cfg_t enet_pads2[] = {
  98. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  99. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  100. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  101. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  102. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  103. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL),
  104. };
  105. static void novena_spl_setup_iomux_enet(void)
  106. {
  107. imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  108. /* Assert Ethernet PHY nRST */
  109. gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
  110. /*
  111. * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset
  112. * de-assertion. The intention is to use weak signal drivers (pull-ups)
  113. * to prevent the conflict between PHY pins becoming outputs after
  114. * reset and imx6 still driving the pins. The issue is described in PHY
  115. * datasheet, p.14
  116. */
  117. gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */
  118. gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */
  119. gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */
  120. gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */
  121. gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */
  122. gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */
  123. /* Following reset timing (p.53, fig.8 from the PHY datasheet) */
  124. mdelay(10);
  125. /* De-assert Ethernet PHY nRST */
  126. gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  127. /* PHY is now configured, connect FEC to the pads */
  128. imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  129. /*
  130. * PHY datasheet recommends on p.53 to wait at least 100us after reset
  131. * before using MII, so we enforce the delay here
  132. */
  133. udelay(100);
  134. }
  135. /*
  136. * FPGA
  137. */
  138. static iomux_v3_cfg_t fpga_pads[] = {
  139. /* FPGA_RESET_N */
  140. MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  141. };
  142. static void novena_spl_setup_iomux_fpga(void)
  143. {
  144. imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads));
  145. gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0);
  146. }
  147. /*
  148. * GPIO Button
  149. */
  150. static iomux_v3_cfg_t button_pads[] = {
  151. /* Debug */
  152. MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  153. };
  154. static void novena_spl_setup_iomux_buttons(void)
  155. {
  156. imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads));
  157. }
  158. /*
  159. * I2C
  160. */
  161. /*
  162. * I2C1:
  163. * 0x1d ... MMA7455L
  164. * 0x30 ... SO-DIMM temp sensor
  165. * 0x44 ... STMPE610
  166. * 0x50 ... SO-DIMM ID
  167. */
  168. struct i2c_pads_info i2c_pad_info0 = {
  169. .scl = {
  170. .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  171. .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  172. .gp = IMX_GPIO_NR(3, 21)
  173. },
  174. .sda = {
  175. .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  176. .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  177. .gp = IMX_GPIO_NR(3, 28)
  178. }
  179. };
  180. /*
  181. * I2C2:
  182. * 0x08 ... PMIC
  183. * 0x3a ... HDMI DCC
  184. * 0x50 ... HDMI DCC
  185. */
  186. static struct i2c_pads_info i2c_pad_info1 = {
  187. .scl = {
  188. .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
  189. .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
  190. .gp = IMX_GPIO_NR(2, 30)
  191. },
  192. .sda = {
  193. .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
  194. .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
  195. .gp = IMX_GPIO_NR(3, 16)
  196. }
  197. };
  198. /*
  199. * I2C3:
  200. * 0x11 ... ES8283
  201. * 0x50 ... LCD EDID
  202. * 0x56 ... EEPROM
  203. */
  204. static struct i2c_pads_info i2c_pad_info2 = {
  205. .scl = {
  206. .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
  207. .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
  208. .gp = IMX_GPIO_NR(3, 17)
  209. },
  210. .sda = {
  211. .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
  212. .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
  213. .gp = IMX_GPIO_NR(3, 18)
  214. }
  215. };
  216. static void novena_spl_setup_iomux_i2c(void)
  217. {
  218. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  219. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  220. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  221. }
  222. /*
  223. * PCI express
  224. */
  225. #ifdef CONFIG_CMD_PCI
  226. static iomux_v3_cfg_t pcie_pads[] = {
  227. /* "Reset" pin */
  228. MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  229. /* "Power on" pin */
  230. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  231. /* "Wake up" pin (input) */
  232. MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  233. /* "Disable endpoint" (rfkill) pin */
  234. MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  235. };
  236. static void novena_spl_setup_iomux_pcie(void)
  237. {
  238. imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  239. /* Ensure PCIe is powered down */
  240. gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0);
  241. /* Put the card into reset */
  242. gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0);
  243. /* Input signal to wake system from mPCIe card */
  244. gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO);
  245. /* Drive RFKILL high, to ensure the radio is turned on */
  246. gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1);
  247. }
  248. #else
  249. static inline void novena_spl_setup_iomux_pcie(void) {}
  250. #endif
  251. /*
  252. * SDHC
  253. */
  254. static iomux_v3_cfg_t usdhc2_pads[] = {
  255. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  256. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  257. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  258. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  259. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  260. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  261. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
  262. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  263. };
  264. static iomux_v3_cfg_t usdhc3_pads[] = {
  265. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  266. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  267. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  268. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  269. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  270. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  271. };
  272. static void novena_spl_setup_iomux_sdhc(void)
  273. {
  274. imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  275. imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  276. /* Big SD write-protect and card-detect */
  277. gpio_direction_input(IMX_GPIO_NR(1, 2));
  278. gpio_direction_input(IMX_GPIO_NR(1, 4));
  279. }
  280. /*
  281. * SPI
  282. */
  283. #ifdef CONFIG_MXC_SPI
  284. static iomux_v3_cfg_t ecspi3_pads[] = {
  285. /* SS1 */
  286. MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  287. MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  288. MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  289. MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  290. MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  291. MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL),
  292. MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL),
  293. };
  294. static void novena_spl_setup_iomux_spi(void)
  295. {
  296. imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
  297. /* De-assert the nCS */
  298. gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1);
  299. gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1);
  300. gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1);
  301. }
  302. #else
  303. static void novena_spl_setup_iomux_spi(void) {}
  304. #endif
  305. /*
  306. * UART
  307. */
  308. static iomux_v3_cfg_t const uart2_pads[] = {
  309. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  310. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  311. };
  312. static iomux_v3_cfg_t const uart3_pads[] = {
  313. MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  314. MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  315. };
  316. static iomux_v3_cfg_t const uart4_pads[] = {
  317. MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  318. MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  319. MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  320. MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  321. };
  322. static void novena_spl_setup_iomux_uart(void)
  323. {
  324. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  325. imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  326. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  327. }
  328. /*
  329. * Video
  330. */
  331. #ifdef CONFIG_VIDEO
  332. static iomux_v3_cfg_t hdmi_pads[] = {
  333. /* "Ghost HPD" pin */
  334. MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  335. /* LCD_PWR_CTL */
  336. MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  337. /* LCD_BL_ON */
  338. MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  339. /* GPIO_PWM1 */
  340. MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  341. };
  342. static void novena_spl_setup_iomux_video(void)
  343. {
  344. imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads));
  345. gpio_direction_input(NOVENA_HDMI_GHOST_HPD);
  346. }
  347. #else
  348. static inline void novena_spl_setup_iomux_video(void) {}
  349. #endif
  350. /*
  351. * SPL boots from uSDHC card
  352. */
  353. #ifdef CONFIG_FSL_ESDHC_IMX
  354. static struct fsl_esdhc_cfg usdhc_cfg = {
  355. USDHC3_BASE_ADDR, 0, 4
  356. };
  357. int board_mmc_getcd(struct mmc *mmc)
  358. {
  359. /* There is no CD for a microSD card, assume always present. */
  360. return 1;
  361. }
  362. int board_mmc_init(bd_t *bis)
  363. {
  364. usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  365. return fsl_esdhc_initialize(bis, &usdhc_cfg);
  366. }
  367. #endif
  368. /* Configure MX6Q/DUAL mmdc DDR io registers */
  369. static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = {
  370. /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  371. .dram_sdclk_0 = 0x00020038,
  372. .dram_sdclk_1 = 0x00020038,
  373. .dram_cas = 0x00000038,
  374. .dram_ras = 0x00000038,
  375. .dram_reset = 0x00000038,
  376. /* SDCKE[0:1]: 100k pull-up */
  377. .dram_sdcke0 = 0x00000038,
  378. .dram_sdcke1 = 0x00000038,
  379. /* SDBA2: pull-up disabled */
  380. .dram_sdba2 = 0x00000000,
  381. /* SDODT[0:1]: 100k pull-up, 40 ohm */
  382. .dram_sdodt0 = 0x00000038,
  383. .dram_sdodt1 = 0x00000038,
  384. /* SDQS[0:7]: Differential input, 40 ohm */
  385. .dram_sdqs0 = 0x00000038,
  386. .dram_sdqs1 = 0x00000038,
  387. .dram_sdqs2 = 0x00000038,
  388. .dram_sdqs3 = 0x00000038,
  389. .dram_sdqs4 = 0x00000038,
  390. .dram_sdqs5 = 0x00000038,
  391. .dram_sdqs6 = 0x00000038,
  392. .dram_sdqs7 = 0x00000038,
  393. /* DQM[0:7]: Differential input, 40 ohm */
  394. .dram_dqm0 = 0x00000038,
  395. .dram_dqm1 = 0x00000038,
  396. .dram_dqm2 = 0x00000038,
  397. .dram_dqm3 = 0x00000038,
  398. .dram_dqm4 = 0x00000038,
  399. .dram_dqm5 = 0x00000038,
  400. .dram_dqm6 = 0x00000038,
  401. .dram_dqm7 = 0x00000038,
  402. };
  403. /* Configure MX6Q/DUAL mmdc GRP io registers */
  404. static struct mx6dq_iomux_grp_regs novena_grp_ioregs = {
  405. /* DDR3 */
  406. .grp_ddr_type = 0x000c0000,
  407. .grp_ddrmode_ctl = 0x00020000,
  408. /* Disable DDR pullups */
  409. .grp_ddrpke = 0x00000000,
  410. /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  411. .grp_addds = 0x00000038,
  412. /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  413. .grp_ctlds = 0x00000038,
  414. /* DATA[00:63]: Differential input, 40 ohm */
  415. .grp_ddrmode = 0x00020000,
  416. .grp_b0ds = 0x00000038,
  417. .grp_b1ds = 0x00000038,
  418. .grp_b2ds = 0x00000038,
  419. .grp_b3ds = 0x00000038,
  420. .grp_b4ds = 0x00000038,
  421. .grp_b5ds = 0x00000038,
  422. .grp_b6ds = 0x00000038,
  423. .grp_b7ds = 0x00000038,
  424. };
  425. static struct mx6_mmdc_calibration novena_mmdc_calib = {
  426. /* write leveling calibration determine */
  427. .p0_mpwldectrl0 = 0x00420048,
  428. .p0_mpwldectrl1 = 0x006f0059,
  429. .p1_mpwldectrl0 = 0x005a0104,
  430. .p1_mpwldectrl1 = 0x01070113,
  431. /* Read DQS Gating calibration */
  432. .p0_mpdgctrl0 = 0x437c040b,
  433. .p0_mpdgctrl1 = 0x0413040e,
  434. .p1_mpdgctrl0 = 0x444f0446,
  435. .p1_mpdgctrl1 = 0x044d0422,
  436. /* Read Calibration: DQS delay relative to DQ read access */
  437. .p0_mprddlctl = 0x4c424249,
  438. .p1_mprddlctl = 0x4e48414f,
  439. /* Write Calibration: DQ/DM delay relative to DQS write access */
  440. .p0_mpwrdlctl = 0x42414641,
  441. .p1_mpwrdlctl = 0x46374b43,
  442. };
  443. static struct mx6_ddr_sysinfo novena_ddr_info = {
  444. /* Width of data bus: 0=16, 1=32, 2=64 */
  445. .dsize = 2,
  446. /* Config for full 4GB range so that get_mem_size() works */
  447. .cs_density = 32, /* 32Gb per CS */
  448. /* Single chip select */
  449. .ncs = 1,
  450. .cs1_mirror = 0,
  451. .rtt_wr = 0, /* RTT_Wr = RZQ/4 */
  452. .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
  453. .walat = 0, /* Write additional latency */
  454. .ralat = 5, /* Read additional latency */
  455. .mif3_mode = 3, /* Command prediction working mode */
  456. .bi_on = 1, /* Bank interleaving enabled */
  457. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  458. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  459. .refsel = 1, /* Refresh cycles at 32KHz */
  460. .refr = 7, /* 8 refresh commands per refresh cycle */
  461. };
  462. static struct mx6_ddr3_cfg elpida_4gib_1600 = {
  463. .mem_speed = 1600,
  464. .density = 4,
  465. .width = 64,
  466. .banks = 8,
  467. .rowaddr = 16,
  468. .coladdr = 10,
  469. .pagesz = 2,
  470. .trcd = 1375,
  471. .trcmin = 4875,
  472. .trasmin = 3500,
  473. };
  474. static void ccgr_init(void)
  475. {
  476. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  477. writel(0x00C03F3F, &ccm->CCGR0);
  478. writel(0x0030FC03, &ccm->CCGR1);
  479. writel(0x0FFFC000, &ccm->CCGR2);
  480. writel(0x3FF00000, &ccm->CCGR3);
  481. writel(0xFFFFF300, &ccm->CCGR4);
  482. writel(0x0F0000C3, &ccm->CCGR5);
  483. writel(0x000003FF, &ccm->CCGR6);
  484. }
  485. /*
  486. * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
  487. * - we have a stack and a place to store GD, both in SRAM
  488. * - no variable global data is available
  489. */
  490. void board_init_f(ulong dummy)
  491. {
  492. /* setup AIPS and disable watchdog */
  493. arch_cpu_init();
  494. ccgr_init();
  495. gpr_init();
  496. /* setup GP timer */
  497. timer_init();
  498. #ifdef CONFIG_BOARD_POSTCLK_INIT
  499. board_postclk_init();
  500. #endif
  501. #ifdef CONFIG_FSL_ESDHC_IMX
  502. get_clocks();
  503. #endif
  504. /* Setup IOMUX and configure basics. */
  505. novena_spl_setup_iomux_audio();
  506. novena_spl_setup_iomux_buttons();
  507. novena_spl_setup_iomux_enet();
  508. novena_spl_setup_iomux_fpga();
  509. novena_spl_setup_iomux_i2c();
  510. novena_spl_setup_iomux_pcie();
  511. novena_spl_setup_iomux_sdhc();
  512. novena_spl_setup_iomux_spi();
  513. novena_spl_setup_iomux_uart();
  514. novena_spl_setup_iomux_video();
  515. /* UART clocks enabled and gd valid - init serial console */
  516. preloader_console_init();
  517. /* Start the DDR DRAM */
  518. mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
  519. mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
  520. /* Perform DDR DRAM calibration */
  521. udelay(100);
  522. mmdc_do_write_level_calibration(&novena_ddr_info);
  523. mmdc_do_dqs_calibration(&novena_ddr_info);
  524. }