board.c 5.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2016 Grinn
  5. */
  6. #include <asm/arch/clock.h>
  7. #include <asm/arch/iomux.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/litesom.h>
  11. #include <asm/arch/mx6ul_pins.h>
  12. #include <asm/arch/mx6-pins.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/io.h>
  18. #include <common.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <linux/sizes.h>
  21. #include <linux/fb.h>
  22. #include <miiphy.h>
  23. #include <mmc.h>
  24. #include <netdev.h>
  25. #include <spl.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  28. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  29. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  30. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  31. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  32. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  34. PAD_CTL_SPEED_HIGH | \
  35. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  36. #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  37. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  38. #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  39. static iomux_v3_cfg_t const uart1_pads[] = {
  40. MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  41. MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  42. };
  43. static iomux_v3_cfg_t const sd_pads[] = {
  44. MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  45. MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  46. MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  47. MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  48. MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  49. MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  50. /* CD */
  51. MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  52. };
  53. static void setup_iomux_uart(void)
  54. {
  55. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  56. }
  57. #ifdef CONFIG_FSL_ESDHC_IMX
  58. static struct fsl_esdhc_cfg sd_cfg = {USDHC1_BASE_ADDR, 0, 4};
  59. #define SD_CD_GPIO IMX_GPIO_NR(1, 19)
  60. static int mmc_get_env_devno(void)
  61. {
  62. u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
  63. int dev_no;
  64. u32 bootsel;
  65. bootsel = (soc_sbmr & 0x000000FF) >> 6;
  66. /* If not boot from sd/mmc, use default value */
  67. if (bootsel != 1)
  68. return CONFIG_SYS_MMC_ENV_DEV;
  69. /* BOOT_CFG2[3] and BOOT_CFG2[4] */
  70. dev_no = (soc_sbmr & 0x00001800) >> 11;
  71. return dev_no;
  72. }
  73. int board_mmc_getcd(struct mmc *mmc)
  74. {
  75. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  76. int ret = 0;
  77. switch (cfg->esdhc_base) {
  78. case USDHC1_BASE_ADDR:
  79. ret = !gpio_get_value(SD_CD_GPIO);
  80. break;
  81. case USDHC2_BASE_ADDR:
  82. ret = 1;
  83. break;
  84. }
  85. return ret;
  86. }
  87. int board_mmc_init(bd_t *bis)
  88. {
  89. int ret;
  90. /* SD */
  91. imx_iomux_v3_setup_multiple_pads(sd_pads, ARRAY_SIZE(sd_pads));
  92. gpio_direction_input(SD_CD_GPIO);
  93. sd_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  94. ret = fsl_esdhc_initialize(bis, &sd_cfg);
  95. if (ret) {
  96. printf("Warning: failed to initialize mmc dev 0 (SD)\n");
  97. return ret;
  98. }
  99. return litesom_mmc_init(bis);
  100. }
  101. static int check_mmc_autodetect(void)
  102. {
  103. char *autodetect_str = env_get("mmcautodetect");
  104. if ((autodetect_str != NULL) &&
  105. (strcmp(autodetect_str, "yes") == 0)) {
  106. return 1;
  107. }
  108. return 0;
  109. }
  110. void board_late_mmc_init(void)
  111. {
  112. char cmd[32];
  113. char mmcblk[32];
  114. u32 dev_no = mmc_get_env_devno();
  115. if (!check_mmc_autodetect())
  116. return;
  117. env_set_ulong("mmcdev", dev_no);
  118. /* Set mmcblk env */
  119. sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
  120. dev_no);
  121. env_set("mmcroot", mmcblk);
  122. sprintf(cmd, "mmc dev %d", dev_no);
  123. run_command(cmd, 0);
  124. }
  125. #endif
  126. #ifdef CONFIG_FEC_MXC
  127. static int setup_fec(void)
  128. {
  129. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  130. int ret;
  131. /* Use 50M anatop loopback REF_CLK1 for ENET1, clear gpr1[13],
  132. set gpr1[17]*/
  133. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  134. IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  135. ret = enable_fec_anatop_clock(0, ENET_50MHZ);
  136. if (ret)
  137. return ret;
  138. enable_enet_clk(1);
  139. return 0;
  140. }
  141. #endif
  142. int board_early_init_f(void)
  143. {
  144. setup_iomux_uart();
  145. return 0;
  146. }
  147. int board_init(void)
  148. {
  149. /* Address of boot parameters */
  150. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  151. #ifdef CONFIG_FEC_MXC
  152. setup_fec();
  153. #endif
  154. return 0;
  155. }
  156. #ifdef CONFIG_CMD_BMODE
  157. static const struct boot_mode board_boot_modes[] = {
  158. /* 4 bit bus width */
  159. {"sd", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  160. {"emmc", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00)},
  161. {NULL, 0},
  162. };
  163. #endif
  164. int board_late_init(void)
  165. {
  166. #ifdef CONFIG_CMD_BMODE
  167. add_board_boot_modes(board_boot_modes);
  168. #endif
  169. #ifdef CONFIG_ENV_IS_IN_MMC
  170. board_late_mmc_init();
  171. #endif
  172. return 0;
  173. }
  174. int checkboard(void)
  175. {
  176. puts("Board: Grinn liteBoard\n");
  177. return 0;
  178. }
  179. #ifdef CONFIG_SPL_BUILD
  180. void board_boot_order(u32 *spl_boot_list)
  181. {
  182. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  183. unsigned gpr10_boot = readl(&psrc->gpr10) & (1 << 28);
  184. unsigned reg = gpr10_boot ? readl(&psrc->gpr9) : readl(&psrc->sbmr1);
  185. unsigned port = (reg >> 11) & 0x1;
  186. if (port == 0) {
  187. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  188. spl_boot_list[1] = BOOT_DEVICE_MMC2;
  189. } else {
  190. spl_boot_list[0] = BOOT_DEVICE_MMC2;
  191. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  192. }
  193. }
  194. void board_init_f(ulong dummy)
  195. {
  196. litesom_init_f();
  197. }
  198. #endif