gw_ventana.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Gateworks Corporation
  4. *
  5. * Author: Tim Harvey <tharvey@gateworks.com>
  6. */
  7. #include <common.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/crm_regs.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <asm/arch/mxc_hdmi.h>
  13. #include <asm/arch/sys_proto.h>
  14. #include <asm/gpio.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/mach-imx/sata.h>
  17. #include <asm/mach-imx/spi.h>
  18. #include <asm/mach-imx/video.h>
  19. #include <asm/io.h>
  20. #include <asm/setup.h>
  21. #include <dm.h>
  22. #include <dm/platform_data/serial_mxc.h>
  23. #include <environment.h>
  24. #include <hwconfig.h>
  25. #include <i2c.h>
  26. #include <fdt_support.h>
  27. #include <fsl_esdhc_imx.h>
  28. #include <jffs2/load_kernel.h>
  29. #include <linux/ctype.h>
  30. #include <miiphy.h>
  31. #include <mtd_node.h>
  32. #include <netdev.h>
  33. #include <pci.h>
  34. #include <power/pmic.h>
  35. #include <power/ltc3676_pmic.h>
  36. #include <power/pfuze100_pmic.h>
  37. #include <fdt_support.h>
  38. #include <jffs2/load_kernel.h>
  39. #include <spi_flash.h>
  40. #include "gsc.h"
  41. #include "common.h"
  42. DECLARE_GLOBAL_DATA_PTR;
  43. /*
  44. * EEPROM board info struct populated by read_eeprom so that we only have to
  45. * read it once.
  46. */
  47. struct ventana_board_info ventana_info;
  48. static int board_type;
  49. /* ENET */
  50. static iomux_v3_cfg_t const enet_pads[] = {
  51. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  52. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  53. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  54. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  55. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  56. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  57. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  58. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
  59. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  60. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
  61. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
  68. MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69. /* PHY nRST */
  70. IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
  71. };
  72. #ifdef CONFIG_CMD_NAND
  73. static iomux_v3_cfg_t const nfc_pads[] = {
  74. IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  75. IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
  76. IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  77. IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  78. IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  79. IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  80. IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
  81. IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  82. IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  83. IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  84. IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  85. IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  86. IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  87. IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  88. IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  89. };
  90. static void setup_gpmi_nand(void)
  91. {
  92. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  93. /* config gpmi nand iomux */
  94. SETUP_IOMUX_PADS(nfc_pads);
  95. /* config gpmi and bch clock to 100 MHz */
  96. clrsetbits_le32(&mxc_ccm->cs2cdr,
  97. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  98. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  99. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  100. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  101. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  102. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  103. /* enable gpmi and bch clock gating */
  104. setbits_le32(&mxc_ccm->CCGR4,
  105. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  106. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  107. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  108. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  109. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  110. /* enable apbh clock gating */
  111. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  112. }
  113. #endif
  114. static void setup_iomux_enet(int gpio)
  115. {
  116. SETUP_IOMUX_PADS(enet_pads);
  117. /* toggle PHY_RST# */
  118. gpio_request(gpio, "phy_rst#");
  119. gpio_direction_output(gpio, 0);
  120. mdelay(10);
  121. gpio_set_value(gpio, 1);
  122. mdelay(100);
  123. }
  124. #ifdef CONFIG_USB_EHCI_MX6
  125. static iomux_v3_cfg_t const usb_pads[] = {
  126. IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
  127. IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
  128. /* OTG PWR */
  129. IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
  130. };
  131. int board_ehci_hcd_init(int port)
  132. {
  133. int gpio;
  134. SETUP_IOMUX_PADS(usb_pads);
  135. /* Reset USB HUB */
  136. switch (board_type) {
  137. case GW53xx:
  138. case GW552x:
  139. case GW5906:
  140. gpio = (IMX_GPIO_NR(1, 9));
  141. break;
  142. case GW54proto:
  143. case GW54xx:
  144. gpio = (IMX_GPIO_NR(1, 16));
  145. break;
  146. default:
  147. return 0;
  148. }
  149. /* request and toggle hub rst */
  150. gpio_request(gpio, "usb_hub_rst#");
  151. gpio_direction_output(gpio, 0);
  152. mdelay(2);
  153. gpio_set_value(gpio, 1);
  154. return 0;
  155. }
  156. int board_ehci_power(int port, int on)
  157. {
  158. /* enable OTG VBUS */
  159. if (!port && board_type < GW_UNKNOWN) {
  160. if (gpio_cfg[board_type].otgpwr_en)
  161. gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
  162. }
  163. return 0;
  164. }
  165. #endif /* CONFIG_USB_EHCI_MX6 */
  166. #ifdef CONFIG_MXC_SPI
  167. iomux_v3_cfg_t const ecspi1_pads[] = {
  168. /* SS1 */
  169. IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  170. IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  171. IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  172. IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  173. };
  174. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  175. {
  176. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
  177. }
  178. static void setup_spi(void)
  179. {
  180. gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
  181. gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
  182. SETUP_IOMUX_PADS(ecspi1_pads);
  183. }
  184. #endif
  185. /* configure eth0 PHY board-specific LED behavior */
  186. int board_phy_config(struct phy_device *phydev)
  187. {
  188. unsigned short val;
  189. /* Marvel 88E1510 */
  190. if (phydev->phy_id == 0x1410dd1) {
  191. /*
  192. * Page 3, Register 16: LED[2:0] Function Control Register
  193. * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
  194. * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
  195. */
  196. phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
  197. val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
  198. val &= 0xff00;
  199. val |= 0x0017;
  200. phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
  201. phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
  202. }
  203. /* TI DP83867 */
  204. else if (phydev->phy_id == 0x2000a231) {
  205. /* configure register 0x170 for ref CLKOUT */
  206. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
  207. phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
  208. phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
  209. val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
  210. val &= ~0x1f00;
  211. val |= 0x0b00; /* chD tx clock*/
  212. phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
  213. }
  214. if (phydev->drv->config)
  215. phydev->drv->config(phydev);
  216. return 0;
  217. }
  218. #ifdef CONFIG_MV88E61XX_SWITCH
  219. int mv88e61xx_hw_reset(struct phy_device *phydev)
  220. {
  221. struct mii_dev *bus = phydev->bus;
  222. /* GPIO[0] output, CLK125 */
  223. debug("enabling RGMII_REFCLK\n");
  224. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  225. 0x1a /*MV_SCRATCH_MISC*/,
  226. (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
  227. bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
  228. 0x1a /*MV_SCRATCH_MISC*/,
  229. (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
  230. /* RGMII delay - Physical Control register bit[15:14] */
  231. debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
  232. /* forced 1000mbps full-duplex link */
  233. bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
  234. phydev->autoneg = AUTONEG_DISABLE;
  235. phydev->speed = SPEED_1000;
  236. phydev->duplex = DUPLEX_FULL;
  237. /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
  238. bus->write(bus, 0x10, 0, 0x16, 0x8088);
  239. bus->write(bus, 0x11, 0, 0x16, 0x8088);
  240. bus->write(bus, 0x12, 0, 0x16, 0x8088);
  241. bus->write(bus, 0x13, 0, 0x16, 0x8088);
  242. return 0;
  243. }
  244. #endif // CONFIG_MV88E61XX_SWITCH
  245. int board_eth_init(bd_t *bis)
  246. {
  247. #ifdef CONFIG_FEC_MXC
  248. struct ventana_board_info *info = &ventana_info;
  249. if (test_bit(EECONFIG_ETH0, info->config)) {
  250. setup_iomux_enet(GP_PHY_RST);
  251. cpu_eth_init(bis);
  252. }
  253. #endif
  254. #ifdef CONFIG_E1000
  255. e1000_initialize(bis);
  256. #endif
  257. #ifdef CONFIG_CI_UDC
  258. /* For otg ethernet*/
  259. usb_eth_initialize(bis);
  260. #endif
  261. /* default to the first detected enet dev */
  262. if (!env_get("ethprime")) {
  263. struct eth_device *dev = eth_get_dev_by_index(0);
  264. if (dev) {
  265. env_set("ethprime", dev->name);
  266. printf("set ethprime to %s\n", env_get("ethprime"));
  267. }
  268. }
  269. return 0;
  270. }
  271. #if defined(CONFIG_VIDEO_IPUV3)
  272. static void enable_hdmi(struct display_info_t const *dev)
  273. {
  274. imx_enable_hdmi_phy();
  275. }
  276. static int detect_i2c(struct display_info_t const *dev)
  277. {
  278. return i2c_set_bus_num(dev->bus) == 0 &&
  279. i2c_probe(dev->addr) == 0;
  280. }
  281. static void enable_lvds(struct display_info_t const *dev)
  282. {
  283. struct iomuxc *iomux = (struct iomuxc *)
  284. IOMUXC_BASE_ADDR;
  285. /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
  286. u32 reg = readl(&iomux->gpr[2]);
  287. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  288. writel(reg, &iomux->gpr[2]);
  289. /* Enable Backlight */
  290. gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
  291. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  292. gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
  293. SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
  294. gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
  295. }
  296. struct display_info_t const displays[] = {{
  297. /* HDMI Output */
  298. .bus = -1,
  299. .addr = 0,
  300. .pixfmt = IPU_PIX_FMT_RGB24,
  301. .detect = detect_hdmi,
  302. .enable = enable_hdmi,
  303. .mode = {
  304. .name = "HDMI",
  305. .refresh = 60,
  306. .xres = 1024,
  307. .yres = 768,
  308. .pixclock = 15385,
  309. .left_margin = 220,
  310. .right_margin = 40,
  311. .upper_margin = 21,
  312. .lower_margin = 7,
  313. .hsync_len = 60,
  314. .vsync_len = 10,
  315. .sync = FB_SYNC_EXT,
  316. .vmode = FB_VMODE_NONINTERLACED
  317. } }, {
  318. /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
  319. .bus = 2,
  320. .addr = 0x4,
  321. .pixfmt = IPU_PIX_FMT_LVDS666,
  322. .detect = detect_i2c,
  323. .enable = enable_lvds,
  324. .mode = {
  325. .name = "Hannstar-XGA",
  326. .refresh = 60,
  327. .xres = 1024,
  328. .yres = 768,
  329. .pixclock = 15385,
  330. .left_margin = 220,
  331. .right_margin = 40,
  332. .upper_margin = 21,
  333. .lower_margin = 7,
  334. .hsync_len = 60,
  335. .vsync_len = 10,
  336. .sync = FB_SYNC_EXT,
  337. .vmode = FB_VMODE_NONINTERLACED
  338. } }, {
  339. /* DLC700JMG-T-4 */
  340. .bus = 2,
  341. .addr = 0x38,
  342. .detect = NULL,
  343. .enable = enable_lvds,
  344. .pixfmt = IPU_PIX_FMT_LVDS666,
  345. .mode = {
  346. .name = "DLC700JMGT4",
  347. .refresh = 60,
  348. .xres = 1024, /* 1024x600active pixels */
  349. .yres = 600,
  350. .pixclock = 15385, /* 64MHz */
  351. .left_margin = 220,
  352. .right_margin = 40,
  353. .upper_margin = 21,
  354. .lower_margin = 7,
  355. .hsync_len = 60,
  356. .vsync_len = 10,
  357. .sync = FB_SYNC_EXT,
  358. .vmode = FB_VMODE_NONINTERLACED
  359. } }, {
  360. /* DLC800FIG-T-3 */
  361. .bus = 2,
  362. .addr = 0x14,
  363. .detect = NULL,
  364. .enable = enable_lvds,
  365. .pixfmt = IPU_PIX_FMT_LVDS666,
  366. .mode = {
  367. .name = "DLC800FIGT3",
  368. .refresh = 60,
  369. .xres = 1024, /* 1024x768 active pixels */
  370. .yres = 768,
  371. .pixclock = 15385, /* 64MHz */
  372. .left_margin = 220,
  373. .right_margin = 40,
  374. .upper_margin = 21,
  375. .lower_margin = 7,
  376. .hsync_len = 60,
  377. .vsync_len = 10,
  378. .sync = FB_SYNC_EXT,
  379. .vmode = FB_VMODE_NONINTERLACED
  380. } }, {
  381. .bus = 2,
  382. .addr = 0x5d,
  383. .detect = detect_i2c,
  384. .enable = enable_lvds,
  385. .pixfmt = IPU_PIX_FMT_LVDS666,
  386. .mode = {
  387. .name = "Z101WX01",
  388. .refresh = 60,
  389. .xres = 1280,
  390. .yres = 800,
  391. .pixclock = 15385, /* 64MHz */
  392. .left_margin = 220,
  393. .right_margin = 40,
  394. .upper_margin = 21,
  395. .lower_margin = 7,
  396. .hsync_len = 60,
  397. .vsync_len = 10,
  398. .sync = FB_SYNC_EXT,
  399. .vmode = FB_VMODE_NONINTERLACED
  400. }
  401. },
  402. };
  403. size_t display_count = ARRAY_SIZE(displays);
  404. static void setup_display(void)
  405. {
  406. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  407. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  408. int reg;
  409. enable_ipu_clock();
  410. imx_setup_hdmi();
  411. /* Turn on LDB0,IPU,IPU DI0 clocks */
  412. reg = __raw_readl(&mxc_ccm->CCGR3);
  413. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  414. writel(reg, &mxc_ccm->CCGR3);
  415. /* set LDB0, LDB1 clk select to 011/011 */
  416. reg = readl(&mxc_ccm->cs2cdr);
  417. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  418. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  419. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  420. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  421. writel(reg, &mxc_ccm->cs2cdr);
  422. reg = readl(&mxc_ccm->cscmr2);
  423. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  424. writel(reg, &mxc_ccm->cscmr2);
  425. reg = readl(&mxc_ccm->chsccdr);
  426. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  427. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  428. writel(reg, &mxc_ccm->chsccdr);
  429. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  430. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  431. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  432. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  433. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  434. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  435. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  436. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  437. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  438. writel(reg, &iomux->gpr[2]);
  439. reg = readl(&iomux->gpr[3]);
  440. reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
  441. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  442. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  443. writel(reg, &iomux->gpr[3]);
  444. /* LVDS Backlight GPIO on LVDS connector - output low */
  445. SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
  446. gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
  447. }
  448. #endif /* CONFIG_VIDEO_IPUV3 */
  449. /* setup board specific PMIC */
  450. int power_init_board(void)
  451. {
  452. setup_pmic();
  453. return 0;
  454. }
  455. #if defined(CONFIG_CMD_PCI)
  456. int imx6_pcie_toggle_reset(void)
  457. {
  458. if (board_type < GW_UNKNOWN) {
  459. uint pin = gpio_cfg[board_type].pcie_rst;
  460. gpio_request(pin, "pci_rst#");
  461. gpio_direction_output(pin, 0);
  462. mdelay(50);
  463. gpio_direction_output(pin, 1);
  464. }
  465. return 0;
  466. }
  467. /*
  468. * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
  469. * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
  470. * properly and assert reset for 100ms.
  471. */
  472. #define MAX_PCI_DEVS 32
  473. struct pci_dev {
  474. pci_dev_t devfn;
  475. unsigned short vendor;
  476. unsigned short device;
  477. unsigned short class;
  478. unsigned short busno; /* subbordinate busno */
  479. struct pci_dev *ppar;
  480. };
  481. struct pci_dev pci_devs[MAX_PCI_DEVS];
  482. int pci_devno;
  483. int pci_bridgeno;
  484. void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
  485. unsigned short vendor, unsigned short device,
  486. unsigned short class)
  487. {
  488. int i;
  489. u32 dw;
  490. struct pci_dev *pdev = &pci_devs[pci_devno++];
  491. debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
  492. PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
  493. /* store array of devs for later use in device-tree fixup */
  494. pdev->devfn = dev;
  495. pdev->vendor = vendor;
  496. pdev->device = device;
  497. pdev->class = class;
  498. pdev->ppar = NULL;
  499. if (class == PCI_CLASS_BRIDGE_PCI)
  500. pdev->busno = ++pci_bridgeno;
  501. else
  502. pdev->busno = 0;
  503. /* fixup RC - it should be 00:00.0 not 00:01.0 */
  504. if (PCI_BUS(dev) == 0)
  505. pdev->devfn = 0;
  506. /* find dev's parent */
  507. for (i = 0; i < pci_devno; i++) {
  508. if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
  509. pdev->ppar = &pci_devs[i];
  510. break;
  511. }
  512. }
  513. /* assert downstream PERST# */
  514. if (vendor == PCI_VENDOR_ID_PLX &&
  515. (device & 0xfff0) == 0x8600 &&
  516. PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
  517. debug("configuring PLX 860X downstream PERST#\n");
  518. pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
  519. dw |= 0xaaa8; /* GPIO1-7 outputs */
  520. pci_hose_write_config_dword(hose, dev, 0x62c, dw);
  521. pci_hose_read_config_dword(hose, dev, 0x644, &dw);
  522. dw |= 0xfe; /* GPIO1-7 output high */
  523. pci_hose_write_config_dword(hose, dev, 0x644, dw);
  524. mdelay(100);
  525. }
  526. }
  527. #endif /* CONFIG_CMD_PCI */
  528. #ifdef CONFIG_SERIAL_TAG
  529. /*
  530. * called when setting up ATAGS before booting kernel
  531. * populate serialnum from the following (in order of priority):
  532. * serial# env var
  533. * eeprom
  534. */
  535. void get_board_serial(struct tag_serialnr *serialnr)
  536. {
  537. char *serial = env_get("serial#");
  538. if (serial) {
  539. serialnr->high = 0;
  540. serialnr->low = simple_strtoul(serial, NULL, 10);
  541. } else if (ventana_info.model[0]) {
  542. serialnr->high = 0;
  543. serialnr->low = ventana_info.serial;
  544. } else {
  545. serialnr->high = 0;
  546. serialnr->low = 0;
  547. }
  548. }
  549. #endif
  550. /*
  551. * Board Support
  552. */
  553. int board_early_init_f(void)
  554. {
  555. setup_iomux_uart();
  556. #if defined(CONFIG_VIDEO_IPUV3)
  557. setup_display();
  558. #endif
  559. return 0;
  560. }
  561. int dram_init(void)
  562. {
  563. gd->ram_size = imx_ddr_size();
  564. return 0;
  565. }
  566. int board_init(void)
  567. {
  568. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  569. clrsetbits_le32(&iomuxc_regs->gpr[1],
  570. IOMUXC_GPR1_OTG_ID_MASK,
  571. IOMUXC_GPR1_OTG_ID_GPIO1);
  572. /* address of linux boot parameters */
  573. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  574. /* read Gateworks EEPROM into global struct (used later) */
  575. setup_ventana_i2c(0);
  576. board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
  577. #ifdef CONFIG_CMD_NAND
  578. if (gpio_cfg[board_type].nand)
  579. setup_gpmi_nand();
  580. #endif
  581. #ifdef CONFIG_MXC_SPI
  582. setup_spi();
  583. #endif
  584. setup_ventana_i2c(1);
  585. setup_ventana_i2c(2);
  586. #ifdef CONFIG_SATA
  587. setup_sata();
  588. #endif
  589. setup_iomux_gpio(board_type, &ventana_info);
  590. return 0;
  591. }
  592. #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
  593. /*
  594. * called during late init (after relocation and after board_init())
  595. * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
  596. * EEPROM read.
  597. */
  598. int checkboard(void)
  599. {
  600. struct ventana_board_info *info = &ventana_info;
  601. unsigned char buf[4];
  602. const char *p;
  603. int quiet; /* Quiet or minimal output mode */
  604. quiet = 0;
  605. p = env_get("quiet");
  606. if (p)
  607. quiet = simple_strtol(p, NULL, 10);
  608. else
  609. env_set("quiet", "0");
  610. puts("\nGateworks Corporation Copyright 2014\n");
  611. if (info->model[0]) {
  612. printf("Model: %s\n", info->model);
  613. printf("MFGDate: %02x-%02x-%02x%02x\n",
  614. info->mfgdate[0], info->mfgdate[1],
  615. info->mfgdate[2], info->mfgdate[3]);
  616. printf("Serial:%d\n", info->serial);
  617. } else {
  618. puts("Invalid EEPROM - board will not function fully\n");
  619. }
  620. if (quiet)
  621. return 0;
  622. /* Display GSC firmware revision/CRC/status */
  623. gsc_info(0);
  624. /* Display RTC */
  625. if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
  626. printf("RTC: %d\n",
  627. buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
  628. }
  629. return 0;
  630. }
  631. #endif
  632. #ifdef CONFIG_CMD_BMODE
  633. /*
  634. * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
  635. * see Table 8-11 and Table 5-9
  636. * BOOT_CFG1[7] = 1 (boot from NAND)
  637. * BOOT_CFG1[5] = 0 - raw NAND
  638. * BOOT_CFG1[4] = 0 - default pad settings
  639. * BOOT_CFG1[3:2] = 00 - devices = 1
  640. * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
  641. * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
  642. * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
  643. * BOOT_CFG2[0] = 0 - Reset time 12ms
  644. */
  645. static const struct boot_mode board_boot_modes[] = {
  646. /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
  647. { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
  648. { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
  649. { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
  650. { NULL, 0 },
  651. };
  652. #endif
  653. /* late init */
  654. int misc_init_r(void)
  655. {
  656. struct ventana_board_info *info = &ventana_info;
  657. char buf[256];
  658. int i;
  659. /* set env vars based on EEPROM data */
  660. if (ventana_info.model[0]) {
  661. char str[16], fdt[36];
  662. char *p;
  663. const char *cputype = "";
  664. /*
  665. * FDT name will be prefixed with CPU type. Three versions
  666. * will be created each increasingly generic and bootloader
  667. * env scripts will try loading each from most specific to
  668. * least.
  669. */
  670. if (is_cpu_type(MXC_CPU_MX6Q) ||
  671. is_cpu_type(MXC_CPU_MX6D))
  672. cputype = "imx6q";
  673. else if (is_cpu_type(MXC_CPU_MX6DL) ||
  674. is_cpu_type(MXC_CPU_MX6SOLO))
  675. cputype = "imx6dl";
  676. env_set("soctype", cputype);
  677. if (8 << (ventana_info.nand_flash_size-1) >= 2048)
  678. env_set("flash_layout", "large");
  679. else
  680. env_set("flash_layout", "normal");
  681. memset(str, 0, sizeof(str));
  682. for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
  683. str[i] = tolower(info->model[i]);
  684. env_set("model", str);
  685. if (!env_get("fdt_file")) {
  686. sprintf(fdt, "%s-%s.dtb", cputype, str);
  687. env_set("fdt_file", fdt);
  688. }
  689. p = strchr(str, '-');
  690. if (p) {
  691. *p++ = 0;
  692. env_set("model_base", str);
  693. sprintf(fdt, "%s-%s.dtb", cputype, str);
  694. env_set("fdt_file1", fdt);
  695. if (board_type != GW551x &&
  696. board_type != GW552x &&
  697. board_type != GW553x &&
  698. board_type != GW560x)
  699. str[4] = 'x';
  700. str[5] = 'x';
  701. str[6] = 0;
  702. sprintf(fdt, "%s-%s.dtb", cputype, str);
  703. env_set("fdt_file2", fdt);
  704. }
  705. /* initialize env from EEPROM */
  706. if (test_bit(EECONFIG_ETH0, info->config) &&
  707. !env_get("ethaddr")) {
  708. eth_env_set_enetaddr("ethaddr", info->mac0);
  709. }
  710. if (test_bit(EECONFIG_ETH1, info->config) &&
  711. !env_get("eth1addr")) {
  712. eth_env_set_enetaddr("eth1addr", info->mac1);
  713. }
  714. /* board serial-number */
  715. sprintf(str, "%6d", info->serial);
  716. env_set("serial#", str);
  717. /* memory MB */
  718. sprintf(str, "%d", (int) (gd->ram_size >> 20));
  719. env_set("mem_mb", str);
  720. }
  721. /* Set a non-initialized hwconfig based on board configuration */
  722. if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
  723. buf[0] = 0;
  724. if (gpio_cfg[board_type].rs232_en)
  725. strcat(buf, "rs232;");
  726. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  727. char buf1[32];
  728. sprintf(buf1, "dio%d:mode=gpio;", i);
  729. if (strlen(buf) + strlen(buf1) < sizeof(buf))
  730. strcat(buf, buf1);
  731. }
  732. env_set("hwconfig", buf);
  733. }
  734. /* setup baseboard specific GPIO based on board and env */
  735. setup_board_gpio(board_type, info);
  736. #ifdef CONFIG_CMD_BMODE
  737. add_board_boot_modes(board_boot_modes);
  738. #endif
  739. /* disable boot watchdog */
  740. gsc_boot_wd_disable();
  741. return 0;
  742. }
  743. #ifdef CONFIG_OF_BOARD_SETUP
  744. static int ft_sethdmiinfmt(void *blob, char *mode)
  745. {
  746. int off;
  747. if (!mode)
  748. return -EINVAL;
  749. off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
  750. if (off < 0)
  751. return off;
  752. if (0 == strcasecmp(mode, "yuv422bt656")) {
  753. u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
  754. 0x00, 0x00, 0x00 };
  755. mode = "422_ccir";
  756. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  757. fdt_setprop_u32(blob, off, "vidout_trc", 1);
  758. fdt_setprop_u32(blob, off, "vidout_blc", 1);
  759. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  760. printf(" set HDMI input mode to %s\n", mode);
  761. } else if (0 == strcasecmp(mode, "yuv422smp")) {
  762. u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
  763. 0x82, 0x81, 0x00 };
  764. mode = "422_smp";
  765. fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
  766. fdt_setprop_u32(blob, off, "vidout_trc", 0);
  767. fdt_setprop_u32(blob, off, "vidout_blc", 0);
  768. fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
  769. printf(" set HDMI input mode to %s\n", mode);
  770. } else {
  771. return -EINVAL;
  772. }
  773. return 0;
  774. }
  775. #if defined(CONFIG_CMD_PCI)
  776. #define PCI_ID(x) ( \
  777. (PCI_BUS(x->devfn)<<16)| \
  778. (PCI_DEV(x->devfn)<<11)| \
  779. (PCI_FUNC(x->devfn)<<8) \
  780. )
  781. int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
  782. {
  783. uint32_t reg[5];
  784. char node[32];
  785. int np;
  786. sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
  787. PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
  788. np = fdt_subnode_offset(blob, par, node);
  789. if (np >= 0)
  790. return np;
  791. np = fdt_add_subnode(blob, par, node);
  792. if (np < 0) {
  793. printf(" %s failed: no space\n", __func__);
  794. return np;
  795. }
  796. memset(reg, 0, sizeof(reg));
  797. reg[0] = cpu_to_fdt32(PCI_ID(dev));
  798. fdt_setprop(blob, np, "reg", reg, sizeof(reg));
  799. return np;
  800. }
  801. /* build a path of nested PCI devs for all bridges passed through */
  802. int fdt_add_pci_path(void *blob, struct pci_dev *dev)
  803. {
  804. struct pci_dev *bridges[MAX_PCI_DEVS];
  805. int k, np;
  806. /* build list of parents */
  807. np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  808. if (np < 0)
  809. return np;
  810. k = 0;
  811. while (dev) {
  812. bridges[k++] = dev;
  813. dev = dev->ppar;
  814. };
  815. /* now add them the to DT in reverse order */
  816. while (k--) {
  817. np = fdt_add_pci_node(blob, np, bridges[k]);
  818. if (np < 0)
  819. break;
  820. }
  821. return np;
  822. }
  823. /*
  824. * The GW16082 has a hardware errata errata such that it's
  825. * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
  826. * of this normal PCI interrupt swizzling will not work so we will
  827. * provide an irq-map via device-tree.
  828. */
  829. int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
  830. {
  831. int len;
  832. int host;
  833. uint32_t imap_new[8*4*4];
  834. const uint32_t *imap;
  835. uint32_t irq[4];
  836. uint32_t reg[4];
  837. int i;
  838. /* build irq-map based on host controllers map */
  839. host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
  840. if (host < 0) {
  841. printf(" %s failed: missing host\n", __func__);
  842. return host;
  843. }
  844. /* use interrupt data from root complex's node */
  845. imap = fdt_getprop(blob, host, "interrupt-map", &len);
  846. if (!imap || len != 128) {
  847. printf(" %s failed: invalid interrupt-map\n",
  848. __func__);
  849. return -FDT_ERR_NOTFOUND;
  850. }
  851. /* obtain irq's of host controller in pin order */
  852. for (i = 0; i < 4; i++)
  853. irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
  854. /*
  855. * determine number of swizzles necessary:
  856. * For each bridge we pass through we need to swizzle
  857. * the number of the slot we are on.
  858. */
  859. struct pci_dev *d;
  860. int b;
  861. b = 0;
  862. d = dev->ppar;
  863. while(d && d->ppar) {
  864. b += PCI_DEV(d->devfn);
  865. d = d->ppar;
  866. }
  867. /* create new irq mappings for slots12-15
  868. * <skt> <idsel> <slot> <skt-inta> <skt-intb>
  869. * J3 AD28 12 INTD INTA
  870. * J4 AD29 13 INTC INTD
  871. * J5 AD30 14 INTB INTC
  872. * J2 AD31 15 INTA INTB
  873. */
  874. for (i = 0; i < 4; i++) {
  875. /* addr matches bus:dev:func */
  876. u32 addr = dev->busno << 16 | (12+i) << 11;
  877. /* default cells from root complex */
  878. memcpy(&imap_new[i*32], imap, 128);
  879. /* first cell is PCI device address (BDF) */
  880. imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
  881. imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
  882. imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
  883. imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
  884. /* third cell is pin */
  885. imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
  886. imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
  887. imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
  888. imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
  889. /* sixth cell is relative interrupt */
  890. imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
  891. imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
  892. imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
  893. imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
  894. }
  895. fdt_setprop(blob, np, "interrupt-map", imap_new,
  896. sizeof(imap_new));
  897. reg[0] = cpu_to_fdt32(0xfff00);
  898. reg[1] = 0;
  899. reg[2] = 0;
  900. reg[3] = cpu_to_fdt32(0x7);
  901. fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
  902. fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
  903. fdt_setprop_string(blob, np, "device_type", "pci");
  904. fdt_setprop_cell(blob, np, "#address-cells", 3);
  905. fdt_setprop_cell(blob, np, "#size-cells", 2);
  906. printf(" Added custom interrupt-map for GW16082\n");
  907. return 0;
  908. }
  909. /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
  910. int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
  911. {
  912. char *tmp, *end;
  913. char mac[16];
  914. unsigned char mac_addr[6];
  915. int j;
  916. sprintf(mac, "eth1addr");
  917. tmp = env_get(mac);
  918. if (tmp) {
  919. for (j = 0; j < 6; j++) {
  920. mac_addr[j] = tmp ?
  921. simple_strtoul(tmp, &end,16) : 0;
  922. if (tmp)
  923. tmp = (*end) ? end+1 : end;
  924. }
  925. fdt_setprop(blob, np, "local-mac-address", mac_addr,
  926. sizeof(mac_addr));
  927. printf(" Added mac addr for eth1\n");
  928. return 0;
  929. }
  930. return -1;
  931. }
  932. /*
  933. * PCI DT nodes must be nested therefore if we need to apply a DT fixup
  934. * we will walk the PCI bus and add bridge nodes up to the device receiving
  935. * the fixup.
  936. */
  937. void ft_board_pci_fixup(void *blob, bd_t *bd)
  938. {
  939. int i, np;
  940. struct pci_dev *dev;
  941. for (i = 0; i < pci_devno; i++) {
  942. dev = &pci_devs[i];
  943. /*
  944. * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
  945. * an EEPROM at i2c1-0x50.
  946. */
  947. if ((dev->vendor == PCI_VENDOR_ID_TI) &&
  948. (dev->device == 0x8240) &&
  949. (i2c_set_bus_num(1) == 0) &&
  950. (i2c_probe(0x50) == 0))
  951. {
  952. np = fdt_add_pci_path(blob, dev);
  953. if (np > 0)
  954. fdt_fixup_gw16082(blob, np, dev);
  955. }
  956. /* ethernet1 mac address */
  957. else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
  958. (dev->device == 0x4380))
  959. {
  960. np = fdt_add_pci_path(blob, dev);
  961. if (np > 0)
  962. fdt_fixup_sky2(blob, np, dev);
  963. }
  964. }
  965. }
  966. #endif /* if defined(CONFIG_CMD_PCI) */
  967. void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
  968. {
  969. int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
  970. if (off) {
  971. fdt_delprop(blob, off, "ext-reset-output");
  972. fdt_delprop(blob, off, "fsl,ext-reset-output");
  973. }
  974. }
  975. /*
  976. * called prior to booting kernel or by 'fdt boardsetup' command
  977. *
  978. * unless 'fdt_noauto' env var is set we will update the following in the DTB:
  979. * - mtd partitions based on mtdparts/mtdids env
  980. * - system-serial (board serial num from EEPROM)
  981. * - board (full model from EEPROM)
  982. * - peripherals removed from DTB if not loaded on board (per EEPROM config)
  983. */
  984. #define WDOG1_ADDR 0x20bc000
  985. #define WDOG2_ADDR 0x20c0000
  986. #define GPIO3_ADDR 0x20a4000
  987. #define USDHC3_ADDR 0x2198000
  988. #define PWM0_ADDR 0x2080000
  989. int ft_board_setup(void *blob, bd_t *bd)
  990. {
  991. struct ventana_board_info *info = &ventana_info;
  992. struct ventana_eeprom_config *cfg;
  993. static const struct node_info nodes[] = {
  994. { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
  995. { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
  996. };
  997. const char *model = env_get("model");
  998. const char *display = env_get("display");
  999. int i;
  1000. char rev = 0;
  1001. /* determine board revision */
  1002. for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
  1003. if (ventana_info.model[i] >= 'A') {
  1004. rev = ventana_info.model[i];
  1005. break;
  1006. }
  1007. }
  1008. if (env_get("fdt_noauto")) {
  1009. puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
  1010. return 0;
  1011. }
  1012. if (test_bit(EECONFIG_NAND, info->config)) {
  1013. /* Update partition nodes using info from mtdparts env var */
  1014. puts(" Updating MTD partitions...\n");
  1015. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  1016. }
  1017. /* Update display timings from display env var */
  1018. if (display) {
  1019. if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
  1020. display) >= 0)
  1021. printf(" Set display timings for %s...\n", display);
  1022. }
  1023. printf(" Adjusting FDT per EEPROM for %s...\n", model);
  1024. /* board serial number */
  1025. fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
  1026. strlen(env_get("serial#")) + 1);
  1027. /* board (model contains model from device-tree) */
  1028. fdt_setprop(blob, 0, "board", info->model,
  1029. strlen((const char *)info->model) + 1);
  1030. /* set desired digital video capture format */
  1031. ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
  1032. /*
  1033. * Board model specific fixups
  1034. */
  1035. switch (board_type) {
  1036. case GW51xx:
  1037. /*
  1038. * disable wdog node for GW51xx-A/B to work around
  1039. * errata causing wdog timer to be unreliable.
  1040. */
  1041. if (rev >= 'A' && rev < 'C') {
  1042. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
  1043. WDOG1_ADDR);
  1044. if (i)
  1045. fdt_status_disabled(blob, i);
  1046. }
  1047. /* GW51xx-E adds WDOG1_B external reset */
  1048. if (rev < 'E')
  1049. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1050. break;
  1051. case GW52xx:
  1052. /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
  1053. if (info->model[4] == '2') {
  1054. u32 handle = 0;
  1055. u32 *range = NULL;
  1056. i = fdt_node_offset_by_compatible(blob, -1,
  1057. "fsl,imx6q-pcie");
  1058. if (i)
  1059. range = (u32 *)fdt_getprop(blob, i,
  1060. "reset-gpio", NULL);
  1061. if (range) {
  1062. i = fdt_node_offset_by_compat_reg(blob,
  1063. "fsl,imx6q-gpio", GPIO3_ADDR);
  1064. if (i)
  1065. handle = fdt_get_phandle(blob, i);
  1066. if (handle) {
  1067. range[0] = cpu_to_fdt32(handle);
  1068. range[1] = cpu_to_fdt32(23);
  1069. }
  1070. }
  1071. /* these have broken usd_vsel */
  1072. if (strstr((const char *)info->model, "SP318-B") ||
  1073. strstr((const char *)info->model, "SP331-B"))
  1074. gpio_cfg[board_type].usd_vsel = 0;
  1075. /* GW522x-B adds WDOG1_B external reset */
  1076. if (rev < 'B')
  1077. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1078. }
  1079. /* GW520x-E adds WDOG1_B external reset */
  1080. else if (info->model[4] == '0' && rev < 'E')
  1081. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1082. break;
  1083. case GW53xx:
  1084. /* GW53xx-E adds WDOG1_B external reset */
  1085. if (rev < 'E')
  1086. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1087. break;
  1088. case GW54xx:
  1089. /*
  1090. * disable serial2 node for GW54xx for compatibility with older
  1091. * 3.10.x kernel that improperly had this node enabled in the DT
  1092. */
  1093. fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
  1094. 0);
  1095. /* GW54xx-E adds WDOG2_B external reset */
  1096. if (rev < 'E')
  1097. ft_board_wdog_fixup(blob, WDOG2_ADDR);
  1098. break;
  1099. case GW551x:
  1100. /*
  1101. * isolate CSI0_DATA_EN for GW551x-A to work around errata
  1102. * causing non functional digital video in (it is not hooked up)
  1103. */
  1104. if (rev == 'A') {
  1105. u32 *range = NULL;
  1106. int len;
  1107. const u32 *handle = NULL;
  1108. i = fdt_node_offset_by_compatible(blob, -1,
  1109. "fsl,imx-tda1997x-video");
  1110. if (i)
  1111. handle = fdt_getprop(blob, i, "pinctrl-0",
  1112. NULL);
  1113. if (handle)
  1114. i = fdt_node_offset_by_phandle(blob,
  1115. fdt32_to_cpu(*handle));
  1116. if (i)
  1117. range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
  1118. &len);
  1119. if (range) {
  1120. len /= sizeof(u32);
  1121. for (i = 0; i < len; i += 6) {
  1122. u32 mux_reg = fdt32_to_cpu(range[i+0]);
  1123. u32 conf_reg = fdt32_to_cpu(range[i+1]);
  1124. /* mux PAD_CSI0_DATA_EN to GPIO */
  1125. if (is_cpu_type(MXC_CPU_MX6Q) &&
  1126. mux_reg == 0x260 &&
  1127. conf_reg == 0x630)
  1128. range[i+3] = cpu_to_fdt32(0x5);
  1129. else if (!is_cpu_type(MXC_CPU_MX6Q) &&
  1130. mux_reg == 0x08c &&
  1131. conf_reg == 0x3a0)
  1132. range[i+3] = cpu_to_fdt32(0x5);
  1133. }
  1134. fdt_setprop_inplace(blob, i, "fsl,pins", range,
  1135. len);
  1136. }
  1137. /* set BT656 video format */
  1138. ft_sethdmiinfmt(blob, "yuv422bt656");
  1139. }
  1140. /* GW551x-C adds WDOG1_B external reset */
  1141. if (rev < 'C')
  1142. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1143. break;
  1144. case GW5901:
  1145. case GW5902:
  1146. /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
  1147. if (rev < 'B')
  1148. ft_board_wdog_fixup(blob, WDOG1_ADDR);
  1149. break;
  1150. }
  1151. /* Configure DIO */
  1152. for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
  1153. struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
  1154. char arg[10];
  1155. sprintf(arg, "dio%d", i);
  1156. if (!hwconfig(arg))
  1157. continue;
  1158. if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
  1159. {
  1160. phys_addr_t addr;
  1161. int off;
  1162. printf(" Enabling pwm%d for DIO%d\n",
  1163. cfg->pwm_param, i);
  1164. addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
  1165. off = fdt_node_offset_by_compat_reg(blob,
  1166. "fsl,imx6q-pwm",
  1167. addr);
  1168. if (off)
  1169. fdt_status_okay(blob, off);
  1170. }
  1171. }
  1172. /* remove no-1-8-v if UHS-I support is present */
  1173. if (gpio_cfg[board_type].usd_vsel) {
  1174. debug("Enabling UHS-I support\n");
  1175. i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
  1176. USDHC3_ADDR);
  1177. if (i)
  1178. fdt_delprop(blob, i, "no-1-8-v");
  1179. }
  1180. #if defined(CONFIG_CMD_PCI)
  1181. if (!env_get("nopcifixup"))
  1182. ft_board_pci_fixup(blob, bd);
  1183. #endif
  1184. /*
  1185. * Peripheral Config:
  1186. * remove nodes by alias path if EEPROM config tells us the
  1187. * peripheral is not loaded on the board.
  1188. */
  1189. if (env_get("fdt_noconfig")) {
  1190. puts(" Skiping periperhal config (fdt_noconfig defined)\n");
  1191. return 0;
  1192. }
  1193. cfg = econfig;
  1194. while (cfg->name) {
  1195. if (!test_bit(cfg->bit, info->config)) {
  1196. fdt_del_node_and_alias(blob, cfg->dtalias ?
  1197. cfg->dtalias : cfg->name);
  1198. }
  1199. cfg++;
  1200. }
  1201. return 0;
  1202. }
  1203. #endif /* CONFIG_OF_BOARD_SETUP */
  1204. static struct mxc_serial_platdata ventana_mxc_serial_plat = {
  1205. .reg = (struct mxc_uart *)UART2_BASE,
  1206. };
  1207. U_BOOT_DEVICE(ventana_serial) = {
  1208. .name = "serial_mxc",
  1209. .platdata = &ventana_mxc_serial_plat,
  1210. };