mx7dsabresd.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <asm/arch/clock.h>
  6. #include <asm/arch/imx-regs.h>
  7. #include <asm/arch/mx7-pins.h>
  8. #include <asm/arch/sys_proto.h>
  9. #include <asm/gpio.h>
  10. #include <asm/mach-imx/iomux-v3.h>
  11. #include <asm/io.h>
  12. #include <linux/sizes.h>
  13. #include <common.h>
  14. #include <fsl_esdhc_imx.h>
  15. #include <mmc.h>
  16. #include <miiphy.h>
  17. #include <netdev.h>
  18. #include <power/pmic.h>
  19. #include <power/pfuze3000_pmic.h>
  20. #include "../common/pfuze.h"
  21. #include <i2c.h>
  22. #include <asm/mach-imx/mxc_i2c.h>
  23. #include <asm/arch/crm_regs.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
  26. PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  27. #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  28. #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM)
  29. #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  30. #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
  31. PAD_CTL_DSE_3P3V_49OHM)
  32. #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  33. #define SPI_PAD_CTRL \
  34. (PAD_CTL_HYS | PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST)
  35. #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
  36. #ifdef CONFIG_MXC_SPI
  37. static iomux_v3_cfg_t const ecspi3_pads[] = {
  38. MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  39. MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  40. MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  41. MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  42. };
  43. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  44. {
  45. return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(6, 22)) : -1;
  46. }
  47. static void setup_spi(void)
  48. {
  49. imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads));
  50. }
  51. #endif
  52. int dram_init(void)
  53. {
  54. gd->ram_size = PHYS_SDRAM_SIZE;
  55. return 0;
  56. }
  57. static iomux_v3_cfg_t const wdog_pads[] = {
  58. MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  59. };
  60. static iomux_v3_cfg_t const uart1_pads[] = {
  61. MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  62. MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  63. };
  64. #ifdef CONFIG_NAND_MXS
  65. static iomux_v3_cfg_t const gpmi_pads[] = {
  66. MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  67. MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  68. MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  69. MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  70. MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  71. MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  72. MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  73. MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  74. MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  75. MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  76. MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  77. MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  78. MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  79. MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  80. MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  81. MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  82. MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  83. MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
  84. MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
  85. };
  86. static void setup_gpmi_nand(void)
  87. {
  88. imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  89. /* NAND_USDHC_BUS_CLK is set in rom */
  90. set_clk_nand();
  91. }
  92. #endif
  93. #ifdef CONFIG_VIDEO_MXS
  94. static iomux_v3_cfg_t const lcd_pads[] = {
  95. MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  96. MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  97. MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  98. MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  99. MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  100. MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  101. MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  102. MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  103. MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  104. MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  105. MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  106. MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  107. MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  108. MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  109. MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  110. MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  111. MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  112. MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  113. MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  114. MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  115. MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  116. MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  117. MX7D_PAD_LCD_DATA18__LCD_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  118. MX7D_PAD_LCD_DATA19__LCD_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  119. MX7D_PAD_LCD_DATA20__LCD_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  120. MX7D_PAD_LCD_DATA21__LCD_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  121. MX7D_PAD_LCD_DATA22__LCD_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  122. MX7D_PAD_LCD_DATA23__LCD_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  123. MX7D_PAD_LCD_RESET__GPIO3_IO4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  124. };
  125. static iomux_v3_cfg_t const pwm_pads[] = {
  126. /* Use GPIO for Brightness adjustment, duty cycle = period */
  127. MX7D_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
  128. };
  129. static int setup_lcd(void)
  130. {
  131. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  132. imx_iomux_v3_setup_multiple_pads(pwm_pads, ARRAY_SIZE(pwm_pads));
  133. /* Reset LCD */
  134. gpio_request(IMX_GPIO_NR(3, 4), "lcd reset");
  135. gpio_direction_output(IMX_GPIO_NR(3, 4) , 0);
  136. udelay(500);
  137. gpio_direction_output(IMX_GPIO_NR(3, 4) , 1);
  138. /* Set Brightness to high */
  139. gpio_request(IMX_GPIO_NR(1, 1), "lcd backlight");
  140. gpio_direction_output(IMX_GPIO_NR(1, 1) , 1);
  141. return 0;
  142. }
  143. #endif
  144. #ifdef CONFIG_FEC_MXC
  145. static iomux_v3_cfg_t const fec1_pads[] = {
  146. MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  147. MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  148. MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  149. MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  150. MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  151. MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  152. MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  153. MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  154. MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  155. MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  156. MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  157. MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  158. MX7D_PAD_GPIO1_IO10__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
  159. MX7D_PAD_GPIO1_IO11__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
  160. };
  161. static void setup_iomux_fec(void)
  162. {
  163. imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
  164. }
  165. #endif
  166. static void setup_iomux_uart(void)
  167. {
  168. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  169. }
  170. int board_mmc_get_env_dev(int devno)
  171. {
  172. if (devno == 2)
  173. devno--;
  174. return devno;
  175. }
  176. int mmc_map_to_kernel_blk(int dev_no)
  177. {
  178. if (dev_no == 1)
  179. dev_no++;
  180. return dev_no;
  181. }
  182. #ifdef CONFIG_FEC_MXC
  183. int board_eth_init(bd_t *bis)
  184. {
  185. int ret;
  186. unsigned int gpio;
  187. ret = gpio_lookup_name("gpio_spi@0_5", NULL, NULL, &gpio);
  188. if (ret) {
  189. printf("GPIO: 'gpio_spi@0_5' not found\n");
  190. return -ENODEV;
  191. }
  192. ret = gpio_request(gpio, "fec_rst");
  193. if (ret && ret != -EBUSY) {
  194. printf("gpio: requesting pin %u failed\n", gpio);
  195. return ret;
  196. }
  197. gpio_direction_output(gpio, 0);
  198. udelay(500);
  199. gpio_direction_output(gpio, 1);
  200. setup_iomux_fec();
  201. ret = fecmxc_initialize_multi(bis, 0,
  202. CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  203. if (ret)
  204. printf("FEC1 MXC: %s:failed\n", __func__);
  205. return ret;
  206. }
  207. static int setup_fec(void)
  208. {
  209. struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
  210. = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
  211. /* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/
  212. clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
  213. (IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |
  214. IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK), 0);
  215. return set_clk_enet(ENET_125MHZ);
  216. }
  217. int board_phy_config(struct phy_device *phydev)
  218. {
  219. /* enable rgmii rxc skew and phy mode select to RGMII copper */
  220. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x21);
  221. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x7ea8);
  222. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x2f);
  223. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x71b7);
  224. if (phydev->drv->config)
  225. phydev->drv->config(phydev);
  226. return 0;
  227. }
  228. #endif
  229. #ifdef CONFIG_FSL_QSPI
  230. int board_qspi_init(void)
  231. {
  232. /* Set the clock */
  233. set_clk_qspi();
  234. return 0;
  235. }
  236. #endif
  237. int board_early_init_f(void)
  238. {
  239. setup_iomux_uart();
  240. return 0;
  241. }
  242. int board_init(void)
  243. {
  244. /* address of boot parameters */
  245. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  246. #ifdef CONFIG_FEC_MXC
  247. setup_fec();
  248. #endif
  249. #ifdef CONFIG_NAND_MXS
  250. setup_gpmi_nand();
  251. #endif
  252. #ifdef CONFIG_VIDEO_MXS
  253. setup_lcd();
  254. #endif
  255. #ifdef CONFIG_FSL_QSPI
  256. board_qspi_init();
  257. #endif
  258. #ifdef CONFIG_MXC_SPI
  259. setup_spi();
  260. #endif
  261. return 0;
  262. }
  263. #ifdef CONFIG_DM_PMIC
  264. int power_init_board(void)
  265. {
  266. struct udevice *dev;
  267. int ret, dev_id, rev_id;
  268. ret = pmic_get("pfuze3000", &dev);
  269. if (ret == -ENODEV)
  270. return 0;
  271. if (ret != 0)
  272. return ret;
  273. dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  274. rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  275. printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  276. pmic_clrsetbits(dev, PFUZE3000_LDOGCTL, 0, 1);
  277. /*
  278. * Set the voltage of VLDO4 output to 2.8V which feeds
  279. * the MIPI DSI and MIPI CSI inputs.
  280. */
  281. pmic_clrsetbits(dev, PFUZE3000_VLD4CTL, 0xF, 0xA);
  282. return 0;
  283. }
  284. #endif
  285. int board_late_init(void)
  286. {
  287. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  288. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  289. set_wdog_reset(wdog);
  290. /*
  291. * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4),
  292. * since we use PMIC_PWRON to reset the board.
  293. */
  294. clrsetbits_le16(&wdog->wcr, 0, 0x10);
  295. return 0;
  296. }
  297. int checkboard(void)
  298. {
  299. char *mode;
  300. if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
  301. mode = "secure";
  302. else
  303. mode = "non-secure";
  304. printf("Board: i.MX7D SABRESD in %s mode\n", mode);
  305. return 0;
  306. }