mx6ul_14x14_evk.c 20 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015 Freescale Semiconductor, Inc.
  4. */
  5. #include <asm/arch/clock.h>
  6. #include <asm/arch/iomux.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/crm_regs.h>
  9. #include <asm/arch/mx6ul_pins.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/gpio.h>
  13. #include <asm/mach-imx/iomux-v3.h>
  14. #include <asm/mach-imx/boot_mode.h>
  15. #include <asm/mach-imx/mxc_i2c.h>
  16. #include <asm/io.h>
  17. #include <common.h>
  18. #include <fsl_esdhc_imx.h>
  19. #include <i2c.h>
  20. #include <miiphy.h>
  21. #include <linux/sizes.h>
  22. #include <mmc.h>
  23. #include <netdev.h>
  24. #include <power/pmic.h>
  25. #include <power/pfuze3000_pmic.h>
  26. #include "../common/pfuze.h"
  27. #include <usb.h>
  28. #include <usb/ehci-ci.h>
  29. DECLARE_GLOBAL_DATA_PTR;
  30. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  31. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  32. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  34. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  35. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  36. #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  37. PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
  38. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  39. #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  40. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  41. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  42. PAD_CTL_ODE)
  43. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  44. PAD_CTL_SPEED_HIGH | \
  45. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  46. #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  47. PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  48. #define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  49. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
  50. #define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  51. #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  52. PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  53. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  54. #ifdef CONFIG_DM_PMIC
  55. int power_init_board(void)
  56. {
  57. struct udevice *dev;
  58. int ret, dev_id, rev_id;
  59. unsigned int reg;
  60. ret = pmic_get("pfuze3000", &dev);
  61. if (ret == -ENODEV)
  62. return 0;
  63. if (ret != 0)
  64. return ret;
  65. dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
  66. rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
  67. printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  68. /* disable Low Power Mode during standby mode */
  69. reg = pmic_reg_read(dev, PFUZE3000_LDOGCTL);
  70. reg |= 0x1;
  71. pmic_reg_write(dev, PFUZE3000_LDOGCTL, reg);
  72. /* SW1B step ramp up time from 2us to 4us/25mV */
  73. pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
  74. /* SW1B mode to APS/PFM */
  75. pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
  76. /* SW1B standby voltage set to 0.975V */
  77. pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
  78. return 0;
  79. }
  80. #endif
  81. int dram_init(void)
  82. {
  83. gd->ram_size = imx_ddr_size();
  84. return 0;
  85. }
  86. static iomux_v3_cfg_t const uart1_pads[] = {
  87. MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  88. MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  89. };
  90. #ifndef CONFIG_SPL_BUILD
  91. static iomux_v3_cfg_t const usdhc1_pads[] = {
  92. MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93. MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  94. MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95. MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96. MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97. MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98. /* VSELECT */
  99. MX6_PAD_GPIO1_IO05__USDHC1_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  100. /* CD */
  101. MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  102. /* RST_B */
  103. MX6_PAD_GPIO1_IO09__GPIO1_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  104. };
  105. #endif
  106. /*
  107. * mx6ul_14x14_evk board default supports sd card. If want to use
  108. * EMMC, need to do board rework for sd2.
  109. * Introduce CONFIG_MX6UL_14X14_EVK_EMMC_REWORK, if sd2 reworked to support
  110. * emmc, need to define this macro.
  111. */
  112. #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
  113. static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
  114. MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  115. MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  116. MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118. MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  119. MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  120. MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  121. MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  122. MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123. MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124. /*
  125. * RST_B
  126. */
  127. MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  128. };
  129. #else
  130. static iomux_v3_cfg_t const usdhc2_pads[] = {
  131. MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132. MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  133. MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  134. MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  135. MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  136. MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  137. };
  138. /*
  139. * The evk board uses DAT3 to detect CD card plugin,
  140. * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
  141. */
  142. static iomux_v3_cfg_t const usdhc2_cd_pad =
  143. MX6_PAD_NAND_DATA03__GPIO4_IO05 | MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
  144. static iomux_v3_cfg_t const usdhc2_dat3_pad =
  145. MX6_PAD_NAND_DATA03__USDHC2_DATA3 |
  146. MUX_PAD_CTRL(USDHC_DAT3_CD_PAD_CTRL);
  147. #endif
  148. static void setup_iomux_uart(void)
  149. {
  150. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  151. }
  152. #ifdef CONFIG_FSL_QSPI
  153. static int board_qspi_init(void)
  154. {
  155. /* Set the clock */
  156. enable_qspi_clk(0);
  157. return 0;
  158. }
  159. #endif
  160. #ifdef CONFIG_FSL_ESDHC_IMX
  161. static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  162. {USDHC1_BASE_ADDR, 0, 4},
  163. #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
  164. {USDHC2_BASE_ADDR, 0, 8},
  165. #else
  166. {USDHC2_BASE_ADDR, 0, 4},
  167. #endif
  168. };
  169. #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
  170. #define USDHC1_PWR_GPIO IMX_GPIO_NR(1, 9)
  171. #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 5)
  172. #define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
  173. int board_mmc_getcd(struct mmc *mmc)
  174. {
  175. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  176. int ret = 0;
  177. switch (cfg->esdhc_base) {
  178. case USDHC1_BASE_ADDR:
  179. ret = !gpio_get_value(USDHC1_CD_GPIO);
  180. break;
  181. case USDHC2_BASE_ADDR:
  182. #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
  183. ret = 1;
  184. #else
  185. imx_iomux_v3_setup_pad(usdhc2_cd_pad);
  186. gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
  187. gpio_direction_input(USDHC2_CD_GPIO);
  188. /*
  189. * Since it is the DAT3 pin, this pin is pulled to
  190. * low voltage if no card
  191. */
  192. ret = gpio_get_value(USDHC2_CD_GPIO);
  193. imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
  194. #endif
  195. break;
  196. }
  197. return ret;
  198. }
  199. int board_mmc_init(bd_t *bis)
  200. {
  201. #ifdef CONFIG_SPL_BUILD
  202. #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
  203. imx_iomux_v3_setup_multiple_pads(usdhc2_emmc_pads,
  204. ARRAY_SIZE(usdhc2_emmc_pads));
  205. #else
  206. imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  207. #endif
  208. gpio_direction_output(USDHC2_PWR_GPIO, 0);
  209. udelay(500);
  210. gpio_direction_output(USDHC2_PWR_GPIO, 1);
  211. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  212. return fsl_esdhc_initialize(bis, &usdhc_cfg[1]);
  213. #else
  214. int i, ret;
  215. /*
  216. * According to the board_mmc_init() the following map is done:
  217. * (U-Boot device node) (Physical Port)
  218. * mmc0 USDHC1
  219. * mmc1 USDHC2
  220. */
  221. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  222. switch (i) {
  223. case 0:
  224. imx_iomux_v3_setup_multiple_pads(
  225. usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  226. gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
  227. gpio_direction_input(USDHC1_CD_GPIO);
  228. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  229. gpio_direction_output(USDHC1_PWR_GPIO, 0);
  230. udelay(500);
  231. gpio_direction_output(USDHC1_PWR_GPIO, 1);
  232. break;
  233. case 1:
  234. #if defined(CONFIG_MX6UL_14X14_EVK_EMMC_REWORK)
  235. imx_iomux_v3_setup_multiple_pads(
  236. usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
  237. #else
  238. imx_iomux_v3_setup_multiple_pads(
  239. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  240. #endif
  241. gpio_request(USDHC2_PWR_GPIO, "usdhc2 pwr");
  242. gpio_direction_output(USDHC2_PWR_GPIO, 0);
  243. udelay(500);
  244. gpio_direction_output(USDHC2_PWR_GPIO, 1);
  245. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  246. break;
  247. default:
  248. printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n", i + 1);
  249. return -EINVAL;
  250. }
  251. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  252. if (ret) {
  253. printf("Warning: failed to initialize mmc dev %d\n", i);
  254. return ret;
  255. }
  256. }
  257. #endif
  258. return 0;
  259. }
  260. #endif
  261. #ifdef CONFIG_USB_EHCI_MX6
  262. #ifndef CONFIG_DM_USB
  263. #define USB_OTHERREGS_OFFSET 0x800
  264. #define UCTRL_PWR_POL (1 << 9)
  265. static iomux_v3_cfg_t const usb_otg_pads[] = {
  266. MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
  267. };
  268. /* At default the 3v3 enables the MIC2026 for VBUS power */
  269. static void setup_usb(void)
  270. {
  271. imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  272. ARRAY_SIZE(usb_otg_pads));
  273. }
  274. int board_usb_phy_mode(int port)
  275. {
  276. if (port == 1)
  277. return USB_INIT_HOST;
  278. else
  279. return usb_phy_mode(port);
  280. }
  281. int board_ehci_hcd_init(int port)
  282. {
  283. u32 *usbnc_usb_ctrl;
  284. if (port > 1)
  285. return -EINVAL;
  286. usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  287. port * 4);
  288. /* Set Power polarity */
  289. setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  290. return 0;
  291. }
  292. #endif
  293. #endif
  294. #ifdef CONFIG_FEC_MXC
  295. /*
  296. * pin conflicts for fec1 and fec2, GPIO1_IO06 and GPIO1_IO07 can only
  297. * be used for ENET1 or ENET2, cannot be used for both.
  298. */
  299. static iomux_v3_cfg_t const fec1_pads[] = {
  300. MX6_PAD_GPIO1_IO06__ENET1_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  301. MX6_PAD_GPIO1_IO07__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  302. MX6_PAD_ENET1_TX_DATA0__ENET1_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  303. MX6_PAD_ENET1_TX_DATA1__ENET1_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  304. MX6_PAD_ENET1_TX_EN__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  305. MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  306. MX6_PAD_ENET1_RX_DATA0__ENET1_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  307. MX6_PAD_ENET1_RX_DATA1__ENET1_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  308. MX6_PAD_ENET1_RX_ER__ENET1_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  309. MX6_PAD_ENET1_RX_EN__ENET1_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  310. };
  311. static iomux_v3_cfg_t const fec2_pads[] = {
  312. MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
  313. MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  314. MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  315. MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  316. MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  317. MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  318. MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  319. MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  320. MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  321. MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
  322. };
  323. static void setup_iomux_fec(int fec_id)
  324. {
  325. if (fec_id == 0)
  326. imx_iomux_v3_setup_multiple_pads(fec1_pads,
  327. ARRAY_SIZE(fec1_pads));
  328. else
  329. imx_iomux_v3_setup_multiple_pads(fec2_pads,
  330. ARRAY_SIZE(fec2_pads));
  331. }
  332. int board_eth_init(bd_t *bis)
  333. {
  334. setup_iomux_fec(CONFIG_FEC_ENET_DEV);
  335. return fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
  336. CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  337. }
  338. static int setup_fec(int fec_id)
  339. {
  340. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  341. int ret;
  342. if (fec_id == 0) {
  343. /*
  344. * Use 50M anatop loopback REF_CLK1 for ENET1,
  345. * clear gpr1[13], set gpr1[17].
  346. */
  347. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
  348. IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
  349. } else {
  350. /*
  351. * Use 50M anatop loopback REF_CLK2 for ENET2,
  352. * clear gpr1[14], set gpr1[18].
  353. */
  354. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
  355. IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
  356. }
  357. ret = enable_fec_anatop_clock(fec_id, ENET_50MHZ);
  358. if (ret)
  359. return ret;
  360. enable_enet_clk(1);
  361. return 0;
  362. }
  363. int board_phy_config(struct phy_device *phydev)
  364. {
  365. phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
  366. if (phydev->drv->config)
  367. phydev->drv->config(phydev);
  368. return 0;
  369. }
  370. #endif
  371. #ifdef CONFIG_VIDEO_MXS
  372. static iomux_v3_cfg_t const lcd_pads[] = {
  373. MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  374. MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  375. MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  376. MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  377. MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  378. MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  379. MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  380. MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  381. MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  382. MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  383. MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  384. MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  385. MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  386. MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  387. MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  388. MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  389. MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  390. MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  391. MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  392. MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  393. MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  394. MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  395. MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  396. MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  397. MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  398. MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  399. MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  400. MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  401. /* LCD_RST */
  402. MX6_PAD_SNVS_TAMPER9__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
  403. /* Use GPIO for Brightness adjustment, duty cycle = period. */
  404. MX6_PAD_GPIO1_IO08__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  405. };
  406. static int setup_lcd(void)
  407. {
  408. enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
  409. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  410. /* Reset the LCD */
  411. gpio_request(IMX_GPIO_NR(5, 9), "lcd reset");
  412. gpio_direction_output(IMX_GPIO_NR(5, 9) , 0);
  413. udelay(500);
  414. gpio_direction_output(IMX_GPIO_NR(5, 9) , 1);
  415. /* Set Brightness to high */
  416. gpio_request(IMX_GPIO_NR(1, 8), "backlight");
  417. gpio_direction_output(IMX_GPIO_NR(1, 8) , 1);
  418. return 0;
  419. }
  420. #endif
  421. int board_early_init_f(void)
  422. {
  423. setup_iomux_uart();
  424. return 0;
  425. }
  426. int board_init(void)
  427. {
  428. /* Address of boot parameters */
  429. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  430. #ifdef CONFIG_FEC_MXC
  431. setup_fec(CONFIG_FEC_ENET_DEV);
  432. #endif
  433. #ifdef CONFIG_USB_EHCI_MX6
  434. #ifndef CONFIG_DM_USB
  435. setup_usb();
  436. #endif
  437. #endif
  438. #ifdef CONFIG_FSL_QSPI
  439. board_qspi_init();
  440. #endif
  441. #ifdef CONFIG_VIDEO_MXS
  442. setup_lcd();
  443. #endif
  444. return 0;
  445. }
  446. #ifdef CONFIG_CMD_BMODE
  447. static const struct boot_mode board_boot_modes[] = {
  448. /* 4 bit bus width */
  449. {"sd1", MAKE_CFGVAL(0x42, 0x20, 0x00, 0x00)},
  450. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  451. {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
  452. {NULL, 0},
  453. };
  454. #endif
  455. int board_late_init(void)
  456. {
  457. #ifdef CONFIG_CMD_BMODE
  458. add_board_boot_modes(board_boot_modes);
  459. #endif
  460. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  461. env_set("board_name", "EVK");
  462. if (is_mx6ul_9x9_evk())
  463. env_set("board_rev", "9X9");
  464. else
  465. env_set("board_rev", "14X14");
  466. #endif
  467. return 0;
  468. }
  469. int checkboard(void)
  470. {
  471. if (is_mx6ul_9x9_evk())
  472. puts("Board: MX6UL 9x9 EVK\n");
  473. else
  474. puts("Board: MX6UL 14x14 EVK\n");
  475. return 0;
  476. }
  477. #ifdef CONFIG_SPL_BUILD
  478. #include <linux/libfdt.h>
  479. #include <spl.h>
  480. #include <asm/arch/mx6-ddr.h>
  481. static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
  482. .grp_addds = 0x00000030,
  483. .grp_ddrmode_ctl = 0x00020000,
  484. .grp_b0ds = 0x00000030,
  485. .grp_ctlds = 0x00000030,
  486. .grp_b1ds = 0x00000030,
  487. .grp_ddrpke = 0x00000000,
  488. .grp_ddrmode = 0x00020000,
  489. #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
  490. .grp_ddr_type = 0x00080000,
  491. #else
  492. .grp_ddr_type = 0x000c0000,
  493. #endif
  494. };
  495. #ifdef CONFIG_TARGET_MX6UL_9X9_EVK
  496. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  497. .dram_dqm0 = 0x00000030,
  498. .dram_dqm1 = 0x00000030,
  499. .dram_ras = 0x00000030,
  500. .dram_cas = 0x00000030,
  501. .dram_odt0 = 0x00000000,
  502. .dram_odt1 = 0x00000000,
  503. .dram_sdba2 = 0x00000000,
  504. .dram_sdclk_0 = 0x00000030,
  505. .dram_sdqs0 = 0x00003030,
  506. .dram_sdqs1 = 0x00003030,
  507. .dram_reset = 0x00000030,
  508. };
  509. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  510. .p0_mpwldectrl0 = 0x00000000,
  511. .p0_mpdgctrl0 = 0x20000000,
  512. .p0_mprddlctl = 0x4040484f,
  513. .p0_mpwrdlctl = 0x40405247,
  514. .mpzqlp2ctl = 0x1b4700c7,
  515. };
  516. static struct mx6_lpddr2_cfg mem_ddr = {
  517. .mem_speed = 800,
  518. .density = 2,
  519. .width = 16,
  520. .banks = 4,
  521. .rowaddr = 14,
  522. .coladdr = 10,
  523. .trcd_lp = 1500,
  524. .trppb_lp = 1500,
  525. .trpab_lp = 2000,
  526. .trasmin = 4250,
  527. };
  528. struct mx6_ddr_sysinfo ddr_sysinfo = {
  529. .dsize = 0,
  530. .cs_density = 18,
  531. .ncs = 1,
  532. .cs1_mirror = 0,
  533. .walat = 0,
  534. .ralat = 5,
  535. .mif3_mode = 3,
  536. .bi_on = 1,
  537. .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */
  538. .rtt_nom = 0,
  539. .sde_to_rst = 0, /* LPDDR2 does not need this field */
  540. .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
  541. .ddr_type = DDR_TYPE_LPDDR2,
  542. .refsel = 0, /* Refresh cycles at 64KHz */
  543. .refr = 3, /* 4 refresh commands per refresh cycle */
  544. };
  545. #else
  546. static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
  547. .dram_dqm0 = 0x00000030,
  548. .dram_dqm1 = 0x00000030,
  549. .dram_ras = 0x00000030,
  550. .dram_cas = 0x00000030,
  551. .dram_odt0 = 0x00000030,
  552. .dram_odt1 = 0x00000030,
  553. .dram_sdba2 = 0x00000000,
  554. .dram_sdclk_0 = 0x00000030,
  555. .dram_sdqs0 = 0x00000030,
  556. .dram_sdqs1 = 0x00000030,
  557. .dram_reset = 0x00000030,
  558. };
  559. static struct mx6_mmdc_calibration mx6_mmcd_calib = {
  560. .p0_mpwldectrl0 = 0x00000000,
  561. .p0_mpdgctrl0 = 0x41570155,
  562. .p0_mprddlctl = 0x4040474A,
  563. .p0_mpwrdlctl = 0x40405550,
  564. };
  565. struct mx6_ddr_sysinfo ddr_sysinfo = {
  566. .dsize = 0,
  567. .cs_density = 20,
  568. .ncs = 1,
  569. .cs1_mirror = 0,
  570. .rtt_wr = 2,
  571. .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
  572. .walat = 0, /* Write additional latency */
  573. .ralat = 5, /* Read additional latency */
  574. .mif3_mode = 3, /* Command prediction working mode */
  575. .bi_on = 1, /* Bank interleaving enabled */
  576. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  577. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  578. .ddr_type = DDR_TYPE_DDR3,
  579. .refsel = 0, /* Refresh cycles at 64KHz */
  580. .refr = 1, /* 2 refresh commands per refresh cycle */
  581. };
  582. static struct mx6_ddr3_cfg mem_ddr = {
  583. .mem_speed = 800,
  584. .density = 4,
  585. .width = 16,
  586. .banks = 8,
  587. .rowaddr = 15,
  588. .coladdr = 10,
  589. .pagesz = 2,
  590. .trcd = 1375,
  591. .trcmin = 4875,
  592. .trasmin = 3500,
  593. };
  594. #endif
  595. static void ccgr_init(void)
  596. {
  597. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  598. writel(0xFFFFFFFF, &ccm->CCGR0);
  599. writel(0xFFFFFFFF, &ccm->CCGR1);
  600. writel(0xFFFFFFFF, &ccm->CCGR2);
  601. writel(0xFFFFFFFF, &ccm->CCGR3);
  602. writel(0xFFFFFFFF, &ccm->CCGR4);
  603. writel(0xFFFFFFFF, &ccm->CCGR5);
  604. writel(0xFFFFFFFF, &ccm->CCGR6);
  605. writel(0xFFFFFFFF, &ccm->CCGR7);
  606. }
  607. static void spl_dram_init(void)
  608. {
  609. mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  610. mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
  611. }
  612. void board_init_f(ulong dummy)
  613. {
  614. ccgr_init();
  615. /* setup AIPS and disable watchdog */
  616. arch_cpu_init();
  617. /* iomux and setup of i2c */
  618. board_early_init_f();
  619. /* setup GP timer */
  620. timer_init();
  621. /* UART clocks enabled and gd valid - init serial console */
  622. preloader_console_init();
  623. /* DDR initialization */
  624. spl_dram_init();
  625. /* Clear the BSS. */
  626. memset(__bss_start, 0, __bss_end - __bss_start);
  627. /* load/boot image from boot device */
  628. board_init_r(NULL, 0);
  629. }
  630. #endif