mx6sxsabresd.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. */
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/crm_regs.h>
  9. #include <asm/arch/iomux.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/io.h>
  16. #include <asm/mach-imx/mxc_i2c.h>
  17. #include <linux/sizes.h>
  18. #include <common.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <mmc.h>
  21. #include <i2c.h>
  22. #include <miiphy.h>
  23. #include <netdev.h>
  24. #include <power/pmic.h>
  25. #include <power/pfuze100_pmic.h>
  26. #include "../common/pfuze.h"
  27. DECLARE_GLOBAL_DATA_PTR;
  28. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  29. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  30. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  31. #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  32. PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
  33. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  34. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  35. PAD_CTL_SPEED_HIGH | \
  36. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  37. #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  38. PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  39. #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  40. PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  41. #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  42. PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
  43. #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
  44. PAD_CTL_DSE_40ohm)
  45. int dram_init(void)
  46. {
  47. gd->ram_size = imx_ddr_size();
  48. return 0;
  49. }
  50. static iomux_v3_cfg_t const uart1_pads[] = {
  51. MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  52. MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  53. };
  54. static iomux_v3_cfg_t const wdog_b_pad = {
  55. MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  56. };
  57. static iomux_v3_cfg_t const fec1_pads[] = {
  58. MX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59. MX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60. MX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  61. MX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  62. MX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  63. MX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  64. MX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  65. MX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  66. MX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67. MX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68. MX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69. MX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70. MX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71. MX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72. };
  73. static iomux_v3_cfg_t const peri_3v3_pads[] = {
  74. MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),
  75. };
  76. static iomux_v3_cfg_t const phy_control_pads[] = {
  77. /* 25MHz Ethernet PHY Clock */
  78. MX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  79. /* ENET PHY Power */
  80. MX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),
  81. /* AR8031 PHY Reset */
  82. MX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
  83. };
  84. static void setup_iomux_uart(void)
  85. {
  86. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  87. }
  88. static int setup_fec(void)
  89. {
  90. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  91. struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
  92. int reg, ret;
  93. /* Use 125MHz anatop loopback REF_CLK1 for ENET1 */
  94. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);
  95. ret = enable_fec_anatop_clock(0, ENET_125MHZ);
  96. if (ret)
  97. return ret;
  98. imx_iomux_v3_setup_multiple_pads(phy_control_pads,
  99. ARRAY_SIZE(phy_control_pads));
  100. /* Enable the ENET power, active low */
  101. gpio_request(IMX_GPIO_NR(2, 6), "enet_rst");
  102. gpio_direction_output(IMX_GPIO_NR(2, 6) , 0);
  103. /* Reset AR8031 PHY */
  104. gpio_request(IMX_GPIO_NR(2, 7), "phy_rst");
  105. gpio_direction_output(IMX_GPIO_NR(2, 7) , 0);
  106. mdelay(10);
  107. gpio_set_value(IMX_GPIO_NR(2, 7), 1);
  108. reg = readl(&anatop->pll_enet);
  109. reg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;
  110. writel(reg, &anatop->pll_enet);
  111. return 0;
  112. }
  113. int board_eth_init(bd_t *bis)
  114. {
  115. imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
  116. setup_fec();
  117. return cpu_eth_init(bis);
  118. }
  119. int power_init_board(void)
  120. {
  121. struct udevice *dev;
  122. unsigned int reg;
  123. int ret;
  124. dev = pfuze_common_init();
  125. if (!dev)
  126. return -ENODEV;
  127. ret = pfuze_mode_init(dev, APS_PFM);
  128. if (ret < 0)
  129. return ret;
  130. /* Enable power of VGEN5 3V3, needed for SD3 */
  131. reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
  132. reg &= ~LDO_VOL_MASK;
  133. reg |= (LDOB_3_30V | (1 << LDO_EN));
  134. pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
  135. return 0;
  136. }
  137. int board_phy_config(struct phy_device *phydev)
  138. {
  139. /*
  140. * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
  141. * Phy control debug reg 0
  142. */
  143. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  144. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  145. /* rgmii tx clock delay enable */
  146. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  147. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  148. if (phydev->drv->config)
  149. phydev->drv->config(phydev);
  150. return 0;
  151. }
  152. int board_early_init_f(void)
  153. {
  154. setup_iomux_uart();
  155. /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */
  156. imx_iomux_v3_setup_multiple_pads(peri_3v3_pads,
  157. ARRAY_SIZE(peri_3v3_pads));
  158. return 0;
  159. }
  160. int board_mmc_get_env_dev(int devno)
  161. {
  162. return devno;
  163. }
  164. #ifdef CONFIG_FSL_QSPI
  165. int board_qspi_init(void)
  166. {
  167. /* Set the clock */
  168. enable_qspi_clk(1);
  169. return 0;
  170. }
  171. #endif
  172. #ifdef CONFIG_VIDEO_MXS
  173. static iomux_v3_cfg_t const lcd_pads[] = {
  174. MX6_PAD_LCD1_CLK__LCDIF1_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
  175. MX6_PAD_LCD1_ENABLE__LCDIF1_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
  176. MX6_PAD_LCD1_HSYNC__LCDIF1_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  177. MX6_PAD_LCD1_VSYNC__LCDIF1_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
  178. MX6_PAD_LCD1_DATA00__LCDIF1_DATA_0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  179. MX6_PAD_LCD1_DATA01__LCDIF1_DATA_1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  180. MX6_PAD_LCD1_DATA02__LCDIF1_DATA_2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  181. MX6_PAD_LCD1_DATA03__LCDIF1_DATA_3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  182. MX6_PAD_LCD1_DATA04__LCDIF1_DATA_4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  183. MX6_PAD_LCD1_DATA05__LCDIF1_DATA_5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  184. MX6_PAD_LCD1_DATA06__LCDIF1_DATA_6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  185. MX6_PAD_LCD1_DATA07__LCDIF1_DATA_7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  186. MX6_PAD_LCD1_DATA08__LCDIF1_DATA_8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  187. MX6_PAD_LCD1_DATA09__LCDIF1_DATA_9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  188. MX6_PAD_LCD1_DATA10__LCDIF1_DATA_10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  189. MX6_PAD_LCD1_DATA11__LCDIF1_DATA_11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  190. MX6_PAD_LCD1_DATA12__LCDIF1_DATA_12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  191. MX6_PAD_LCD1_DATA13__LCDIF1_DATA_13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  192. MX6_PAD_LCD1_DATA14__LCDIF1_DATA_14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  193. MX6_PAD_LCD1_DATA15__LCDIF1_DATA_15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  194. MX6_PAD_LCD1_DATA16__LCDIF1_DATA_16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  195. MX6_PAD_LCD1_DATA17__LCDIF1_DATA_17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  196. MX6_PAD_LCD1_DATA18__LCDIF1_DATA_18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  197. MX6_PAD_LCD1_DATA19__LCDIF1_DATA_19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  198. MX6_PAD_LCD1_DATA20__LCDIF1_DATA_20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  199. MX6_PAD_LCD1_DATA21__LCDIF1_DATA_21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  200. MX6_PAD_LCD1_DATA22__LCDIF1_DATA_22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  201. MX6_PAD_LCD1_DATA23__LCDIF1_DATA_23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
  202. MX6_PAD_LCD1_RESET__GPIO3_IO_27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  203. /* Use GPIO for Brightness adjustment, duty cycle = period */
  204. MX6_PAD_SD1_DATA2__GPIO6_IO_4 | MUX_PAD_CTRL(NO_PAD_CTRL),
  205. };
  206. static int setup_lcd(void)
  207. {
  208. enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
  209. imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
  210. /* Reset the LCD */
  211. gpio_request(IMX_GPIO_NR(3, 27), "lcd_rst");
  212. gpio_direction_output(IMX_GPIO_NR(3, 27) , 0);
  213. udelay(500);
  214. gpio_direction_output(IMX_GPIO_NR(3, 27) , 1);
  215. /* Set Brightness to high */
  216. gpio_request(IMX_GPIO_NR(6, 4), "lcd_bright");
  217. gpio_direction_output(IMX_GPIO_NR(6, 4) , 1);
  218. return 0;
  219. }
  220. #endif
  221. int board_init(void)
  222. {
  223. /* Address of boot parameters */
  224. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  225. /*
  226. * Because kernel set WDOG_B mux before pad with the common pinctrl
  227. * framwork now and wdog reset will be triggered once set WDOG_B mux
  228. * with default pad setting, we set pad setting here to workaround this.
  229. * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set
  230. * as GPIO mux firstly here to workaround it.
  231. */
  232. imx_iomux_v3_setup_pad(wdog_b_pad);
  233. /* Active high for ncp692 */
  234. gpio_request(IMX_GPIO_NR(4, 16), "ncp692_en");
  235. gpio_direction_output(IMX_GPIO_NR(4, 16), 1);
  236. #ifdef CONFIG_FSL_QSPI
  237. board_qspi_init();
  238. #endif
  239. #ifdef CONFIG_VIDEO_MXS
  240. setup_lcd();
  241. #endif
  242. return 0;
  243. }
  244. static bool is_reva(void)
  245. {
  246. return (nxp_board_rev() == 1);
  247. }
  248. int board_late_init(void)
  249. {
  250. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  251. if (is_reva())
  252. env_set("board_rev", "REVA");
  253. #endif
  254. return 0;
  255. }
  256. int checkboard(void)
  257. {
  258. printf("Board: MX6SX SABRE SDB rev%c\n", nxp_board_rev_string());
  259. return 0;
  260. }
  261. #ifdef CONFIG_SPL_BUILD
  262. #include <linux/libfdt.h>
  263. #include <spl.h>
  264. #include <asm/arch/mx6-ddr.h>
  265. static struct fsl_esdhc_cfg usdhc_cfg[3] = {
  266. {USDHC2_BASE_ADDR, 0, 4},
  267. {USDHC3_BASE_ADDR},
  268. {USDHC4_BASE_ADDR},
  269. };
  270. #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 10)
  271. #define USDHC3_PWR_GPIO IMX_GPIO_NR(2, 11)
  272. #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 21)
  273. static iomux_v3_cfg_t const usdhc2_pads[] = {
  274. MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  275. MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  276. MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  277. MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  278. MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  279. MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  280. };
  281. static iomux_v3_cfg_t const usdhc3_pads[] = {
  282. MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  283. MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  284. MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  285. MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  286. MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  287. MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  288. MX6_PAD_SD3_DATA4__USDHC3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  289. MX6_PAD_SD3_DATA5__USDHC3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  290. MX6_PAD_SD3_DATA6__USDHC3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  291. MX6_PAD_SD3_DATA7__USDHC3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  292. /* CD pin */
  293. MX6_PAD_KEY_COL0__GPIO2_IO_10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  294. /* RST_B, used for power reset cycle */
  295. MX6_PAD_KEY_COL1__GPIO2_IO_11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  296. };
  297. static iomux_v3_cfg_t const usdhc4_pads[] = {
  298. MX6_PAD_SD4_CLK__USDHC4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  299. MX6_PAD_SD4_CMD__USDHC4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  300. MX6_PAD_SD4_DATA0__USDHC4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  301. MX6_PAD_SD4_DATA1__USDHC4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  302. MX6_PAD_SD4_DATA2__USDHC4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  303. MX6_PAD_SD4_DATA3__USDHC4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  304. MX6_PAD_SD4_DATA7__GPIO6_IO_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  305. };
  306. int board_mmc_init(bd_t *bis)
  307. {
  308. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  309. u32 val;
  310. u32 port;
  311. val = readl(&src_regs->sbmr1);
  312. if ((val & 0xc0) != 0x40) {
  313. printf("Not boot from USDHC!\n");
  314. return -EINVAL;
  315. }
  316. port = (val >> 11) & 0x3;
  317. printf("port %d\n", port);
  318. switch (port) {
  319. case 1:
  320. imx_iomux_v3_setup_multiple_pads(
  321. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  322. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  323. usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
  324. break;
  325. case 2:
  326. imx_iomux_v3_setup_multiple_pads(
  327. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  328. gpio_direction_input(USDHC3_CD_GPIO);
  329. gpio_direction_output(USDHC3_PWR_GPIO, 1);
  330. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  331. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  332. break;
  333. case 3:
  334. imx_iomux_v3_setup_multiple_pads(
  335. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  336. gpio_direction_input(USDHC4_CD_GPIO);
  337. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  338. usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
  339. break;
  340. }
  341. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  342. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  343. }
  344. int board_mmc_getcd(struct mmc *mmc)
  345. {
  346. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  347. int ret = 0;
  348. switch (cfg->esdhc_base) {
  349. case USDHC2_BASE_ADDR:
  350. ret = 1; /* Assume uSDHC2 is always present */
  351. break;
  352. case USDHC3_BASE_ADDR:
  353. ret = !gpio_get_value(USDHC3_CD_GPIO);
  354. break;
  355. case USDHC4_BASE_ADDR:
  356. ret = !gpio_get_value(USDHC4_CD_GPIO);
  357. break;
  358. }
  359. return ret;
  360. }
  361. const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = {
  362. .dram_dqm0 = 0x00000028,
  363. .dram_dqm1 = 0x00000028,
  364. .dram_dqm2 = 0x00000028,
  365. .dram_dqm3 = 0x00000028,
  366. .dram_ras = 0x00000020,
  367. .dram_cas = 0x00000020,
  368. .dram_odt0 = 0x00000020,
  369. .dram_odt1 = 0x00000020,
  370. .dram_sdba2 = 0x00000000,
  371. .dram_sdcke0 = 0x00003000,
  372. .dram_sdcke1 = 0x00003000,
  373. .dram_sdclk_0 = 0x00000030,
  374. .dram_sdqs0 = 0x00000028,
  375. .dram_sdqs1 = 0x00000028,
  376. .dram_sdqs2 = 0x00000028,
  377. .dram_sdqs3 = 0x00000028,
  378. .dram_reset = 0x00000020,
  379. };
  380. const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = {
  381. .grp_addds = 0x00000020,
  382. .grp_ddrmode_ctl = 0x00020000,
  383. .grp_ddrpke = 0x00000000,
  384. .grp_ddrmode = 0x00020000,
  385. .grp_b0ds = 0x00000028,
  386. .grp_b1ds = 0x00000028,
  387. .grp_ctlds = 0x00000020,
  388. .grp_ddr_type = 0x000c0000,
  389. .grp_b2ds = 0x00000028,
  390. .grp_b3ds = 0x00000028,
  391. };
  392. const struct mx6_mmdc_calibration mx6_mmcd_calib = {
  393. .p0_mpwldectrl0 = 0x00290025,
  394. .p0_mpwldectrl1 = 0x00220022,
  395. .p0_mpdgctrl0 = 0x41480144,
  396. .p0_mpdgctrl1 = 0x01340130,
  397. .p0_mprddlctl = 0x3C3E4244,
  398. .p0_mpwrdlctl = 0x34363638,
  399. };
  400. static struct mx6_ddr3_cfg mem_ddr = {
  401. .mem_speed = 1600,
  402. .density = 4,
  403. .width = 32,
  404. .banks = 8,
  405. .rowaddr = 15,
  406. .coladdr = 10,
  407. .pagesz = 2,
  408. .trcd = 1375,
  409. .trcmin = 4875,
  410. .trasmin = 3500,
  411. };
  412. static void ccgr_init(void)
  413. {
  414. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  415. writel(0xFFFFFFFF, &ccm->CCGR0);
  416. writel(0xFFFFFFFF, &ccm->CCGR1);
  417. writel(0xFFFFFFFF, &ccm->CCGR2);
  418. writel(0xFFFFFFFF, &ccm->CCGR3);
  419. writel(0xFFFFFFFF, &ccm->CCGR4);
  420. writel(0xFFFFFFFF, &ccm->CCGR5);
  421. writel(0xFFFFFFFF, &ccm->CCGR6);
  422. writel(0xFFFFFFFF, &ccm->CCGR7);
  423. }
  424. static void spl_dram_init(void)
  425. {
  426. struct mx6_ddr_sysinfo sysinfo = {
  427. .dsize = mem_ddr.width/32,
  428. .cs_density = 24,
  429. .ncs = 1,
  430. .cs1_mirror = 0,
  431. .rtt_wr = 2,
  432. .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
  433. .walat = 1, /* Write additional latency */
  434. .ralat = 5, /* Read additional latency */
  435. .mif3_mode = 3, /* Command prediction working mode */
  436. .bi_on = 1, /* Bank interleaving enabled */
  437. .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
  438. .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
  439. .ddr_type = DDR_TYPE_DDR3,
  440. .refsel = 1, /* Refresh cycles at 32KHz */
  441. .refr = 7, /* 8 refresh commands per refresh cycle */
  442. };
  443. mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
  444. mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
  445. }
  446. void board_init_f(ulong dummy)
  447. {
  448. /* setup AIPS and disable watchdog */
  449. arch_cpu_init();
  450. ccgr_init();
  451. /* iomux and setup of i2c */
  452. board_early_init_f();
  453. /* setup GP timer */
  454. timer_init();
  455. /* UART clocks enabled and gd valid - init serial console */
  456. preloader_console_init();
  457. /* DDR initialization */
  458. spl_dram_init();
  459. /* Clear the BSS. */
  460. memset(__bss_start, 0, __bss_end - __bss_start);
  461. /* load/boot image from boot device */
  462. board_init_r(NULL, 0);
  463. }
  464. #endif