mx6sxsabreauto.c 8.5 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Ye Li <ye.li@nxp.com>
  6. */
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/crm_regs.h>
  9. #include <asm/arch/iomux.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/mx6-pins.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/io.h>
  17. #include <linux/sizes.h>
  18. #include <common.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <miiphy.h>
  21. #include <netdev.h>
  22. #include <power/pmic.h>
  23. #include <power/pfuze100_pmic.h>
  24. #include "../common/pfuze.h"
  25. #include <usb.h>
  26. #include <usb/ehci-ci.h>
  27. #include <pca953x.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  30. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  31. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  32. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  33. PAD_CTL_SPEED_HIGH | \
  34. PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  35. #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  36. PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  37. #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  38. PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  39. #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
  40. #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
  41. PAD_CTL_SRE_FAST)
  42. #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
  43. int dram_init(void)
  44. {
  45. gd->ram_size = imx_ddr_size();
  46. return 0;
  47. }
  48. static iomux_v3_cfg_t const uart1_pads[] = {
  49. MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  50. MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  51. };
  52. static iomux_v3_cfg_t const fec2_pads[] = {
  53. MX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  54. MX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  55. MX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  56. MX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  57. MX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  58. MX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  59. MX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  60. MX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  61. MX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62. MX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63. MX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64. MX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65. MX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66. MX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67. };
  68. static void setup_iomux_uart(void)
  69. {
  70. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  71. }
  72. static int setup_fec(void)
  73. {
  74. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  75. /* Use 125MHz anatop loopback REF_CLK1 for ENET2 */
  76. clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);
  77. return enable_fec_anatop_clock(1, ENET_125MHZ);
  78. }
  79. int board_eth_init(bd_t *bis)
  80. {
  81. int ret;
  82. imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
  83. setup_fec();
  84. ret = fecmxc_initialize_multi(bis, 1,
  85. CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  86. if (ret)
  87. printf("FEC%d MXC: %s:failed\n", 1, __func__);
  88. return ret;
  89. }
  90. int board_phy_config(struct phy_device *phydev)
  91. {
  92. /*
  93. * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
  94. * Phy control debug reg 0
  95. */
  96. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  97. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  98. /* rgmii tx clock delay enable */
  99. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  100. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  101. if (phydev->drv->config)
  102. phydev->drv->config(phydev);
  103. return 0;
  104. }
  105. int power_init_board(void)
  106. {
  107. struct udevice *dev;
  108. int ret;
  109. u32 dev_id, rev_id, i;
  110. u32 switch_num = 6;
  111. u32 offset = PFUZE100_SW1CMODE;
  112. ret = pmic_get("pfuze100", &dev);
  113. if (ret == -ENODEV)
  114. return 0;
  115. if (ret != 0)
  116. return ret;
  117. dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
  118. rev_id = pmic_reg_read(dev, PFUZE100_REVID);
  119. printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
  120. /* Init mode to APS_PFM */
  121. pmic_reg_write(dev, PFUZE100_SW1ABMODE, APS_PFM);
  122. for (i = 0; i < switch_num - 1; i++)
  123. pmic_reg_write(dev, offset + i * SWITCH_SIZE, APS_PFM);
  124. /* set SW1AB staby volatage 0.975V */
  125. pmic_clrsetbits(dev, PFUZE100_SW1ABSTBY, 0x3f, 0x1b);
  126. /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
  127. pmic_clrsetbits(dev, PFUZE100_SW1ABCONF, 0xc0, 0x40);
  128. /* set SW1C staby volatage 1.10V */
  129. pmic_clrsetbits(dev, PFUZE100_SW1CSTBY, 0x3f, 0x20);
  130. /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
  131. pmic_clrsetbits(dev, PFUZE100_SW1CCONF, 0xc0, 0x40);
  132. return 0;
  133. }
  134. #ifdef CONFIG_USB_EHCI_MX6
  135. #define USB_OTHERREGS_OFFSET 0x800
  136. #define UCTRL_PWR_POL (1 << 9)
  137. static iomux_v3_cfg_t const usb_otg_pads[] = {
  138. /* OGT1 */
  139. MX6_PAD_GPIO1_IO09__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  140. MX6_PAD_GPIO1_IO10__ANATOP_OTG1_ID | MUX_PAD_CTRL(NO_PAD_CTRL),
  141. /* OTG2 */
  142. MX6_PAD_GPIO1_IO12__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
  143. };
  144. static void setup_usb(void)
  145. {
  146. imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
  147. ARRAY_SIZE(usb_otg_pads));
  148. }
  149. int board_usb_phy_mode(int port)
  150. {
  151. if (port == 1)
  152. return USB_INIT_HOST;
  153. else
  154. return usb_phy_mode(port);
  155. }
  156. int board_ehci_hcd_init(int port)
  157. {
  158. u32 *usbnc_usb_ctrl;
  159. if (port > 1)
  160. return -EINVAL;
  161. usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
  162. port * 4);
  163. /* Set Power polarity */
  164. setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
  165. return 0;
  166. }
  167. #endif
  168. int board_early_init_f(void)
  169. {
  170. setup_iomux_uart();
  171. return 0;
  172. }
  173. #ifdef CONFIG_FSL_QSPI
  174. int board_qspi_init(void)
  175. {
  176. /* Set the clock */
  177. enable_qspi_clk(0);
  178. return 0;
  179. }
  180. #endif
  181. #ifdef CONFIG_NAND_MXS
  182. iomux_v3_cfg_t gpmi_pads[] = {
  183. MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  184. MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  185. MX6_PAD_NAND_WP_B__RAWNAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  186. MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0),
  187. MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  188. MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  189. MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  190. MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  191. MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  192. MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  193. MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  194. MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  195. MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  196. MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  197. MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2),
  198. };
  199. static void setup_gpmi_nand(void)
  200. {
  201. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  202. /* config gpmi nand iomux */
  203. imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
  204. setup_gpmi_io_clk((MXC_CCM_CS2CDR_QSPI2_CLK_PODF(0) |
  205. MXC_CCM_CS2CDR_QSPI2_CLK_PRED(3) |
  206. MXC_CCM_CS2CDR_QSPI2_CLK_SEL(3)));
  207. /* enable apbh clock gating */
  208. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  209. }
  210. #endif
  211. int board_init(void)
  212. {
  213. struct gpio_desc desc;
  214. int ret;
  215. /* Address of boot parameters */
  216. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  217. ret = dm_gpio_lookup_name("gpio@30_4", &desc);
  218. if (ret)
  219. return ret;
  220. ret = dm_gpio_request(&desc, "cpu_per_rst_b");
  221. if (ret)
  222. return ret;
  223. /* Reset CPU_PER_RST_B signal for enet phy and PCIE */
  224. dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
  225. udelay(500);
  226. dm_gpio_set_value(&desc, 1);
  227. ret = dm_gpio_lookup_name("gpio@32_2", &desc);
  228. if (ret)
  229. return ret;
  230. ret = dm_gpio_request(&desc, "steer_enet");
  231. if (ret)
  232. return ret;
  233. dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
  234. udelay(500);
  235. /* Set steering signal to L for selecting B0 */
  236. dm_gpio_set_value(&desc, 0);
  237. #ifdef CONFIG_USB_EHCI_MX6
  238. setup_usb();
  239. #endif
  240. #ifdef CONFIG_FSL_QSPI
  241. board_qspi_init();
  242. #endif
  243. #ifdef CONFIG_NAND_MXS
  244. setup_gpmi_nand();
  245. #endif
  246. return 0;
  247. }
  248. #ifdef CONFIG_CMD_BMODE
  249. static const struct boot_mode board_boot_modes[] = {
  250. {"sda", MAKE_CFGVAL(0x42, 0x30, 0x00, 0x00)},
  251. {"sdb", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  252. {"qspi1", MAKE_CFGVAL(0x10, 0x00, 0x00, 0x00)},
  253. {"nand", MAKE_CFGVAL(0x82, 0x00, 0x00, 0x00)},
  254. {NULL, 0},
  255. };
  256. #endif
  257. int board_late_init(void)
  258. {
  259. #ifdef CONFIG_CMD_BMODE
  260. add_board_boot_modes(board_boot_modes);
  261. #endif
  262. return 0;
  263. }
  264. int checkboard(void)
  265. {
  266. puts("Board: MX6SX SABRE AUTO\n");
  267. return 0;
  268. }