mx6sabresd.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  4. *
  5. * Author: Fabio Estevam <fabio.estevam@freescale.com>
  6. */
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/iomux.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/mach-imx/spi.h>
  12. #include <linux/errno.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/mxc_i2c.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <asm/mach-imx/video.h>
  18. #include <mmc.h>
  19. #include <fsl_esdhc_imx.h>
  20. #include <miiphy.h>
  21. #include <netdev.h>
  22. #include <asm/arch/mxc_hdmi.h>
  23. #include <asm/arch/crm_regs.h>
  24. #include <asm/io.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include <i2c.h>
  27. #include <input.h>
  28. #include <power/pmic.h>
  29. #include <power/pfuze100_pmic.h>
  30. #include "../common/pfuze.h"
  31. #include <usb.h>
  32. #include <usb/ehci-ci.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  35. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  36. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  38. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  39. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  40. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  41. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  42. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  43. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  44. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  45. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  46. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  47. #define I2C_PMIC 1
  48. #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  49. #define DISP0_PWR_EN IMX_GPIO_NR(1, 21)
  50. #define KEY_VOL_UP IMX_GPIO_NR(1, 4)
  51. int dram_init(void)
  52. {
  53. gd->ram_size = imx_ddr_size();
  54. return 0;
  55. }
  56. static iomux_v3_cfg_t const uart1_pads[] = {
  57. IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  58. IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  59. };
  60. static iomux_v3_cfg_t const enet_pads[] = {
  61. IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  62. IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  63. IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  64. IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  65. IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  66. IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  67. IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  68. IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  69. IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  70. IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  71. IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  72. IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  73. IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  74. IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  75. IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
  76. /* AR8031 PHY Reset */
  77. IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  78. };
  79. static void setup_iomux_enet(void)
  80. {
  81. SETUP_IOMUX_PADS(enet_pads);
  82. }
  83. static iomux_v3_cfg_t const usdhc2_pads[] = {
  84. IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  85. IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  86. IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  87. IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  88. IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  89. IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  90. IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  91. IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  92. IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  93. IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  94. IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
  95. };
  96. static iomux_v3_cfg_t const usdhc3_pads[] = {
  97. IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  98. IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  99. IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  100. IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  101. IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  102. IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  103. IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  104. IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  105. IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  106. IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  107. IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
  108. };
  109. static iomux_v3_cfg_t const usdhc4_pads[] = {
  110. IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  111. IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  112. IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  113. IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  114. IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  115. IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  116. IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  117. IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  118. IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  119. IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  120. };
  121. static iomux_v3_cfg_t const ecspi1_pads[] = {
  122. IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  123. IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  124. IOMUX_PADS(PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
  125. IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  126. };
  127. static iomux_v3_cfg_t const rgb_pads[] = {
  128. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
  129. IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  130. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  131. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  132. IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  133. IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  134. IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  135. IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  136. IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  137. IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  138. IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  139. IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  140. IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  141. IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  142. IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  143. IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  144. IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  145. IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  146. IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  147. IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  148. IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  149. IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  150. IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  151. IOMUX_PADS(PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  152. IOMUX_PADS(PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  153. IOMUX_PADS(PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  154. IOMUX_PADS(PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  155. IOMUX_PADS(PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  156. IOMUX_PADS(PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  157. };
  158. static iomux_v3_cfg_t const bl_pads[] = {
  159. IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  160. };
  161. static void enable_backlight(void)
  162. {
  163. SETUP_IOMUX_PADS(bl_pads);
  164. gpio_request(DISP0_PWR_EN, "Display Power Enable");
  165. gpio_direction_output(DISP0_PWR_EN, 1);
  166. }
  167. static void enable_rgb(struct display_info_t const *dev)
  168. {
  169. SETUP_IOMUX_PADS(rgb_pads);
  170. enable_backlight();
  171. }
  172. static void enable_lvds(struct display_info_t const *dev)
  173. {
  174. enable_backlight();
  175. }
  176. static struct i2c_pads_info mx6q_i2c_pad_info1 = {
  177. .scl = {
  178. .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  179. .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  180. .gp = IMX_GPIO_NR(4, 12)
  181. },
  182. .sda = {
  183. .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  184. .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  185. .gp = IMX_GPIO_NR(4, 13)
  186. }
  187. };
  188. static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
  189. .scl = {
  190. .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  191. .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  192. .gp = IMX_GPIO_NR(4, 12)
  193. },
  194. .sda = {
  195. .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  196. .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  197. .gp = IMX_GPIO_NR(4, 13)
  198. }
  199. };
  200. static void setup_spi(void)
  201. {
  202. SETUP_IOMUX_PADS(ecspi1_pads);
  203. }
  204. iomux_v3_cfg_t const pcie_pads[] = {
  205. IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* POWER */
  206. IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* RESET */
  207. };
  208. static void setup_pcie(void)
  209. {
  210. SETUP_IOMUX_PADS(pcie_pads);
  211. }
  212. iomux_v3_cfg_t const di0_pads[] = {
  213. IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), /* DISP0_CLK */
  214. IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* DISP0_HSYNC */
  215. IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* DISP0_VSYNC */
  216. };
  217. static void setup_iomux_uart(void)
  218. {
  219. SETUP_IOMUX_PADS(uart1_pads);
  220. }
  221. #ifdef CONFIG_FSL_ESDHC_IMX
  222. struct fsl_esdhc_cfg usdhc_cfg[3] = {
  223. {USDHC2_BASE_ADDR},
  224. {USDHC3_BASE_ADDR},
  225. {USDHC4_BASE_ADDR},
  226. };
  227. #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
  228. #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
  229. int board_mmc_get_env_dev(int devno)
  230. {
  231. return devno - 1;
  232. }
  233. int board_mmc_getcd(struct mmc *mmc)
  234. {
  235. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  236. int ret = 0;
  237. switch (cfg->esdhc_base) {
  238. case USDHC2_BASE_ADDR:
  239. ret = !gpio_get_value(USDHC2_CD_GPIO);
  240. break;
  241. case USDHC3_BASE_ADDR:
  242. ret = !gpio_get_value(USDHC3_CD_GPIO);
  243. break;
  244. case USDHC4_BASE_ADDR:
  245. ret = 1; /* eMMC/uSDHC4 is always present */
  246. break;
  247. }
  248. return ret;
  249. }
  250. int board_mmc_init(bd_t *bis)
  251. {
  252. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  253. unsigned reg = readl(&psrc->sbmr1) >> 11;
  254. /*
  255. * Upon reading BOOT_CFG register the following map is done:
  256. * Bit 11 and 12 of BOOT_CFG register can determine the current
  257. * mmc port
  258. * 0x1 SD1
  259. * 0x2 SD2
  260. * 0x3 SD4
  261. */
  262. switch (reg & 0x3) {
  263. case 0x1:
  264. SETUP_IOMUX_PADS(usdhc2_pads);
  265. usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
  266. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  267. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  268. break;
  269. case 0x2:
  270. SETUP_IOMUX_PADS(usdhc3_pads);
  271. usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
  272. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  273. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  274. break;
  275. case 0x3:
  276. SETUP_IOMUX_PADS(usdhc4_pads);
  277. usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
  278. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  279. gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
  280. break;
  281. }
  282. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  283. }
  284. #endif
  285. static int ar8031_phy_fixup(struct phy_device *phydev)
  286. {
  287. unsigned short val;
  288. /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  289. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  290. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  291. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  292. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  293. val &= 0xffe3;
  294. val |= 0x18;
  295. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  296. /* introduce tx clock delay */
  297. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  298. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  299. val |= 0x0100;
  300. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  301. return 0;
  302. }
  303. int board_phy_config(struct phy_device *phydev)
  304. {
  305. ar8031_phy_fixup(phydev);
  306. if (phydev->drv->config)
  307. phydev->drv->config(phydev);
  308. return 0;
  309. }
  310. #if defined(CONFIG_VIDEO_IPUV3)
  311. static void disable_lvds(struct display_info_t const *dev)
  312. {
  313. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  314. int reg = readl(&iomux->gpr[2]);
  315. reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
  316. IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
  317. writel(reg, &iomux->gpr[2]);
  318. }
  319. static void do_enable_hdmi(struct display_info_t const *dev)
  320. {
  321. disable_lvds(dev);
  322. imx_enable_hdmi_phy();
  323. }
  324. struct display_info_t const displays[] = {{
  325. .bus = -1,
  326. .addr = 0,
  327. .pixfmt = IPU_PIX_FMT_RGB666,
  328. .detect = NULL,
  329. .enable = enable_lvds,
  330. .mode = {
  331. .name = "Hannstar-XGA",
  332. .refresh = 60,
  333. .xres = 1024,
  334. .yres = 768,
  335. .pixclock = 15384,
  336. .left_margin = 160,
  337. .right_margin = 24,
  338. .upper_margin = 29,
  339. .lower_margin = 3,
  340. .hsync_len = 136,
  341. .vsync_len = 6,
  342. .sync = FB_SYNC_EXT,
  343. .vmode = FB_VMODE_NONINTERLACED
  344. } }, {
  345. .bus = -1,
  346. .addr = 0,
  347. .pixfmt = IPU_PIX_FMT_RGB24,
  348. .detect = detect_hdmi,
  349. .enable = do_enable_hdmi,
  350. .mode = {
  351. .name = "HDMI",
  352. .refresh = 60,
  353. .xres = 1024,
  354. .yres = 768,
  355. .pixclock = 15384,
  356. .left_margin = 160,
  357. .right_margin = 24,
  358. .upper_margin = 29,
  359. .lower_margin = 3,
  360. .hsync_len = 136,
  361. .vsync_len = 6,
  362. .sync = FB_SYNC_EXT,
  363. .vmode = FB_VMODE_NONINTERLACED
  364. } }, {
  365. .bus = 0,
  366. .addr = 0,
  367. .pixfmt = IPU_PIX_FMT_RGB24,
  368. .detect = NULL,
  369. .enable = enable_rgb,
  370. .mode = {
  371. .name = "SEIKO-WVGA",
  372. .refresh = 60,
  373. .xres = 800,
  374. .yres = 480,
  375. .pixclock = 29850,
  376. .left_margin = 89,
  377. .right_margin = 164,
  378. .upper_margin = 23,
  379. .lower_margin = 10,
  380. .hsync_len = 10,
  381. .vsync_len = 10,
  382. .sync = 0,
  383. .vmode = FB_VMODE_NONINTERLACED
  384. } } };
  385. size_t display_count = ARRAY_SIZE(displays);
  386. static void setup_display(void)
  387. {
  388. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  389. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  390. int reg;
  391. /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
  392. SETUP_IOMUX_PADS(di0_pads);
  393. enable_ipu_clock();
  394. imx_setup_hdmi();
  395. /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
  396. reg = readl(&mxc_ccm->CCGR3);
  397. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
  398. writel(reg, &mxc_ccm->CCGR3);
  399. /* set LDB0, LDB1 clk select to 011/011 */
  400. reg = readl(&mxc_ccm->cs2cdr);
  401. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  402. | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  403. reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  404. | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  405. writel(reg, &mxc_ccm->cs2cdr);
  406. reg = readl(&mxc_ccm->cscmr2);
  407. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
  408. writel(reg, &mxc_ccm->cscmr2);
  409. reg = readl(&mxc_ccm->chsccdr);
  410. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  411. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  412. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  413. << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
  414. writel(reg, &mxc_ccm->chsccdr);
  415. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  416. | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
  417. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  418. | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  419. | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  420. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  421. | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  422. | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
  423. | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
  424. writel(reg, &iomux->gpr[2]);
  425. reg = readl(&iomux->gpr[3]);
  426. reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
  427. | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  428. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  429. << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
  430. writel(reg, &iomux->gpr[3]);
  431. }
  432. #endif /* CONFIG_VIDEO_IPUV3 */
  433. /*
  434. * Do not overwrite the console
  435. * Use always serial for U-Boot console
  436. */
  437. int overwrite_console(void)
  438. {
  439. return 1;
  440. }
  441. int board_eth_init(bd_t *bis)
  442. {
  443. setup_iomux_enet();
  444. setup_pcie();
  445. return cpu_eth_init(bis);
  446. }
  447. #ifdef CONFIG_USB_EHCI_MX6
  448. static void setup_usb(void)
  449. {
  450. /*
  451. * set daisy chain for otg_pin_id on 6q.
  452. * for 6dl, this bit is reserved
  453. */
  454. imx_iomux_set_gpr_register(1, 13, 1, 0);
  455. }
  456. #endif
  457. int board_early_init_f(void)
  458. {
  459. setup_iomux_uart();
  460. return 0;
  461. }
  462. int board_init(void)
  463. {
  464. /* address of boot parameters */
  465. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  466. #ifdef CONFIG_MXC_SPI
  467. setup_spi();
  468. #endif
  469. if (is_mx6dq() || is_mx6dqp())
  470. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
  471. else
  472. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
  473. #if defined(CONFIG_VIDEO_IPUV3)
  474. setup_display();
  475. #endif
  476. #ifdef CONFIG_USB_EHCI_MX6
  477. setup_usb();
  478. #endif
  479. return 0;
  480. }
  481. int power_init_board(void)
  482. {
  483. struct pmic *p;
  484. unsigned int reg;
  485. int ret;
  486. p = pfuze_common_init(I2C_PMIC);
  487. if (!p)
  488. return -ENODEV;
  489. ret = pfuze_mode_init(p, APS_PFM);
  490. if (ret < 0)
  491. return ret;
  492. /* Increase VGEN3 from 2.5 to 2.8V */
  493. pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
  494. reg &= ~LDO_VOL_MASK;
  495. reg |= LDOB_2_80V;
  496. pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
  497. /* Increase VGEN5 from 2.8 to 3V */
  498. pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
  499. reg &= ~LDO_VOL_MASK;
  500. reg |= LDOB_3_00V;
  501. pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
  502. return 0;
  503. }
  504. #ifdef CONFIG_MXC_SPI
  505. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  506. {
  507. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
  508. }
  509. #endif
  510. #ifdef CONFIG_CMD_BMODE
  511. static const struct boot_mode board_boot_modes[] = {
  512. /* 4 bit bus width */
  513. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  514. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  515. /* 8 bit bus width */
  516. {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
  517. {NULL, 0},
  518. };
  519. #endif
  520. int board_late_init(void)
  521. {
  522. #ifdef CONFIG_CMD_BMODE
  523. add_board_boot_modes(board_boot_modes);
  524. #endif
  525. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  526. env_set("board_name", "SABRESD");
  527. if (is_mx6dqp())
  528. env_set("board_rev", "MX6QP");
  529. else if (is_mx6dq())
  530. env_set("board_rev", "MX6Q");
  531. else if (is_mx6sdl())
  532. env_set("board_rev", "MX6DL");
  533. #endif
  534. return 0;
  535. }
  536. int checkboard(void)
  537. {
  538. puts("Board: MX6-SabreSD\n");
  539. return 0;
  540. }
  541. #ifdef CONFIG_SPL_BUILD
  542. #include <asm/arch/mx6-ddr.h>
  543. #include <spl.h>
  544. #include <linux/libfdt.h>
  545. #ifdef CONFIG_SPL_OS_BOOT
  546. int spl_start_uboot(void)
  547. {
  548. gpio_request(KEY_VOL_UP, "KEY Volume UP");
  549. gpio_direction_input(KEY_VOL_UP);
  550. /* Only enter in Falcon mode if KEY_VOL_UP is pressed */
  551. return gpio_get_value(KEY_VOL_UP);
  552. }
  553. #endif
  554. static void ccgr_init(void)
  555. {
  556. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  557. writel(0x00C03F3F, &ccm->CCGR0);
  558. writel(0x0030FC03, &ccm->CCGR1);
  559. writel(0x0FFFC000, &ccm->CCGR2);
  560. writel(0x3FF00000, &ccm->CCGR3);
  561. writel(0x00FFF300, &ccm->CCGR4);
  562. writel(0x0F0000C3, &ccm->CCGR5);
  563. writel(0x000003FF, &ccm->CCGR6);
  564. }
  565. static int mx6q_dcd_table[] = {
  566. 0x020e0798, 0x000C0000,
  567. 0x020e0758, 0x00000000,
  568. 0x020e0588, 0x00000030,
  569. 0x020e0594, 0x00000030,
  570. 0x020e056c, 0x00000030,
  571. 0x020e0578, 0x00000030,
  572. 0x020e074c, 0x00000030,
  573. 0x020e057c, 0x00000030,
  574. 0x020e058c, 0x00000000,
  575. 0x020e059c, 0x00000030,
  576. 0x020e05a0, 0x00000030,
  577. 0x020e078c, 0x00000030,
  578. 0x020e0750, 0x00020000,
  579. 0x020e05a8, 0x00000030,
  580. 0x020e05b0, 0x00000030,
  581. 0x020e0524, 0x00000030,
  582. 0x020e051c, 0x00000030,
  583. 0x020e0518, 0x00000030,
  584. 0x020e050c, 0x00000030,
  585. 0x020e05b8, 0x00000030,
  586. 0x020e05c0, 0x00000030,
  587. 0x020e0774, 0x00020000,
  588. 0x020e0784, 0x00000030,
  589. 0x020e0788, 0x00000030,
  590. 0x020e0794, 0x00000030,
  591. 0x020e079c, 0x00000030,
  592. 0x020e07a0, 0x00000030,
  593. 0x020e07a4, 0x00000030,
  594. 0x020e07a8, 0x00000030,
  595. 0x020e0748, 0x00000030,
  596. 0x020e05ac, 0x00000030,
  597. 0x020e05b4, 0x00000030,
  598. 0x020e0528, 0x00000030,
  599. 0x020e0520, 0x00000030,
  600. 0x020e0514, 0x00000030,
  601. 0x020e0510, 0x00000030,
  602. 0x020e05bc, 0x00000030,
  603. 0x020e05c4, 0x00000030,
  604. 0x021b0800, 0xa1390003,
  605. 0x021b080c, 0x001F001F,
  606. 0x021b0810, 0x001F001F,
  607. 0x021b480c, 0x001F001F,
  608. 0x021b4810, 0x001F001F,
  609. 0x021b083c, 0x43270338,
  610. 0x021b0840, 0x03200314,
  611. 0x021b483c, 0x431A032F,
  612. 0x021b4840, 0x03200263,
  613. 0x021b0848, 0x4B434748,
  614. 0x021b4848, 0x4445404C,
  615. 0x021b0850, 0x38444542,
  616. 0x021b4850, 0x4935493A,
  617. 0x021b081c, 0x33333333,
  618. 0x021b0820, 0x33333333,
  619. 0x021b0824, 0x33333333,
  620. 0x021b0828, 0x33333333,
  621. 0x021b481c, 0x33333333,
  622. 0x021b4820, 0x33333333,
  623. 0x021b4824, 0x33333333,
  624. 0x021b4828, 0x33333333,
  625. 0x021b08b8, 0x00000800,
  626. 0x021b48b8, 0x00000800,
  627. 0x021b0004, 0x00020036,
  628. 0x021b0008, 0x09444040,
  629. 0x021b000c, 0x555A7975,
  630. 0x021b0010, 0xFF538F64,
  631. 0x021b0014, 0x01FF00DB,
  632. 0x021b0018, 0x00001740,
  633. 0x021b001c, 0x00008000,
  634. 0x021b002c, 0x000026d2,
  635. 0x021b0030, 0x005A1023,
  636. 0x021b0040, 0x00000027,
  637. 0x021b0000, 0x831A0000,
  638. 0x021b001c, 0x04088032,
  639. 0x021b001c, 0x00008033,
  640. 0x021b001c, 0x00048031,
  641. 0x021b001c, 0x09408030,
  642. 0x021b001c, 0x04008040,
  643. 0x021b0020, 0x00005800,
  644. 0x021b0818, 0x00011117,
  645. 0x021b4818, 0x00011117,
  646. 0x021b0004, 0x00025576,
  647. 0x021b0404, 0x00011006,
  648. 0x021b001c, 0x00000000,
  649. };
  650. static int mx6qp_dcd_table[] = {
  651. 0x020e0798, 0x000c0000,
  652. 0x020e0758, 0x00000000,
  653. 0x020e0588, 0x00000030,
  654. 0x020e0594, 0x00000030,
  655. 0x020e056c, 0x00000030,
  656. 0x020e0578, 0x00000030,
  657. 0x020e074c, 0x00000030,
  658. 0x020e057c, 0x00000030,
  659. 0x020e058c, 0x00000000,
  660. 0x020e059c, 0x00000030,
  661. 0x020e05a0, 0x00000030,
  662. 0x020e078c, 0x00000030,
  663. 0x020e0750, 0x00020000,
  664. 0x020e05a8, 0x00000030,
  665. 0x020e05b0, 0x00000030,
  666. 0x020e0524, 0x00000030,
  667. 0x020e051c, 0x00000030,
  668. 0x020e0518, 0x00000030,
  669. 0x020e050c, 0x00000030,
  670. 0x020e05b8, 0x00000030,
  671. 0x020e05c0, 0x00000030,
  672. 0x020e0774, 0x00020000,
  673. 0x020e0784, 0x00000030,
  674. 0x020e0788, 0x00000030,
  675. 0x020e0794, 0x00000030,
  676. 0x020e079c, 0x00000030,
  677. 0x020e07a0, 0x00000030,
  678. 0x020e07a4, 0x00000030,
  679. 0x020e07a8, 0x00000030,
  680. 0x020e0748, 0x00000030,
  681. 0x020e05ac, 0x00000030,
  682. 0x020e05b4, 0x00000030,
  683. 0x020e0528, 0x00000030,
  684. 0x020e0520, 0x00000030,
  685. 0x020e0514, 0x00000030,
  686. 0x020e0510, 0x00000030,
  687. 0x020e05bc, 0x00000030,
  688. 0x020e05c4, 0x00000030,
  689. 0x021b0800, 0xa1390003,
  690. 0x021b080c, 0x001b001e,
  691. 0x021b0810, 0x002e0029,
  692. 0x021b480c, 0x001b002a,
  693. 0x021b4810, 0x0019002c,
  694. 0x021b083c, 0x43240334,
  695. 0x021b0840, 0x0324031a,
  696. 0x021b483c, 0x43340344,
  697. 0x021b4840, 0x03280276,
  698. 0x021b0848, 0x44383A3E,
  699. 0x021b4848, 0x3C3C3846,
  700. 0x021b0850, 0x2e303230,
  701. 0x021b4850, 0x38283E34,
  702. 0x021b081c, 0x33333333,
  703. 0x021b0820, 0x33333333,
  704. 0x021b0824, 0x33333333,
  705. 0x021b0828, 0x33333333,
  706. 0x021b481c, 0x33333333,
  707. 0x021b4820, 0x33333333,
  708. 0x021b4824, 0x33333333,
  709. 0x021b4828, 0x33333333,
  710. 0x021b08c0, 0x24912249,
  711. 0x021b48c0, 0x24914289,
  712. 0x021b08b8, 0x00000800,
  713. 0x021b48b8, 0x00000800,
  714. 0x021b0004, 0x00020036,
  715. 0x021b0008, 0x24444040,
  716. 0x021b000c, 0x555A7955,
  717. 0x021b0010, 0xFF320F64,
  718. 0x021b0014, 0x01ff00db,
  719. 0x021b0018, 0x00001740,
  720. 0x021b001c, 0x00008000,
  721. 0x021b002c, 0x000026d2,
  722. 0x021b0030, 0x005A1023,
  723. 0x021b0040, 0x00000027,
  724. 0x021b0400, 0x14420000,
  725. 0x021b0000, 0x831A0000,
  726. 0x021b0890, 0x00400C58,
  727. 0x00bb0008, 0x00000000,
  728. 0x00bb000c, 0x2891E41A,
  729. 0x00bb0038, 0x00000564,
  730. 0x00bb0014, 0x00000040,
  731. 0x00bb0028, 0x00000020,
  732. 0x00bb002c, 0x00000020,
  733. 0x021b001c, 0x04088032,
  734. 0x021b001c, 0x00008033,
  735. 0x021b001c, 0x00048031,
  736. 0x021b001c, 0x09408030,
  737. 0x021b001c, 0x04008040,
  738. 0x021b0020, 0x00005800,
  739. 0x021b0818, 0x00011117,
  740. 0x021b4818, 0x00011117,
  741. 0x021b0004, 0x00025576,
  742. 0x021b0404, 0x00011006,
  743. 0x021b001c, 0x00000000,
  744. };
  745. static int mx6dl_dcd_table[] = {
  746. 0x020e0774, 0x000C0000,
  747. 0x020e0754, 0x00000000,
  748. 0x020e04ac, 0x00000030,
  749. 0x020e04b0, 0x00000030,
  750. 0x020e0464, 0x00000030,
  751. 0x020e0490, 0x00000030,
  752. 0x020e074c, 0x00000030,
  753. 0x020e0494, 0x00000030,
  754. 0x020e04a0, 0x00000000,
  755. 0x020e04b4, 0x00000030,
  756. 0x020e04b8, 0x00000030,
  757. 0x020e076c, 0x00000030,
  758. 0x020e0750, 0x00020000,
  759. 0x020e04bc, 0x00000030,
  760. 0x020e04c0, 0x00000030,
  761. 0x020e04c4, 0x00000030,
  762. 0x020e04c8, 0x00000030,
  763. 0x020e04cc, 0x00000030,
  764. 0x020e04d0, 0x00000030,
  765. 0x020e04d4, 0x00000030,
  766. 0x020e04d8, 0x00000030,
  767. 0x020e0760, 0x00020000,
  768. 0x020e0764, 0x00000030,
  769. 0x020e0770, 0x00000030,
  770. 0x020e0778, 0x00000030,
  771. 0x020e077c, 0x00000030,
  772. 0x020e0780, 0x00000030,
  773. 0x020e0784, 0x00000030,
  774. 0x020e078c, 0x00000030,
  775. 0x020e0748, 0x00000030,
  776. 0x020e0470, 0x00000030,
  777. 0x020e0474, 0x00000030,
  778. 0x020e0478, 0x00000030,
  779. 0x020e047c, 0x00000030,
  780. 0x020e0480, 0x00000030,
  781. 0x020e0484, 0x00000030,
  782. 0x020e0488, 0x00000030,
  783. 0x020e048c, 0x00000030,
  784. 0x021b0800, 0xa1390003,
  785. 0x021b080c, 0x001F001F,
  786. 0x021b0810, 0x001F001F,
  787. 0x021b480c, 0x001F001F,
  788. 0x021b4810, 0x001F001F,
  789. 0x021b083c, 0x4220021F,
  790. 0x021b0840, 0x0207017E,
  791. 0x021b483c, 0x4201020C,
  792. 0x021b4840, 0x01660172,
  793. 0x021b0848, 0x4A4D4E4D,
  794. 0x021b4848, 0x4A4F5049,
  795. 0x021b0850, 0x3F3C3D31,
  796. 0x021b4850, 0x3238372B,
  797. 0x021b081c, 0x33333333,
  798. 0x021b0820, 0x33333333,
  799. 0x021b0824, 0x33333333,
  800. 0x021b0828, 0x33333333,
  801. 0x021b481c, 0x33333333,
  802. 0x021b4820, 0x33333333,
  803. 0x021b4824, 0x33333333,
  804. 0x021b4828, 0x33333333,
  805. 0x021b08b8, 0x00000800,
  806. 0x021b48b8, 0x00000800,
  807. 0x021b0004, 0x0002002D,
  808. 0x021b0008, 0x00333030,
  809. 0x021b000c, 0x3F435313,
  810. 0x021b0010, 0xB66E8B63,
  811. 0x021b0014, 0x01FF00DB,
  812. 0x021b0018, 0x00001740,
  813. 0x021b001c, 0x00008000,
  814. 0x021b002c, 0x000026d2,
  815. 0x021b0030, 0x00431023,
  816. 0x021b0040, 0x00000027,
  817. 0x021b0000, 0x831A0000,
  818. 0x021b001c, 0x04008032,
  819. 0x021b001c, 0x00008033,
  820. 0x021b001c, 0x00048031,
  821. 0x021b001c, 0x05208030,
  822. 0x021b001c, 0x04008040,
  823. 0x021b0020, 0x00005800,
  824. 0x021b0818, 0x00011117,
  825. 0x021b4818, 0x00011117,
  826. 0x021b0004, 0x0002556D,
  827. 0x021b0404, 0x00011006,
  828. 0x021b001c, 0x00000000,
  829. };
  830. static void ddr_init(int *table, int size)
  831. {
  832. int i;
  833. for (i = 0; i < size / 2 ; i++)
  834. writel(table[2 * i + 1], table[2 * i]);
  835. }
  836. static void spl_dram_init(void)
  837. {
  838. if (is_mx6dq())
  839. ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
  840. else if (is_mx6dqp())
  841. ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
  842. else if (is_mx6sdl())
  843. ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
  844. }
  845. void board_init_f(ulong dummy)
  846. {
  847. /* DDR initialization */
  848. spl_dram_init();
  849. /* setup AIPS and disable watchdog */
  850. arch_cpu_init();
  851. ccgr_init();
  852. gpr_init();
  853. /* iomux and setup of i2c */
  854. board_early_init_f();
  855. /* setup GP timer */
  856. timer_init();
  857. /* UART clocks enabled and gd valid - init serial console */
  858. preloader_console_init();
  859. /* Clear the BSS. */
  860. memset(__bss_start, 0, __bss_end - __bss_start);
  861. /* load/boot image from boot device */
  862. board_init_r(NULL, 0);
  863. }
  864. #endif
  865. #ifdef CONFIG_SPL_LOAD_FIT
  866. int board_fit_config_name_match(const char *name)
  867. {
  868. if (is_mx6dq()) {
  869. if (!strcmp(name, "imx6q-sabresd"))
  870. return 0;
  871. } else if (is_mx6dqp()) {
  872. if (!strcmp(name, "imx6qp-sabresd"))
  873. return 0;
  874. } else if (is_mx6dl()) {
  875. if (!strcmp(name, "imx6dl-sabresd"))
  876. return 0;
  877. }
  878. return -1;
  879. }
  880. #endif