mx53loco.c 9.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  4. * Jason Liu <r64343@freescale.com>
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/sys_proto.h>
  10. #include <asm/arch/crm_regs.h>
  11. #include <asm/arch/clock.h>
  12. #include <asm/arch/iomux-mx53.h>
  13. #include <asm/arch/clock.h>
  14. #include <linux/errno.h>
  15. #include <asm/mach-imx/mx5_video.h>
  16. #include <netdev.h>
  17. #include <i2c.h>
  18. #include <input.h>
  19. #include <mmc.h>
  20. #include <fsl_esdhc_imx.h>
  21. #include <asm/gpio.h>
  22. #include <power/pmic.h>
  23. #include <dialog_pmic.h>
  24. #include <fsl_pmic.h>
  25. #include <linux/fb.h>
  26. #include <ipu_pixfmt.h>
  27. #define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24)
  28. DECLARE_GLOBAL_DATA_PTR;
  29. u32 get_board_rev(void)
  30. {
  31. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  32. struct fuse_bank *bank = &iim->bank[0];
  33. struct fuse_bank0_regs *fuse =
  34. (struct fuse_bank0_regs *)bank->fuse_regs;
  35. int rev = readl(&fuse->gp[6]);
  36. if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR))
  37. rev = 0;
  38. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  39. }
  40. #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  41. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  42. static void setup_iomux_uart(void)
  43. {
  44. static const iomux_v3_cfg_t uart_pads[] = {
  45. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
  46. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
  47. };
  48. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  49. }
  50. #ifdef CONFIG_USB_EHCI_MX5
  51. int board_ehci_hcd_init(int port)
  52. {
  53. /* request VBUS power enable pin, GPIO7_8 */
  54. imx_iomux_v3_setup_pad(MX53_PAD_PATA_DA_2__GPIO7_8);
  55. gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
  56. return 0;
  57. }
  58. #endif
  59. static void setup_iomux_fec(void)
  60. {
  61. static const iomux_v3_cfg_t fec_pads[] = {
  62. NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
  63. PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
  64. NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
  65. NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
  66. PAD_CTL_HYS | PAD_CTL_PKE),
  67. NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
  68. PAD_CTL_HYS | PAD_CTL_PKE),
  69. NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
  70. NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
  71. NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
  72. NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
  73. PAD_CTL_HYS | PAD_CTL_PKE),
  74. NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
  75. PAD_CTL_HYS | PAD_CTL_PKE),
  76. NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
  77. PAD_CTL_HYS | PAD_CTL_PKE),
  78. };
  79. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  80. }
  81. #ifdef CONFIG_FSL_ESDHC_IMX
  82. struct fsl_esdhc_cfg esdhc_cfg[2] = {
  83. {MMC_SDHC1_BASE_ADDR},
  84. {MMC_SDHC3_BASE_ADDR},
  85. };
  86. int board_mmc_getcd(struct mmc *mmc)
  87. {
  88. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  89. int ret;
  90. imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
  91. gpio_direction_input(IMX_GPIO_NR(3, 11));
  92. imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
  93. gpio_direction_input(IMX_GPIO_NR(3, 13));
  94. if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  95. ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
  96. else
  97. ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
  98. return ret;
  99. }
  100. #define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
  101. PAD_CTL_PUS_100K_UP)
  102. #define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
  103. PAD_CTL_DSE_HIGH)
  104. int board_mmc_init(bd_t *bis)
  105. {
  106. static const iomux_v3_cfg_t sd1_pads[] = {
  107. NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
  108. NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
  109. NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
  110. NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
  111. NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
  112. NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
  113. MX53_PAD_EIM_DA13__GPIO3_13,
  114. };
  115. static const iomux_v3_cfg_t sd2_pads[] = {
  116. NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
  117. SD_CMD_PAD_CTRL),
  118. NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
  119. NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
  120. NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
  121. NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
  122. NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
  123. NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
  124. NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
  125. NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
  126. NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
  127. MX53_PAD_EIM_DA11__GPIO3_11,
  128. };
  129. u32 index;
  130. int ret;
  131. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  132. esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  133. for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
  134. switch (index) {
  135. case 0:
  136. imx_iomux_v3_setup_multiple_pads(sd1_pads,
  137. ARRAY_SIZE(sd1_pads));
  138. break;
  139. case 1:
  140. imx_iomux_v3_setup_multiple_pads(sd2_pads,
  141. ARRAY_SIZE(sd2_pads));
  142. break;
  143. default:
  144. printf("Warning: you configured more ESDHC controller"
  145. "(%d) as supported by the board(2)\n",
  146. CONFIG_SYS_FSL_ESDHC_NUM);
  147. return -EINVAL;
  148. }
  149. ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  150. if (ret)
  151. return ret;
  152. }
  153. return 0;
  154. }
  155. #endif
  156. #define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
  157. PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
  158. static void setup_iomux_i2c(void)
  159. {
  160. static const iomux_v3_cfg_t i2c1_pads[] = {
  161. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
  162. NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
  163. };
  164. imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
  165. }
  166. static int power_init(void)
  167. {
  168. unsigned int val;
  169. int ret;
  170. struct pmic *p;
  171. if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
  172. ret = pmic_dialog_init(I2C_PMIC);
  173. if (ret)
  174. return ret;
  175. p = pmic_get("DIALOG_PMIC");
  176. if (!p)
  177. return -ENODEV;
  178. env_set("fdt_file", "imx53-qsb.dtb");
  179. /* Set VDDA to 1.25V */
  180. val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
  181. ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
  182. if (ret) {
  183. printf("Writing to BUCKCORE_REG failed: %d\n", ret);
  184. return ret;
  185. }
  186. pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
  187. val |= DA9052_SUPPLY_VBCOREGO;
  188. ret = pmic_reg_write(p, DA9053_SUPPLY_REG, val);
  189. if (ret) {
  190. printf("Writing to SUPPLY_REG failed: %d\n", ret);
  191. return ret;
  192. }
  193. /* Set Vcc peripheral to 1.30V */
  194. ret = pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
  195. if (ret) {
  196. printf("Writing to BUCKPRO_REG failed: %d\n", ret);
  197. return ret;
  198. }
  199. ret = pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
  200. if (ret) {
  201. printf("Writing to SUPPLY_REG failed: %d\n", ret);
  202. return ret;
  203. }
  204. return ret;
  205. }
  206. if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
  207. ret = pmic_init(I2C_0);
  208. if (ret)
  209. return ret;
  210. p = pmic_get("FSL_PMIC");
  211. if (!p)
  212. return -ENODEV;
  213. env_set("fdt_file", "imx53-qsrb.dtb");
  214. /* Set VDDGP to 1.25V for 1GHz on SW1 */
  215. pmic_reg_read(p, REG_SW_0, &val);
  216. val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
  217. ret = pmic_reg_write(p, REG_SW_0, val);
  218. if (ret) {
  219. printf("Writing to REG_SW_0 failed: %d\n", ret);
  220. return ret;
  221. }
  222. /* Set VCC as 1.30V on SW2 */
  223. pmic_reg_read(p, REG_SW_1, &val);
  224. val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
  225. ret = pmic_reg_write(p, REG_SW_1, val);
  226. if (ret) {
  227. printf("Writing to REG_SW_1 failed: %d\n", ret);
  228. return ret;
  229. }
  230. /* Set global reset timer to 4s */
  231. pmic_reg_read(p, REG_POWER_CTL2, &val);
  232. val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
  233. ret = pmic_reg_write(p, REG_POWER_CTL2, val);
  234. if (ret) {
  235. printf("Writing to REG_POWER_CTL2 failed: %d\n", ret);
  236. return ret;
  237. }
  238. /* Set VUSBSEL and VUSBEN for USB PHY supply*/
  239. pmic_reg_read(p, REG_MODE_0, &val);
  240. val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
  241. ret = pmic_reg_write(p, REG_MODE_0, val);
  242. if (ret) {
  243. printf("Writing to REG_MODE_0 failed: %d\n", ret);
  244. return ret;
  245. }
  246. /* Set SWBST to 5V in auto mode */
  247. val = SWBST_AUTO;
  248. ret = pmic_reg_write(p, SWBST_CTRL, val);
  249. if (ret) {
  250. printf("Writing to SWBST_CTRL failed: %d\n", ret);
  251. return ret;
  252. }
  253. return ret;
  254. }
  255. return -1;
  256. }
  257. static void clock_1GHz(void)
  258. {
  259. int ret;
  260. u32 ref_clk = MXC_HCLK;
  261. /*
  262. * After increasing voltage to 1.25V, we can switch
  263. * CPU clock to 1GHz and DDR to 400MHz safely
  264. */
  265. ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
  266. if (ret)
  267. printf("CPU: Switch CPU clock to 1GHZ failed\n");
  268. ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
  269. ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
  270. if (ret)
  271. printf("CPU: Switch DDR clock to 400MHz failed\n");
  272. }
  273. int board_early_init_f(void)
  274. {
  275. setup_iomux_uart();
  276. setup_iomux_fec();
  277. setup_iomux_lcd();
  278. return 0;
  279. }
  280. /*
  281. * Do not overwrite the console
  282. * Use always serial for U-Boot console
  283. */
  284. int overwrite_console(void)
  285. {
  286. return 1;
  287. }
  288. int board_init(void)
  289. {
  290. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  291. mxc_set_sata_internal_clock();
  292. setup_iomux_i2c();
  293. return 0;
  294. }
  295. int board_late_init(void)
  296. {
  297. if (!power_init())
  298. clock_1GHz();
  299. return 0;
  300. }
  301. int checkboard(void)
  302. {
  303. puts("Board: MX53 LOCO\n");
  304. return 0;
  305. }