mx51evk.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/gpio.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/iomux-mx51.h>
  10. #include <linux/errno.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <asm/arch/crm_regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/mach-imx/mx5_video.h>
  15. #include <i2c.h>
  16. #include <input.h>
  17. #include <mmc.h>
  18. #include <fsl_esdhc_imx.h>
  19. #include <power/pmic.h>
  20. #include <fsl_pmic.h>
  21. #include <mc13892.h>
  22. #include <usb/ehci-ci.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #ifdef CONFIG_FSL_ESDHC_IMX
  25. struct fsl_esdhc_cfg esdhc_cfg[2] = {
  26. {MMC_SDHC1_BASE_ADDR},
  27. {MMC_SDHC2_BASE_ADDR},
  28. };
  29. #endif
  30. int dram_init(void)
  31. {
  32. /* dram_init must store complete ramsize in gd->ram_size */
  33. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  34. PHYS_SDRAM_1_SIZE);
  35. return 0;
  36. }
  37. u32 get_board_rev(void)
  38. {
  39. u32 rev = get_cpu_rev();
  40. if (!gpio_get_value(IMX_GPIO_NR(1, 22)))
  41. rev |= BOARD_REV_2_0 << BOARD_VER_OFFSET;
  42. return rev;
  43. }
  44. #define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH)
  45. static void setup_iomux_uart(void)
  46. {
  47. static const iomux_v3_cfg_t uart_pads[] = {
  48. MX51_PAD_UART1_RXD__UART1_RXD,
  49. MX51_PAD_UART1_TXD__UART1_TXD,
  50. NEW_PAD_CTRL(MX51_PAD_UART1_RTS__UART1_RTS, UART_PAD_CTRL),
  51. NEW_PAD_CTRL(MX51_PAD_UART1_CTS__UART1_CTS, UART_PAD_CTRL),
  52. };
  53. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  54. }
  55. static void setup_iomux_fec(void)
  56. {
  57. static const iomux_v3_cfg_t fec_pads[] = {
  58. NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
  59. PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
  60. PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  61. MX51_PAD_NANDF_CS3__FEC_MDC,
  62. NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
  63. NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
  64. NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
  65. MX51_PAD_NANDF_D9__FEC_RDATA0,
  66. MX51_PAD_NANDF_CS6__FEC_TDATA3,
  67. MX51_PAD_NANDF_CS5__FEC_TDATA2,
  68. MX51_PAD_NANDF_CS4__FEC_TDATA1,
  69. MX51_PAD_NANDF_D8__FEC_TDATA0,
  70. MX51_PAD_NANDF_CS7__FEC_TX_EN,
  71. MX51_PAD_NANDF_CS2__FEC_TX_ER,
  72. MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
  73. NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
  74. NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
  75. MX51_PAD_EIM_CS5__FEC_CRS,
  76. MX51_PAD_EIM_CS4__FEC_RX_ER,
  77. NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
  78. };
  79. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  80. }
  81. #ifdef CONFIG_MXC_SPI
  82. static void setup_iomux_spi(void)
  83. {
  84. static const iomux_v3_cfg_t spi_pads[] = {
  85. NEW_PAD_CTRL(MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, PAD_CTL_HYS |
  86. PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  87. NEW_PAD_CTRL(MX51_PAD_CSPI1_MISO__ECSPI1_MISO, PAD_CTL_HYS |
  88. PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  89. NEW_PAD_CTRL(MX51_PAD_CSPI1_SS1__ECSPI1_SS1,
  90. MX51_GPIO_PAD_CTRL),
  91. MX51_PAD_CSPI1_SS0__ECSPI1_SS0,
  92. NEW_PAD_CTRL(MX51_PAD_CSPI1_RDY__ECSPI1_RDY, MX51_PAD_CTRL_2),
  93. NEW_PAD_CTRL(MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, PAD_CTL_HYS |
  94. PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
  95. };
  96. imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
  97. }
  98. #endif
  99. #ifdef CONFIG_USB_EHCI_MX5
  100. #define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7)
  101. #define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27)
  102. #define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1)
  103. #define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5)
  104. static void setup_usb_h1(void)
  105. {
  106. static const iomux_v3_cfg_t usb_h1_pads[] = {
  107. MX51_PAD_USBH1_CLK__USBH1_CLK,
  108. MX51_PAD_USBH1_DIR__USBH1_DIR,
  109. MX51_PAD_USBH1_STP__USBH1_STP,
  110. MX51_PAD_USBH1_NXT__USBH1_NXT,
  111. MX51_PAD_USBH1_DATA0__USBH1_DATA0,
  112. MX51_PAD_USBH1_DATA1__USBH1_DATA1,
  113. MX51_PAD_USBH1_DATA2__USBH1_DATA2,
  114. MX51_PAD_USBH1_DATA3__USBH1_DATA3,
  115. MX51_PAD_USBH1_DATA4__USBH1_DATA4,
  116. MX51_PAD_USBH1_DATA5__USBH1_DATA5,
  117. MX51_PAD_USBH1_DATA6__USBH1_DATA6,
  118. MX51_PAD_USBH1_DATA7__USBH1_DATA7,
  119. NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
  120. MX51_PAD_EIM_D17__GPIO2_1,
  121. MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
  122. };
  123. imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
  124. }
  125. int board_ehci_hcd_init(int port)
  126. {
  127. /* Set USBH1_STP to GPIO and toggle it */
  128. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
  129. MX51_USBH_PAD_CTRL));
  130. gpio_direction_output(MX51EVK_USBH1_STP, 0);
  131. gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
  132. mdelay(10);
  133. gpio_set_value(MX51EVK_USBH1_STP, 1);
  134. /* Set back USBH1_STP to be function */
  135. imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
  136. /* De-assert USB PHY RESETB */
  137. gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
  138. /* Drive USB_CLK_EN_B line low */
  139. gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
  140. /* Reset USB hub */
  141. gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
  142. mdelay(2);
  143. gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
  144. return 0;
  145. }
  146. #endif
  147. static void power_init(void)
  148. {
  149. unsigned int val;
  150. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
  151. struct pmic *p;
  152. int ret;
  153. ret = pmic_init(CONFIG_FSL_PMIC_BUS);
  154. if (ret)
  155. return;
  156. p = pmic_get("FSL_PMIC");
  157. if (!p)
  158. return;
  159. /* Write needed to Power Gate 2 register */
  160. pmic_reg_read(p, REG_POWER_MISC, &val);
  161. val &= ~PWGT2SPIEN;
  162. pmic_reg_write(p, REG_POWER_MISC, val);
  163. /* Externally powered */
  164. pmic_reg_read(p, REG_CHARGE, &val);
  165. val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
  166. pmic_reg_write(p, REG_CHARGE, val);
  167. /* power up the system first */
  168. pmic_reg_write(p, REG_POWER_MISC, PWUP);
  169. /* Set core voltage to 1.1V */
  170. pmic_reg_read(p, REG_SW_0, &val);
  171. val = (val & ~SWx_VOLT_MASK) | SWx_1_100V;
  172. pmic_reg_write(p, REG_SW_0, val);
  173. /* Setup VCC (SW2) to 1.25 */
  174. pmic_reg_read(p, REG_SW_1, &val);
  175. val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
  176. pmic_reg_write(p, REG_SW_1, val);
  177. /* Setup 1V2_DIG1 (SW3) to 1.25 */
  178. pmic_reg_read(p, REG_SW_2, &val);
  179. val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
  180. pmic_reg_write(p, REG_SW_2, val);
  181. udelay(50);
  182. /* Raise the core frequency to 800MHz */
  183. writel(0x0, &mxc_ccm->cacrr);
  184. /* Set switchers in Auto in NORMAL mode & STANDBY mode */
  185. /* Setup the switcher mode for SW1 & SW2*/
  186. pmic_reg_read(p, REG_SW_4, &val);
  187. val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
  188. (SWMODE_MASK << SWMODE2_SHIFT)));
  189. val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
  190. (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
  191. pmic_reg_write(p, REG_SW_4, val);
  192. /* Setup the switcher mode for SW3 & SW4 */
  193. pmic_reg_read(p, REG_SW_5, &val);
  194. val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
  195. (SWMODE_MASK << SWMODE4_SHIFT)));
  196. val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
  197. (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
  198. pmic_reg_write(p, REG_SW_5, val);
  199. /* Set VDIG to 1.65V, VGEN3 to 1.8V, VCAM to 2.6V */
  200. pmic_reg_read(p, REG_SETTING_0, &val);
  201. val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
  202. val |= VDIG_1_65 | VGEN3_1_8 | VCAM_2_6;
  203. pmic_reg_write(p, REG_SETTING_0, val);
  204. /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
  205. pmic_reg_read(p, REG_SETTING_1, &val);
  206. val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
  207. val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775;
  208. pmic_reg_write(p, REG_SETTING_1, val);
  209. /* Configure VGEN3 and VCAM regulators to use external PNP */
  210. val = VGEN3CONFIG | VCAMCONFIG;
  211. pmic_reg_write(p, REG_MODE_1, val);
  212. udelay(200);
  213. /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
  214. val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
  215. VVIDEOEN | VAUDIOEN | VSDEN;
  216. pmic_reg_write(p, REG_MODE_1, val);
  217. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
  218. NO_PAD_CTRL));
  219. gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
  220. udelay(500);
  221. gpio_set_value(IMX_GPIO_NR(2, 14), 1);
  222. }
  223. #ifdef CONFIG_FSL_ESDHC_IMX
  224. int board_mmc_getcd(struct mmc *mmc)
  225. {
  226. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  227. int ret;
  228. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
  229. NO_PAD_CTRL));
  230. gpio_direction_input(IMX_GPIO_NR(1, 0));
  231. imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
  232. NO_PAD_CTRL));
  233. gpio_direction_input(IMX_GPIO_NR(1, 6));
  234. if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
  235. ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
  236. else
  237. ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
  238. return ret;
  239. }
  240. int board_mmc_init(bd_t *bis)
  241. {
  242. static const iomux_v3_cfg_t sd1_pads[] = {
  243. NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
  244. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  245. NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
  246. PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  247. NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
  248. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  249. NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
  250. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  251. NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
  252. PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
  253. NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
  254. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
  255. NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
  256. NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
  257. };
  258. static const iomux_v3_cfg_t sd2_pads[] = {
  259. NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
  260. PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
  261. NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
  262. PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
  263. NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
  264. PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
  265. NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
  266. PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
  267. NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
  268. PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
  269. NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
  270. PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
  271. NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
  272. NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
  273. };
  274. u32 index;
  275. int ret;
  276. esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  277. esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  278. for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
  279. index++) {
  280. switch (index) {
  281. case 0:
  282. imx_iomux_v3_setup_multiple_pads(sd1_pads,
  283. ARRAY_SIZE(sd1_pads));
  284. break;
  285. case 1:
  286. imx_iomux_v3_setup_multiple_pads(sd2_pads,
  287. ARRAY_SIZE(sd2_pads));
  288. break;
  289. default:
  290. printf("Warning: you configured more ESDHC controller"
  291. "(%d) as supported by the board(2)\n",
  292. CONFIG_SYS_FSL_ESDHC_NUM);
  293. return -EINVAL;
  294. }
  295. ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
  296. if (ret)
  297. return ret;
  298. }
  299. return 0;
  300. }
  301. #endif
  302. int board_early_init_f(void)
  303. {
  304. setup_iomux_uart();
  305. setup_iomux_fec();
  306. #ifdef CONFIG_USB_EHCI_MX5
  307. setup_usb_h1();
  308. #endif
  309. setup_iomux_lcd();
  310. return 0;
  311. }
  312. int board_init(void)
  313. {
  314. /* address of boot parameters */
  315. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  316. return 0;
  317. }
  318. #ifdef CONFIG_BOARD_LATE_INIT
  319. int board_late_init(void)
  320. {
  321. #ifdef CONFIG_MXC_SPI
  322. setup_iomux_spi();
  323. power_init();
  324. #endif
  325. return 0;
  326. }
  327. #endif
  328. /*
  329. * Do not overwrite the console
  330. * Use always serial for U-Boot console
  331. */
  332. int overwrite_console(void)
  333. {
  334. return 1;
  335. }
  336. int checkboard(void)
  337. {
  338. puts("Board: MX51EVK\n");
  339. return 0;
  340. }