mx35pdk.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
  4. *
  5. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  6. */
  7. #include <common.h>
  8. #include <asm/io.h>
  9. #include <linux/errno.h>
  10. #include <asm/arch/imx-regs.h>
  11. #include <asm/arch/crm_regs.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/iomux-mx35.h>
  14. #include <i2c.h>
  15. #include <power/pmic.h>
  16. #include <fsl_pmic.h>
  17. #include <mmc.h>
  18. #include <fsl_esdhc_imx.h>
  19. #include <mc9sdz60.h>
  20. #include <mc13892.h>
  21. #include <linux/types.h>
  22. #include <asm/gpio.h>
  23. #include <asm/arch/sys_proto.h>
  24. #include <netdev.h>
  25. #include <asm/mach-types.h>
  26. #ifndef CONFIG_BOARD_LATE_INIT
  27. #error "CONFIG_BOARD_LATE_INIT must be set for this board"
  28. #endif
  29. #ifndef CONFIG_BOARD_EARLY_INIT_F
  30. #error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
  31. #endif
  32. DECLARE_GLOBAL_DATA_PTR;
  33. int dram_init(void)
  34. {
  35. u32 size1, size2;
  36. size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  37. size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  38. gd->ram_size = size1 + size2;
  39. return 0;
  40. }
  41. int dram_init_banksize(void)
  42. {
  43. gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  44. gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  45. gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  46. gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  47. return 0;
  48. }
  49. #define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
  50. static void setup_iomux_i2c(void)
  51. {
  52. static const iomux_v3_cfg_t i2c1_pads[] = {
  53. NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
  54. NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
  55. };
  56. /* setup pins for I2C1 */
  57. imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
  58. }
  59. static void setup_iomux_spi(void)
  60. {
  61. static const iomux_v3_cfg_t spi_pads[] = {
  62. MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
  63. MX35_PAD_CSPI1_MISO__CSPI1_MISO,
  64. MX35_PAD_CSPI1_SS0__CSPI1_SS0,
  65. MX35_PAD_CSPI1_SS1__CSPI1_SS1,
  66. MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
  67. };
  68. imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
  69. }
  70. #define USBOTG_IN_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | \
  71. PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  72. #define USBOTG_OUT_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  73. static void setup_iomux_usbotg(void)
  74. {
  75. static const iomux_v3_cfg_t usbotg_pads[] = {
  76. NEW_PAD_CTRL(MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
  77. USBOTG_OUT_PAD_CTRL),
  78. NEW_PAD_CTRL(MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
  79. USBOTG_IN_PAD_CTRL),
  80. };
  81. /* Set up pins for USBOTG. */
  82. imx_iomux_v3_setup_multiple_pads(usbotg_pads, ARRAY_SIZE(usbotg_pads));
  83. }
  84. #define FEC_PAD_CTRL (PAD_CTL_DSE_LOW | PAD_CTL_SRE_SLOW)
  85. static void setup_iomux_fec(void)
  86. {
  87. static const iomux_v3_cfg_t fec_pads[] = {
  88. NEW_PAD_CTRL(MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, FEC_PAD_CTRL |
  89. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  90. NEW_PAD_CTRL(MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, FEC_PAD_CTRL |
  91. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  92. NEW_PAD_CTRL(MX35_PAD_FEC_RX_DV__FEC_RX_DV, FEC_PAD_CTRL |
  93. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  94. NEW_PAD_CTRL(MX35_PAD_FEC_COL__FEC_COL, FEC_PAD_CTRL |
  95. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  96. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA0__FEC_RDATA_0, FEC_PAD_CTRL |
  97. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  98. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA0__FEC_TDATA_0, FEC_PAD_CTRL),
  99. NEW_PAD_CTRL(MX35_PAD_FEC_TX_EN__FEC_TX_EN, FEC_PAD_CTRL),
  100. NEW_PAD_CTRL(MX35_PAD_FEC_MDC__FEC_MDC, FEC_PAD_CTRL),
  101. NEW_PAD_CTRL(MX35_PAD_FEC_MDIO__FEC_MDIO, FEC_PAD_CTRL |
  102. PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
  103. NEW_PAD_CTRL(MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, FEC_PAD_CTRL),
  104. NEW_PAD_CTRL(MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, FEC_PAD_CTRL |
  105. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  106. NEW_PAD_CTRL(MX35_PAD_FEC_CRS__FEC_CRS, FEC_PAD_CTRL |
  107. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  108. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA1__FEC_RDATA_1, FEC_PAD_CTRL |
  109. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  110. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA1__FEC_TDATA_1, FEC_PAD_CTRL),
  111. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA2__FEC_RDATA_2, FEC_PAD_CTRL |
  112. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  113. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA2__FEC_TDATA_2, FEC_PAD_CTRL),
  114. NEW_PAD_CTRL(MX35_PAD_FEC_RDATA3__FEC_RDATA_3, FEC_PAD_CTRL |
  115. PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
  116. NEW_PAD_CTRL(MX35_PAD_FEC_TDATA3__FEC_TDATA_3, FEC_PAD_CTRL),
  117. };
  118. /* setup pins for FEC */
  119. imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
  120. }
  121. int board_early_init_f(void)
  122. {
  123. struct ccm_regs *ccm =
  124. (struct ccm_regs *)IMX_CCM_BASE;
  125. /* enable clocks */
  126. writel(readl(&ccm->cgr0) |
  127. MXC_CCM_CGR0_EMI_MASK |
  128. MXC_CCM_CGR0_EDIO_MASK |
  129. MXC_CCM_CGR0_EPIT1_MASK,
  130. &ccm->cgr0);
  131. writel(readl(&ccm->cgr1) |
  132. MXC_CCM_CGR1_FEC_MASK |
  133. MXC_CCM_CGR1_GPIO1_MASK |
  134. MXC_CCM_CGR1_GPIO2_MASK |
  135. MXC_CCM_CGR1_GPIO3_MASK |
  136. MXC_CCM_CGR1_I2C1_MASK |
  137. MXC_CCM_CGR1_I2C2_MASK |
  138. MXC_CCM_CGR1_IPU_MASK,
  139. &ccm->cgr1);
  140. /* Setup NAND */
  141. __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
  142. setup_iomux_i2c();
  143. setup_iomux_usbotg();
  144. setup_iomux_fec();
  145. setup_iomux_spi();
  146. return 0;
  147. }
  148. int board_init(void)
  149. {
  150. gd->bd->bi_arch_number = MACH_TYPE_MX35_3DS; /* board id for linux */
  151. /* address of boot parameters */
  152. gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
  153. return 0;
  154. }
  155. static inline int pmic_detect(void)
  156. {
  157. unsigned int id;
  158. struct pmic *p = pmic_get("FSL_PMIC");
  159. if (!p)
  160. return -ENODEV;
  161. pmic_reg_read(p, REG_IDENTIFICATION, &id);
  162. id = (id >> 6) & 0x7;
  163. if (id == 0x7)
  164. return 1;
  165. return 0;
  166. }
  167. u32 get_board_rev(void)
  168. {
  169. int rev;
  170. rev = pmic_detect();
  171. return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
  172. }
  173. int board_late_init(void)
  174. {
  175. u8 val;
  176. u32 pmic_val;
  177. struct pmic *p;
  178. int ret;
  179. ret = pmic_init(I2C_0);
  180. if (ret)
  181. return ret;
  182. if (pmic_detect()) {
  183. p = pmic_get("FSL_PMIC");
  184. imx_iomux_v3_setup_pad(MX35_PAD_WDOG_RST__WDOG_WDOG_B);
  185. pmic_reg_read(p, REG_SETTING_0, &pmic_val);
  186. pmic_reg_write(p, REG_SETTING_0,
  187. pmic_val | VO_1_30V | VO_1_50V);
  188. pmic_reg_read(p, REG_MODE_0, &pmic_val);
  189. pmic_reg_write(p, REG_MODE_0, pmic_val | VGEN3EN);
  190. imx_iomux_v3_setup_pad(MX35_PAD_COMPARE__GPIO1_5);
  191. gpio_direction_output(IMX_GPIO_NR(1, 5), 1);
  192. }
  193. val = mc9sdz60_reg_read(MC9SDZ60_REG_GPIO_1) | 0x04;
  194. mc9sdz60_reg_write(MC9SDZ60_REG_GPIO_1, val);
  195. mdelay(200);
  196. val = mc9sdz60_reg_read(MC9SDZ60_REG_RESET_1) & 0x7F;
  197. mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
  198. mdelay(200);
  199. val |= 0x80;
  200. mc9sdz60_reg_write(MC9SDZ60_REG_RESET_1, val);
  201. /* Print board revision */
  202. printf("Board: MX35 PDK %d.0\n", ((get_board_rev() >> 8) + 1) & 0x0F);
  203. return 0;
  204. }
  205. int board_eth_init(bd_t *bis)
  206. {
  207. #if defined(CONFIG_SMC911X)
  208. int rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
  209. if (rc)
  210. return rc;
  211. #endif
  212. return cpu_eth_init(bis);
  213. }
  214. #if defined(CONFIG_FSL_ESDHC_IMX)
  215. struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR};
  216. int board_mmc_init(bd_t *bis)
  217. {
  218. static const iomux_v3_cfg_t sdhc1_pads[] = {
  219. MX35_PAD_SD1_CMD__ESDHC1_CMD,
  220. MX35_PAD_SD1_CLK__ESDHC1_CLK,
  221. MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
  222. MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
  223. MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
  224. MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
  225. };
  226. /* configure pins for SDHC1 only */
  227. imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
  228. esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  229. return fsl_esdhc_initialize(bis, &esdhc_cfg);
  230. }
  231. int board_mmc_getcd(struct mmc *mmc)
  232. {
  233. return !(mc9sdz60_reg_read(MC9SDZ60_REG_DES_FLAG) & 0x4);
  234. }
  235. #endif