imx8mq_evk.c 2.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2018 NXP
  4. */
  5. #include <common.h>
  6. #include <malloc.h>
  7. #include <errno.h>
  8. #include <asm/io.h>
  9. #include <miiphy.h>
  10. #include <netdev.h>
  11. #include <asm/mach-imx/iomux-v3.h>
  12. #include <asm-generic/gpio.h>
  13. #include <fsl_esdhc_imx.h>
  14. #include <mmc.h>
  15. #include <asm/arch/imx8mq_pins.h>
  16. #include <asm/arch/sys_proto.h>
  17. #include <asm/mach-imx/gpio.h>
  18. #include <asm/mach-imx/mxc_i2c.h>
  19. #include <asm/arch/clock.h>
  20. #include <spl.h>
  21. #include <power/pmic.h>
  22. #include <power/pfuze100_pmic.h>
  23. #include "../common/pfuze.h"
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  26. #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
  27. static iomux_v3_cfg_t const wdog_pads[] = {
  28. IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  29. };
  30. static iomux_v3_cfg_t const uart_pads[] = {
  31. IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  32. IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  33. };
  34. int board_early_init_f(void)
  35. {
  36. struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  37. imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  38. set_wdog_reset(wdog);
  39. imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  40. return 0;
  41. }
  42. int dram_init(void)
  43. {
  44. /* rom_pointer[1] contains the size of TEE occupies */
  45. if (rom_pointer[1])
  46. gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
  47. else
  48. gd->ram_size = PHYS_SDRAM_SIZE;
  49. return 0;
  50. }
  51. #ifdef CONFIG_FEC_MXC
  52. #define FEC_RST_PAD IMX_GPIO_NR(1, 9)
  53. static iomux_v3_cfg_t const fec1_rst_pads[] = {
  54. IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
  55. };
  56. static void setup_iomux_fec(void)
  57. {
  58. imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
  59. ARRAY_SIZE(fec1_rst_pads));
  60. gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
  61. gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
  62. udelay(500);
  63. gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
  64. }
  65. static int setup_fec(void)
  66. {
  67. struct iomuxc_gpr_base_regs *gpr =
  68. (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  69. setup_iomux_fec();
  70. /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  71. clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
  72. return set_clk_enet(ENET_125MHZ);
  73. }
  74. int board_phy_config(struct phy_device *phydev)
  75. {
  76. /* enable rgmii rxc skew and phy mode select to RGMII copper */
  77. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  78. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  79. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  80. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  81. if (phydev->drv->config)
  82. phydev->drv->config(phydev);
  83. return 0;
  84. }
  85. #endif
  86. int board_init(void)
  87. {
  88. #ifdef CONFIG_FEC_MXC
  89. setup_fec();
  90. #endif
  91. return 0;
  92. }
  93. int board_mmc_get_env_dev(int devno)
  94. {
  95. return devno;
  96. }
  97. int board_late_init(void)
  98. {
  99. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  100. env_set("board_name", "EVK");
  101. env_set("board_rev", "iMX8MQ");
  102. #endif
  103. return 0;
  104. }