mx6boards.c 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014 Eukréa Electromatique
  4. * Author: Eric Bénard <eric@eukrea.com>
  5. * Fabio Estevam <fabio.estevam@freescale.com>
  6. * Jon Nettleton <jon.nettleton@gmail.com>
  7. *
  8. * based on sabresd.c which is :
  9. * Copyright (C) 2012 Freescale Semiconductor, Inc.
  10. * and on hummingboard.c which is :
  11. * Copyright (C) 2013 SolidRun ltd.
  12. * Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>.
  13. */
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/arch/imx-regs.h>
  17. #include <asm/arch/iomux.h>
  18. #include <asm/arch/mx6-pins.h>
  19. #include <linux/errno.h>
  20. #include <asm/gpio.h>
  21. #include <asm/mach-imx/iomux-v3.h>
  22. #include <asm/mach-imx/boot_mode.h>
  23. #include <asm/mach-imx/mxc_i2c.h>
  24. #include <asm/mach-imx/spi.h>
  25. #include <asm/mach-imx/video.h>
  26. #include <i2c.h>
  27. #include <input.h>
  28. #include <mmc.h>
  29. #include <fsl_esdhc_imx.h>
  30. #include <miiphy.h>
  31. #include <netdev.h>
  32. #include <asm/arch/mxc_hdmi.h>
  33. #include <asm/arch/crm_regs.h>
  34. #include <linux/fb.h>
  35. #include <ipu_pixfmt.h>
  36. #include <asm/io.h>
  37. DECLARE_GLOBAL_DATA_PTR;
  38. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  39. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  40. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  41. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  42. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  43. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  44. #define USDHC_PAD_CLK_CTRL (PAD_CTL_SPEED_LOW | \
  45. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
  46. PAD_CTL_HYS)
  47. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  48. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  49. #define ENET_PAD_CTRL_PD (PAD_CTL_PUS_100K_DOWN | \
  50. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51. #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  52. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  53. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  54. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  55. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  56. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  57. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  58. static int board_type = -1;
  59. #define BOARD_IS_MARSBOARD 0
  60. #define BOARD_IS_RIOTBOARD 1
  61. int dram_init(void)
  62. {
  63. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  64. return 0;
  65. }
  66. static iomux_v3_cfg_t const uart2_pads[] = {
  67. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  68. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  69. };
  70. static void setup_iomux_uart(void)
  71. {
  72. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  73. }
  74. iomux_v3_cfg_t const enet_pads[] = {
  75. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77. /* GPIO16 -> AR8035 25MHz */
  78. MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(NO_PAD_CTRL),
  79. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(NO_PAD_CTRL),
  80. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85. /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
  86. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
  87. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  89. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  90. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  93. /* AR8035 PHY Reset */
  94. MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
  95. /* AR8035 PHY Interrupt */
  96. MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  97. };
  98. static void setup_iomux_enet(void)
  99. {
  100. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  101. /* Reset AR8035 PHY */
  102. gpio_direction_output(IMX_GPIO_NR(3, 31) , 0);
  103. mdelay(2);
  104. gpio_set_value(IMX_GPIO_NR(3, 31), 1);
  105. }
  106. int mx6_rgmii_rework(struct phy_device *phydev)
  107. {
  108. /* from linux/arch/arm/mach-imx/mach-imx6q.c :
  109. * Ar803x phy SmartEEE feature cause link status generates glitch,
  110. * which cause ethernet link down/up issue, so disable SmartEEE
  111. */
  112. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  113. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
  114. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
  115. return 0;
  116. }
  117. int board_phy_config(struct phy_device *phydev)
  118. {
  119. mx6_rgmii_rework(phydev);
  120. if (phydev->drv->config)
  121. phydev->drv->config(phydev);
  122. return 0;
  123. }
  124. iomux_v3_cfg_t const usdhc2_pads[] = {
  125. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
  126. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  127. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  128. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  129. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  130. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131. MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
  132. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  133. };
  134. iomux_v3_cfg_t const usdhc3_pads[] = {
  135. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
  136. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  137. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  138. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  139. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  140. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  141. };
  142. iomux_v3_cfg_t const riotboard_usdhc3_pads[] = {
  143. MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
  144. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  145. };
  146. iomux_v3_cfg_t const usdhc4_pads[] = {
  147. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CLK_CTRL),
  148. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  149. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  150. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  151. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  152. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  153. /* eMMC RST */
  154. MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
  155. };
  156. #ifdef CONFIG_FSL_ESDHC_IMX
  157. struct fsl_esdhc_cfg usdhc_cfg[3] = {
  158. {USDHC2_BASE_ADDR},
  159. {USDHC3_BASE_ADDR},
  160. {USDHC4_BASE_ADDR},
  161. };
  162. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  163. #define USDHC3_CD_GPIO IMX_GPIO_NR(7, 0)
  164. int board_mmc_getcd(struct mmc *mmc)
  165. {
  166. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  167. int ret = 0;
  168. switch (cfg->esdhc_base) {
  169. case USDHC2_BASE_ADDR:
  170. ret = !gpio_get_value(USDHC2_CD_GPIO);
  171. break;
  172. case USDHC3_BASE_ADDR:
  173. if (board_type == BOARD_IS_RIOTBOARD)
  174. ret = !gpio_get_value(USDHC3_CD_GPIO);
  175. else if (board_type == BOARD_IS_MARSBOARD)
  176. ret = 1; /* eMMC/uSDHC3 is always present */
  177. break;
  178. case USDHC4_BASE_ADDR:
  179. ret = 1; /* eMMC/uSDHC4 is always present */
  180. break;
  181. }
  182. return ret;
  183. }
  184. int board_mmc_init(bd_t *bis)
  185. {
  186. int ret;
  187. int i;
  188. /*
  189. * According to the board_mmc_init() the following map is done:
  190. * (U-Boot device node) (Physical Port)
  191. * ** RiOTboard :
  192. * mmc0 SDCard slot (bottom)
  193. * mmc1 uSDCard slot (top)
  194. * mmc2 eMMC
  195. * ** MarSBoard :
  196. * mmc0 uSDCard slot (bottom)
  197. * mmc1 eMMC
  198. */
  199. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  200. switch (i) {
  201. case 0:
  202. imx_iomux_v3_setup_multiple_pads(
  203. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  204. gpio_direction_input(USDHC2_CD_GPIO);
  205. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  206. usdhc_cfg[0].max_bus_width = 4;
  207. break;
  208. case 1:
  209. imx_iomux_v3_setup_multiple_pads(
  210. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  211. if (board_type == BOARD_IS_RIOTBOARD) {
  212. imx_iomux_v3_setup_multiple_pads(
  213. riotboard_usdhc3_pads,
  214. ARRAY_SIZE(riotboard_usdhc3_pads));
  215. gpio_direction_input(USDHC3_CD_GPIO);
  216. } else {
  217. gpio_direction_output(IMX_GPIO_NR(7, 8) , 0);
  218. udelay(250);
  219. gpio_set_value(IMX_GPIO_NR(7, 8), 1);
  220. }
  221. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  222. usdhc_cfg[1].max_bus_width = 4;
  223. break;
  224. case 2:
  225. imx_iomux_v3_setup_multiple_pads(
  226. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  227. usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  228. usdhc_cfg[2].max_bus_width = 4;
  229. gpio_direction_output(IMX_GPIO_NR(6, 8) , 0);
  230. udelay(250);
  231. gpio_set_value(IMX_GPIO_NR(6, 8), 1);
  232. break;
  233. default:
  234. printf("Warning: you configured more USDHC controllers"
  235. "(%d) then supported by the board (%d)\n",
  236. i + 1, CONFIG_SYS_FSL_USDHC_NUM);
  237. return -EINVAL;
  238. }
  239. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  240. if (ret)
  241. return ret;
  242. }
  243. return 0;
  244. }
  245. #endif
  246. #ifdef CONFIG_MXC_SPI
  247. iomux_v3_cfg_t const ecspi1_pads[] = {
  248. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  249. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  250. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  251. MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  252. };
  253. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  254. {
  255. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
  256. }
  257. static void setup_spi(void)
  258. {
  259. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  260. }
  261. #endif
  262. struct i2c_pads_info i2c_pad_info1 = {
  263. .scl = {
  264. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL
  265. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  266. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27
  267. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  268. .gp = IMX_GPIO_NR(5, 27)
  269. },
  270. .sda = {
  271. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA
  272. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  273. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26
  274. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  275. .gp = IMX_GPIO_NR(5, 26)
  276. }
  277. };
  278. struct i2c_pads_info i2c_pad_info2 = {
  279. .scl = {
  280. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
  281. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  282. .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
  283. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  284. .gp = IMX_GPIO_NR(4, 12)
  285. },
  286. .sda = {
  287. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
  288. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  289. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
  290. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  291. .gp = IMX_GPIO_NR(4, 13)
  292. }
  293. };
  294. struct i2c_pads_info i2c_pad_info3 = {
  295. .scl = {
  296. .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL
  297. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  298. .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05
  299. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  300. .gp = IMX_GPIO_NR(1, 5)
  301. },
  302. .sda = {
  303. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA
  304. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  305. .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06
  306. | MUX_PAD_CTRL(I2C_PAD_CTRL),
  307. .gp = IMX_GPIO_NR(1, 6)
  308. }
  309. };
  310. iomux_v3_cfg_t const tft_pads_riot[] = {
  311. /* LCD_PWR_EN */
  312. MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  313. /* TOUCH_INT */
  314. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  315. /* LED_PWR_EN */
  316. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  317. /* BL LEVEL */
  318. MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  319. };
  320. iomux_v3_cfg_t const tft_pads_mars[] = {
  321. /* LCD_PWR_EN */
  322. MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  323. /* TOUCH_INT */
  324. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  325. /* LED_PWR_EN */
  326. MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  327. /* BL LEVEL (PWM4) */
  328. MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  329. };
  330. #if defined(CONFIG_VIDEO_IPUV3)
  331. static void enable_lvds(struct display_info_t const *dev)
  332. {
  333. struct iomuxc *iomux = (struct iomuxc *)
  334. IOMUXC_BASE_ADDR;
  335. setbits_le32(&iomux->gpr[2],
  336. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT);
  337. /* set backlight level to ON */
  338. if (board_type == BOARD_IS_RIOTBOARD)
  339. gpio_direction_output(IMX_GPIO_NR(1, 18) , 1);
  340. else if (board_type == BOARD_IS_MARSBOARD)
  341. gpio_direction_output(IMX_GPIO_NR(2, 10) , 1);
  342. }
  343. static void disable_lvds(struct display_info_t const *dev)
  344. {
  345. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  346. /* set backlight level to OFF */
  347. if (board_type == BOARD_IS_RIOTBOARD)
  348. gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
  349. else if (board_type == BOARD_IS_MARSBOARD)
  350. gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
  351. clrbits_le32(&iomux->gpr[2],
  352. IOMUXC_GPR2_LVDS_CH0_MODE_MASK);
  353. }
  354. static void do_enable_hdmi(struct display_info_t const *dev)
  355. {
  356. disable_lvds(dev);
  357. imx_enable_hdmi_phy();
  358. }
  359. static int detect_i2c(struct display_info_t const *dev)
  360. {
  361. return (0 == i2c_set_bus_num(dev->bus)) &&
  362. (0 == i2c_probe(dev->addr));
  363. }
  364. struct display_info_t const displays[] = {{
  365. .bus = -1,
  366. .addr = 0,
  367. .pixfmt = IPU_PIX_FMT_RGB24,
  368. .detect = detect_hdmi,
  369. .enable = do_enable_hdmi,
  370. .mode = {
  371. .name = "HDMI",
  372. .refresh = 60,
  373. .xres = 1024,
  374. .yres = 768,
  375. .pixclock = 15385,
  376. .left_margin = 220,
  377. .right_margin = 40,
  378. .upper_margin = 21,
  379. .lower_margin = 7,
  380. .hsync_len = 60,
  381. .vsync_len = 10,
  382. .sync = FB_SYNC_EXT,
  383. .vmode = FB_VMODE_NONINTERLACED
  384. } }, {
  385. .bus = 2,
  386. .addr = 0x1,
  387. .pixfmt = IPU_PIX_FMT_LVDS666,
  388. .detect = detect_i2c,
  389. .enable = enable_lvds,
  390. .mode = {
  391. .name = "LCD8000-97C",
  392. .refresh = 60,
  393. .xres = 1024,
  394. .yres = 768,
  395. .pixclock = 15385,
  396. .left_margin = 100,
  397. .right_margin = 200,
  398. .upper_margin = 10,
  399. .lower_margin = 20,
  400. .hsync_len = 20,
  401. .vsync_len = 8,
  402. .sync = FB_SYNC_EXT,
  403. .vmode = FB_VMODE_NONINTERLACED
  404. } } };
  405. size_t display_count = ARRAY_SIZE(displays);
  406. static void setup_display(void)
  407. {
  408. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  409. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  410. int reg;
  411. enable_ipu_clock();
  412. imx_setup_hdmi();
  413. /* Turn on LDB0, IPU,IPU DI0 clocks */
  414. setbits_le32(&mxc_ccm->CCGR3,
  415. MXC_CCM_CCGR3_LDB_DI0_MASK);
  416. /* set LDB0 clk select to 011/011 */
  417. clrsetbits_le32(&mxc_ccm->cs2cdr,
  418. MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK,
  419. (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET));
  420. setbits_le32(&mxc_ccm->cscmr2,
  421. MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  422. setbits_le32(&mxc_ccm->chsccdr,
  423. (CHSCCDR_CLK_SEL_LDB_DI0
  424. << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  425. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  426. | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  427. | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  428. | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  429. | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  430. | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  431. | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  432. | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  433. writel(reg, &iomux->gpr[2]);
  434. clrsetbits_le32(&iomux->gpr[3],
  435. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  436. IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
  437. IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  438. << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  439. }
  440. #endif /* CONFIG_VIDEO_IPUV3 */
  441. /*
  442. * Do not overwrite the console
  443. * Use always serial for U-Boot console
  444. */
  445. int overwrite_console(void)
  446. {
  447. return 1;
  448. }
  449. int board_eth_init(bd_t *bis)
  450. {
  451. setup_iomux_enet();
  452. return cpu_eth_init(bis);
  453. }
  454. int board_early_init_f(void)
  455. {
  456. u32 cputype = cpu_type(get_cpu_rev());
  457. switch (cputype) {
  458. case MXC_CPU_MX6SOLO:
  459. board_type = BOARD_IS_RIOTBOARD;
  460. break;
  461. case MXC_CPU_MX6D:
  462. board_type = BOARD_IS_MARSBOARD;
  463. break;
  464. }
  465. setup_iomux_uart();
  466. if (board_type == BOARD_IS_RIOTBOARD)
  467. imx_iomux_v3_setup_multiple_pads(
  468. tft_pads_riot, ARRAY_SIZE(tft_pads_riot));
  469. else if (board_type == BOARD_IS_MARSBOARD)
  470. imx_iomux_v3_setup_multiple_pads(
  471. tft_pads_mars, ARRAY_SIZE(tft_pads_mars));
  472. #if defined(CONFIG_VIDEO_IPUV3)
  473. /* power ON LCD */
  474. gpio_direction_output(IMX_GPIO_NR(1, 29) , 1);
  475. /* touch interrupt is an input */
  476. gpio_direction_input(IMX_GPIO_NR(6, 14));
  477. /* power ON backlight */
  478. gpio_direction_output(IMX_GPIO_NR(6, 15) , 1);
  479. /* set backlight level to off */
  480. if (board_type == BOARD_IS_RIOTBOARD)
  481. gpio_direction_output(IMX_GPIO_NR(1, 18) , 0);
  482. else if (board_type == BOARD_IS_MARSBOARD)
  483. gpio_direction_output(IMX_GPIO_NR(2, 10) , 0);
  484. setup_display();
  485. #endif
  486. return 0;
  487. }
  488. int board_init(void)
  489. {
  490. /* address of boot parameters */
  491. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  492. /* i2c1 : PMIC, Audio codec on RiOT, Expansion connector on MarS */
  493. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  494. /* i2c2 : HDMI EDID */
  495. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  496. /* i2c3 : LVDS, Expansion connector */
  497. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
  498. #ifdef CONFIG_MXC_SPI
  499. setup_spi();
  500. #endif
  501. return 0;
  502. }
  503. #ifdef CONFIG_CMD_BMODE
  504. static const struct boot_mode riotboard_boot_modes[] = {
  505. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  506. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  507. {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  508. {NULL, 0},
  509. };
  510. static const struct boot_mode marsboard_boot_modes[] = {
  511. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  512. {"emmc", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  513. {NULL, 0},
  514. };
  515. #endif
  516. int board_late_init(void)
  517. {
  518. #ifdef CONFIG_CMD_BMODE
  519. if (board_type == BOARD_IS_RIOTBOARD)
  520. add_board_boot_modes(riotboard_boot_modes);
  521. else if (board_type == BOARD_IS_RIOTBOARD)
  522. add_board_boot_modes(marsboard_boot_modes);
  523. #endif
  524. return 0;
  525. }
  526. int checkboard(void)
  527. {
  528. puts("Board: ");
  529. if (board_type == BOARD_IS_MARSBOARD)
  530. puts("MarSBoard\n");
  531. else if (board_type == BOARD_IS_RIOTBOARD)
  532. puts("RIoTboard\n");
  533. else
  534. printf("unknown - cputype : %02x\n", cpu_type(get_cpu_rev()));
  535. return 0;
  536. }
  537. #ifdef CONFIG_SPL_BUILD
  538. #include <spl.h>
  539. void board_init_f(ulong dummy)
  540. {
  541. u32 cputype = cpu_type(get_cpu_rev());
  542. switch (cputype) {
  543. case MXC_CPU_MX6SOLO:
  544. board_type = BOARD_IS_RIOTBOARD;
  545. break;
  546. case MXC_CPU_MX6D:
  547. board_type = BOARD_IS_MARSBOARD;
  548. break;
  549. }
  550. arch_cpu_init();
  551. /* setup GP timer */
  552. timer_init();
  553. #ifdef CONFIG_SPL_SERIAL_SUPPORT
  554. setup_iomux_uart();
  555. preloader_console_init();
  556. #endif
  557. }
  558. void board_boot_order(u32 *spl_boot_list)
  559. {
  560. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  561. }
  562. /*
  563. * In order to jump to standard u-boot shell, you have to connect pin 5 of J13
  564. * to pin 3 (ground).
  565. */
  566. int spl_start_uboot(void)
  567. {
  568. int gpio_key = IMX_GPIO_NR(4, 16);
  569. gpio_direction_input(gpio_key);
  570. if (gpio_get_value(gpio_key) == 0)
  571. return 1;
  572. else
  573. return 0;
  574. }
  575. #endif