spl.c 5.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SPL board functions for CompuLab CL-SOM-iMX7 module
  4. *
  5. * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
  6. *
  7. * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
  8. */
  9. #include <common.h>
  10. #include <spl.h>
  11. #include <fsl_esdhc_imx.h>
  12. #include <asm/mach-imx/iomux-v3.h>
  13. #include <asm/arch-mx7/mx7-pins.h>
  14. #include <asm/arch-mx7/clock.h>
  15. #include <asm/arch-mx7/mx7-ddr.h>
  16. #include "common.h"
  17. #ifdef CONFIG_FSL_ESDHC_IMX
  18. static struct fsl_esdhc_cfg cl_som_imx7_spl_usdhc_cfg = {
  19. USDHC1_BASE_ADDR, 0, 4};
  20. int board_mmc_init(bd_t *bis)
  21. {
  22. cl_som_imx7_usdhc1_pads_set();
  23. cl_som_imx7_spl_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  24. return fsl_esdhc_initialize(bis, &cl_som_imx7_spl_usdhc_cfg);
  25. }
  26. #endif /* CONFIG_FSL_ESDHC_IMX */
  27. static iomux_v3_cfg_t const led_pads[] = {
  28. MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14 | MUX_PAD_CTRL(PAD_CTL_PUS_PU5KOHM |
  29. PAD_CTL_PUE | PAD_CTL_SRE_SLOW)
  30. };
  31. static struct ddrc cl_som_imx7_spl_ddrc_regs_val = {
  32. .init1 = 0x00690000,
  33. .init0 = 0x00020083,
  34. .init3 = 0x09300004,
  35. .init4 = 0x04080000,
  36. .init5 = 0x00100004,
  37. .rankctl = 0x0000033F,
  38. .dramtmg1 = 0x0007020E,
  39. .dramtmg2 = 0x03040407,
  40. .dramtmg3 = 0x00002006,
  41. .dramtmg4 = 0x04020305,
  42. .dramtmg5 = 0x03030202,
  43. .dramtmg8 = 0x00000803,
  44. .zqctl0 = 0x00810021,
  45. .dfitmg0 = 0x02098204,
  46. .dfitmg1 = 0x00030303,
  47. .dfiupd0 = 0x80400003,
  48. .dfiupd1 = 0x00100020,
  49. .dfiupd2 = 0x80100004,
  50. .addrmap4 = 0x00000F0F,
  51. .odtcfg = 0x06000604,
  52. .odtmap = 0x00000001,
  53. };
  54. static struct ddrc_mp cl_som_imx7_spl_ddrc_mp_val = {
  55. .pctrl_0 = 0x00000001,
  56. };
  57. static struct ddr_phy cl_som_imx7_spl_ddr_phy_regs_val = {
  58. .phy_con0 = 0x17420F40,
  59. .phy_con1 = 0x10210100,
  60. .phy_con4 = 0x00060807,
  61. .mdll_con0 = 0x1010007E,
  62. .drvds_con0 = 0x00000D6E,
  63. .cmd_sdll_con0 = 0x00000010,
  64. .offset_lp_con0 = 0x0000000F,
  65. };
  66. struct mx7_calibration cl_som_imx7_spl_calib_param = {
  67. .num_val = 5,
  68. .values = {
  69. 0x0E407304,
  70. 0x0E447304,
  71. 0x0E447306,
  72. 0x0E447304,
  73. 0x0E407304,
  74. },
  75. };
  76. static void cl_som_imx7_spl_dram_cfg_size(u32 ram_size)
  77. {
  78. switch (ram_size) {
  79. case SZ_256M:
  80. cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01041001;
  81. cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046;
  82. cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109;
  83. cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000014;
  84. cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00151515;
  85. cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x03030303;
  86. cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0303;
  87. cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C;
  88. cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404;
  89. break;
  90. case SZ_512M:
  91. cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001;
  92. cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046;
  93. cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109;
  94. cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000015;
  95. cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00161616;
  96. cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404;
  97. cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F0F0404;
  98. cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0C0C0C0C;
  99. cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404;
  100. break;
  101. case SZ_1G:
  102. cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001;
  103. cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x00400046;
  104. cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E1109;
  105. cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000016;
  106. cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00171717;
  107. cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404;
  108. cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x0F040404;
  109. cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A;
  110. cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x02020202;
  111. break;
  112. case SZ_2G:
  113. cl_som_imx7_spl_ddrc_regs_val.mstr = 0x01040001;
  114. cl_som_imx7_spl_ddrc_regs_val.rfshtmg = 0x0040005E;
  115. cl_som_imx7_spl_ddrc_regs_val.dramtmg0 = 0x090E110A;
  116. cl_som_imx7_spl_ddrc_regs_val.addrmap0 = 0x00000018;
  117. cl_som_imx7_spl_ddrc_regs_val.addrmap1 = 0x00181818;
  118. cl_som_imx7_spl_ddrc_regs_val.addrmap5 = 0x04040404;
  119. cl_som_imx7_spl_ddrc_regs_val.addrmap6 = 0x04040404;
  120. cl_som_imx7_spl_ddr_phy_regs_val.offset_rd_con0 = 0x0A0A0A0A;
  121. cl_som_imx7_spl_ddr_phy_regs_val.offset_wr_con0 = 0x04040404;
  122. break;
  123. }
  124. mx7_dram_cfg(&cl_som_imx7_spl_ddrc_regs_val,
  125. &cl_som_imx7_spl_ddrc_mp_val,
  126. &cl_som_imx7_spl_ddr_phy_regs_val,
  127. &cl_som_imx7_spl_calib_param);
  128. }
  129. static void cl_som_imx7_spl_dram_cfg(void)
  130. {
  131. ulong ram_size_test, ram_size = 0;
  132. for (ram_size = SZ_2G; ram_size >= SZ_256M; ram_size >>= 1) {
  133. cl_som_imx7_spl_dram_cfg_size(ram_size);
  134. ram_size_test = get_ram_size((long int *)PHYS_SDRAM, ram_size);
  135. if (ram_size_test == ram_size)
  136. break;
  137. }
  138. if (ram_size < SZ_256M) {
  139. puts("!!!ERROR!!! DRAM detection failed!!!\n");
  140. hang();
  141. }
  142. }
  143. #ifdef CONFIG_SPL_SPI_SUPPORT
  144. static void cl_som_imx7_spl_spi_init(void)
  145. {
  146. cl_som_imx7_espi1_pads_set();
  147. }
  148. #else /* !CONFIG_SPL_SPI_SUPPORT */
  149. static void cl_som_imx7_spl_spi_init(void) {}
  150. #endif /* CONFIG_SPL_SPI_SUPPORT */
  151. void board_init_f(ulong dummy)
  152. {
  153. imx_iomux_v3_setup_multiple_pads(led_pads, 1);
  154. /* setup AIPS and disable watchdog */
  155. arch_cpu_init();
  156. /* setup GP timer */
  157. timer_init();
  158. cl_som_imx7_spl_spi_init();
  159. cl_som_imx7_uart1_pads_set();
  160. /* UART clocks enabled and gd valid - init serial console */
  161. preloader_console_init();
  162. /* DRAM detection */
  163. cl_som_imx7_spl_dram_cfg();
  164. /* Clear the BSS. */
  165. memset(__bss_start, 0, __bss_end - __bss_start);
  166. /* load/boot image from boot device */
  167. board_init_r(NULL, 0);
  168. }
  169. void spl_board_init(void)
  170. {
  171. u32 boot_device = spl_boot_device();
  172. if (boot_device == BOOT_DEVICE_SPI)
  173. puts("Booting from SPI flash\n");
  174. else if (boot_device == BOOT_DEVICE_MMC1)
  175. puts("Booting from SD card\n");
  176. else
  177. puts("Unknown boot device\n");
  178. }
  179. void board_boot_order(u32 *spl_boot_list)
  180. {
  181. spl_boot_list[0] = spl_boot_device();
  182. switch (spl_boot_list[0]) {
  183. case BOOT_DEVICE_SPI:
  184. spl_boot_list[1] = BOOT_DEVICE_MMC1;
  185. break;
  186. case BOOT_DEVICE_MMC1:
  187. spl_boot_list[1] = BOOT_DEVICE_SPI;
  188. break;
  189. }
  190. }