mux.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SPL/U-Boot mux functions for CompuLab CL-SOM-iMX7 module
  4. *
  5. * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
  6. *
  7. * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
  8. */
  9. #include <common.h>
  10. #include <asm/mach-imx/iomux-v3.h>
  11. #include <asm/arch-mx7/mx7-pins.h>
  12. #define PADS_SET(pads_array) \
  13. void cl_som_imx7_##pads_array##_set(void) \
  14. { \
  15. imx_iomux_v3_setup_multiple_pads(pads_array, ARRAY_SIZE(pads_array)); \
  16. }
  17. #ifdef CONFIG_FSL_ESDHC_IMX
  18. #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  19. PAD_CTL_HYS | PAD_CTL_PUE | \
  20. PAD_CTL_PUS_PU47KOHM)
  21. static iomux_v3_cfg_t const usdhc1_pads[] = {
  22. MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  23. MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  24. MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  25. MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  26. MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  27. MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  28. MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  29. };
  30. PADS_SET(usdhc1_pads)
  31. #endif /* CONFIG_FSL_ESDHC_IMX */
  32. #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
  33. PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  34. static iomux_v3_cfg_t const uart1_pads[] = {
  35. MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  36. MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  37. };
  38. PADS_SET(uart1_pads)
  39. #ifdef CONFIG_SPI
  40. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SRE_SLOW | \
  41. PAD_CTL_DSE_3P3V_32OHM)
  42. #define GPIO_PAD_CTRL (PAD_CTL_PUS_PU5KOHM | PAD_CTL_PUE | \
  43. PAD_CTL_SRE_SLOW)
  44. static iomux_v3_cfg_t const espi1_pads[] = {
  45. MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  46. MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  47. MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  48. MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  49. };
  50. PADS_SET(espi1_pads)
  51. #endif /* CONFIG_SPI */
  52. #ifndef CONFIG_SPL_BUILD
  53. #ifdef CONFIG_FSL_ESDHC_IMX
  54. static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
  55. MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  56. MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  57. MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  58. MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  59. MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  60. MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  61. MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  62. MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  63. MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  64. MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  65. MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  66. MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  67. };
  68. PADS_SET(usdhc3_emmc_pads)
  69. #endif /* CONFIG_FSL_ESDHC_IMX */
  70. #ifdef CONFIG_FEC_MXC
  71. #define ENET_PAD_CTRL (PAD_CTL_PUS_PD100KOHM | PAD_CTL_DSE_3P3V_49OHM)
  72. #define ENET_PAD_CTRL_MII (PAD_CTL_PUS_PU5KOHM)
  73. static iomux_v3_cfg_t const phy1_rst_pads[] = {
  74. /* PHY1 RST */
  75. MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  76. };
  77. PADS_SET(phy1_rst_pads)
  78. static iomux_v3_cfg_t const fec1_pads[] = {
  79. MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL |
  80. MUX_PAD_CTRL(ENET_PAD_CTRL),
  81. MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82. MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  83. MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  84. MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85. MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86. MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL |
  87. MUX_PAD_CTRL(ENET_PAD_CTRL),
  88. MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89. MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90. MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91. MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92. MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93. MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
  94. MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
  95. };
  96. PADS_SET(fec1_pads)
  97. #endif /* CONFIG_FEC_MXC */
  98. static iomux_v3_cfg_t const usb_otg1_pads[] = {
  99. MX7D_PAD_GPIO1_IO05__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  100. };
  101. PADS_SET(usb_otg1_pads)
  102. static iomux_v3_cfg_t const wdog_pads[] = {
  103. MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  104. };
  105. PADS_SET(wdog_pads)
  106. #endif /* !CONFIG_SPL_BUILD */