nitrogen6x.c 27 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
  4. * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
  5. */
  6. #include <common.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/imx-regs.h>
  10. #include <asm/arch/iomux.h>
  11. #include <asm/arch/sys_proto.h>
  12. #include <malloc.h>
  13. #include <asm/arch/mx6-pins.h>
  14. #include <linux/errno.h>
  15. #include <asm/gpio.h>
  16. #include <asm/mach-imx/iomux-v3.h>
  17. #include <asm/mach-imx/mxc_i2c.h>
  18. #include <asm/mach-imx/sata.h>
  19. #include <asm/mach-imx/spi.h>
  20. #include <asm/mach-imx/boot_mode.h>
  21. #include <asm/mach-imx/video.h>
  22. #include <mmc.h>
  23. #include <fsl_esdhc_imx.h>
  24. #include <micrel.h>
  25. #include <miiphy.h>
  26. #include <netdev.h>
  27. #include <asm/arch/crm_regs.h>
  28. #include <asm/arch/mxc_hdmi.h>
  29. #include <i2c.h>
  30. #include <input.h>
  31. #include <netdev.h>
  32. #include <usb/ehci-ci.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #define GP_USB_OTG_PWR IMX_GPIO_NR(3, 22)
  35. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  36. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  37. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  38. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  39. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  40. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  41. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  42. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  43. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  44. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  45. #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  46. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  47. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  48. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  49. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  50. #define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \
  51. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  52. PAD_CTL_SRE_SLOW)
  53. #define WEAK_PULLDOWN (PAD_CTL_PUS_100K_DOWN | \
  54. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  55. PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
  56. #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  57. int dram_init(void)
  58. {
  59. gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
  60. return 0;
  61. }
  62. static iomux_v3_cfg_t const uart1_pads[] = {
  63. MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  64. MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  65. };
  66. static iomux_v3_cfg_t const uart2_pads[] = {
  67. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  68. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  69. };
  70. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  71. /* I2C1, SGTL5000 */
  72. static struct i2c_pads_info i2c_pad_info0 = {
  73. .scl = {
  74. .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
  75. .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
  76. .gp = IMX_GPIO_NR(3, 21)
  77. },
  78. .sda = {
  79. .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
  80. .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
  81. .gp = IMX_GPIO_NR(3, 28)
  82. }
  83. };
  84. /* I2C2 Camera, MIPI */
  85. static struct i2c_pads_info i2c_pad_info1 = {
  86. .scl = {
  87. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
  88. .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
  89. .gp = IMX_GPIO_NR(4, 12)
  90. },
  91. .sda = {
  92. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
  93. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
  94. .gp = IMX_GPIO_NR(4, 13)
  95. }
  96. };
  97. /* I2C3, J15 - RGB connector */
  98. static struct i2c_pads_info i2c_pad_info2 = {
  99. .scl = {
  100. .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC,
  101. .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC,
  102. .gp = IMX_GPIO_NR(1, 5)
  103. },
  104. .sda = {
  105. .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
  106. .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
  107. .gp = IMX_GPIO_NR(7, 11)
  108. }
  109. };
  110. static iomux_v3_cfg_t const usdhc2_pads[] = {
  111. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  113. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  114. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  115. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  116. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. };
  118. static iomux_v3_cfg_t const usdhc3_pads[] = {
  119. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  120. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  121. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  122. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  126. };
  127. static iomux_v3_cfg_t const usdhc4_pads[] = {
  128. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  129. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  130. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  131. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  132. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  133. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  134. MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  135. };
  136. static iomux_v3_cfg_t const enet_pads1[] = {
  137. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  138. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  139. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  140. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  141. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  142. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  143. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  144. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  145. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  146. /* pin 35 - 1 (PHY_AD2) on reset */
  147. MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  148. /* pin 32 - 1 - (MODE0) all */
  149. MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  150. /* pin 31 - 1 - (MODE1) all */
  151. MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  152. /* pin 28 - 1 - (MODE2) all */
  153. MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  154. /* pin 27 - 1 - (MODE3) all */
  155. MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  156. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  157. MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
  158. /* pin 42 PHY nRST */
  159. MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  160. MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  161. };
  162. static iomux_v3_cfg_t const enet_pads2[] = {
  163. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  164. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  165. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  166. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  167. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  168. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  169. };
  170. static iomux_v3_cfg_t const misc_pads[] = {
  171. MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),
  172. MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(WEAK_PULLUP),
  173. MX6_PAD_EIM_D30__USB_H1_OC | MUX_PAD_CTRL(WEAK_PULLUP),
  174. /* OTG Power enable */
  175. MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(OUTPUT_40OHM),
  176. };
  177. /* wl1271 pads on nitrogen6x */
  178. static iomux_v3_cfg_t const wl12xx_pads[] = {
  179. (MX6_PAD_NANDF_CS1__GPIO6_IO14 & ~MUX_PAD_CTRL_MASK)
  180. | MUX_PAD_CTRL(WEAK_PULLDOWN),
  181. (MX6_PAD_NANDF_CS2__GPIO6_IO15 & ~MUX_PAD_CTRL_MASK)
  182. | MUX_PAD_CTRL(OUTPUT_40OHM),
  183. (MX6_PAD_NANDF_CS3__GPIO6_IO16 & ~MUX_PAD_CTRL_MASK)
  184. | MUX_PAD_CTRL(OUTPUT_40OHM),
  185. };
  186. #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
  187. #define WL12XX_WL_ENABLE_GP IMX_GPIO_NR(6, 15)
  188. #define WL12XX_BT_ENABLE_GP IMX_GPIO_NR(6, 16)
  189. /* Button assignments for J14 */
  190. static iomux_v3_cfg_t const button_pads[] = {
  191. /* Menu */
  192. MX6_PAD_NANDF_D1__GPIO2_IO01 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  193. /* Back */
  194. MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  195. /* Labelled Search (mapped to Power under Android) */
  196. MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  197. /* Home */
  198. MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  199. /* Volume Down */
  200. MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  201. /* Volume Up */
  202. MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
  203. };
  204. static void setup_iomux_enet(void)
  205. {
  206. gpio_direction_output(IMX_GPIO_NR(3, 23), 0); /* SABRE Lite PHY rst */
  207. gpio_direction_output(IMX_GPIO_NR(1, 27), 0); /* Nitrogen6X PHY rst */
  208. gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
  209. gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
  210. gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
  211. gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
  212. gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
  213. imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  214. gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  215. /* Need delay 10ms according to KSZ9021 spec */
  216. udelay(1000 * 10);
  217. gpio_set_value(IMX_GPIO_NR(3, 23), 1); /* SABRE Lite PHY reset */
  218. gpio_set_value(IMX_GPIO_NR(1, 27), 1); /* Nitrogen6X PHY reset */
  219. imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  220. udelay(100); /* Wait 100 us before using mii interface */
  221. }
  222. static iomux_v3_cfg_t const usb_pads[] = {
  223. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  224. };
  225. static void setup_iomux_uart(void)
  226. {
  227. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  228. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  229. }
  230. #ifdef CONFIG_USB_EHCI_MX6
  231. int board_ehci_hcd_init(int port)
  232. {
  233. imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
  234. /* Reset USB hub */
  235. gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
  236. mdelay(2);
  237. gpio_set_value(IMX_GPIO_NR(7, 12), 1);
  238. return 0;
  239. }
  240. int board_ehci_power(int port, int on)
  241. {
  242. if (port)
  243. return 0;
  244. gpio_set_value(GP_USB_OTG_PWR, on);
  245. return 0;
  246. }
  247. #endif
  248. #ifdef CONFIG_FSL_ESDHC_IMX
  249. static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  250. {USDHC3_BASE_ADDR},
  251. {USDHC4_BASE_ADDR},
  252. };
  253. int board_mmc_getcd(struct mmc *mmc)
  254. {
  255. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  256. int gp_cd = (cfg->esdhc_base == USDHC3_BASE_ADDR) ? IMX_GPIO_NR(7, 0) :
  257. IMX_GPIO_NR(2, 6);
  258. gpio_direction_input(gp_cd);
  259. return !gpio_get_value(gp_cd);
  260. }
  261. int board_mmc_init(bd_t *bis)
  262. {
  263. int ret;
  264. u32 index = 0;
  265. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  266. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  267. usdhc_cfg[0].max_bus_width = 4;
  268. usdhc_cfg[1].max_bus_width = 4;
  269. for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  270. switch (index) {
  271. case 0:
  272. imx_iomux_v3_setup_multiple_pads(
  273. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  274. break;
  275. case 1:
  276. imx_iomux_v3_setup_multiple_pads(
  277. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  278. break;
  279. default:
  280. printf("Warning: you configured more USDHC controllers"
  281. "(%d) then supported by the board (%d)\n",
  282. index + 1, CONFIG_SYS_FSL_USDHC_NUM);
  283. return -EINVAL;
  284. }
  285. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  286. if (ret)
  287. return ret;
  288. }
  289. return 0;
  290. }
  291. #endif
  292. #ifdef CONFIG_MXC_SPI
  293. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  294. {
  295. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
  296. }
  297. static iomux_v3_cfg_t const ecspi1_pads[] = {
  298. /* SS1 */
  299. MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
  300. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  301. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  302. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  303. };
  304. static void setup_spi(void)
  305. {
  306. imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
  307. ARRAY_SIZE(ecspi1_pads));
  308. }
  309. #endif
  310. int board_phy_config(struct phy_device *phydev)
  311. {
  312. /* min rx data delay */
  313. ksz9021_phy_extended_write(phydev,
  314. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
  315. /* min tx data delay */
  316. ksz9021_phy_extended_write(phydev,
  317. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
  318. /* max rx/tx clock delay, min rx/tx control */
  319. ksz9021_phy_extended_write(phydev,
  320. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
  321. if (phydev->drv->config)
  322. phydev->drv->config(phydev);
  323. return 0;
  324. }
  325. int board_eth_init(bd_t *bis)
  326. {
  327. uint32_t base = IMX_FEC_BASE;
  328. struct mii_dev *bus = NULL;
  329. struct phy_device *phydev = NULL;
  330. int ret;
  331. setup_iomux_enet();
  332. #ifdef CONFIG_FEC_MXC
  333. bus = fec_get_miibus(base, -1);
  334. if (!bus)
  335. return -EINVAL;
  336. /* scan phy 4,5,6,7 */
  337. phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII);
  338. if (!phydev) {
  339. ret = -EINVAL;
  340. goto free_bus;
  341. }
  342. printf("using phy at %d\n", phydev->addr);
  343. ret = fec_probe(bis, -1, base, bus, phydev);
  344. if (ret)
  345. goto free_phydev;
  346. #endif
  347. #ifdef CONFIG_CI_UDC
  348. /* For otg ethernet*/
  349. usb_eth_initialize(bis);
  350. #endif
  351. return 0;
  352. free_phydev:
  353. free(phydev);
  354. free_bus:
  355. free(bus);
  356. return ret;
  357. }
  358. static void setup_buttons(void)
  359. {
  360. imx_iomux_v3_setup_multiple_pads(button_pads,
  361. ARRAY_SIZE(button_pads));
  362. }
  363. #if defined(CONFIG_VIDEO_IPUV3)
  364. static iomux_v3_cfg_t const backlight_pads[] = {
  365. /* Backlight on RGB connector: J15 */
  366. MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
  367. #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
  368. /* Backlight on LVDS connector: J6 */
  369. MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
  370. #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
  371. };
  372. static iomux_v3_cfg_t const rgb_pads[] = {
  373. MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
  374. MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15,
  375. MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,
  376. MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,
  377. MX6_PAD_DI0_PIN4__GPIO4_IO20,
  378. MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
  379. MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
  380. MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
  381. MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
  382. MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
  383. MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
  384. MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
  385. MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
  386. MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
  387. MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
  388. MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
  389. MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
  390. MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
  391. MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
  392. MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
  393. MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
  394. MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
  395. MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
  396. MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18,
  397. MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19,
  398. MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20,
  399. MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21,
  400. MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22,
  401. MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23,
  402. };
  403. static void do_enable_hdmi(struct display_info_t const *dev)
  404. {
  405. imx_enable_hdmi_phy();
  406. }
  407. static int detect_i2c(struct display_info_t const *dev)
  408. {
  409. return ((0 == i2c_set_bus_num(dev->bus))
  410. &&
  411. (0 == i2c_probe(dev->addr)));
  412. }
  413. static void enable_lvds(struct display_info_t const *dev)
  414. {
  415. struct iomuxc *iomux = (struct iomuxc *)
  416. IOMUXC_BASE_ADDR;
  417. u32 reg = readl(&iomux->gpr[2]);
  418. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
  419. writel(reg, &iomux->gpr[2]);
  420. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  421. }
  422. static void enable_lvds_jeida(struct display_info_t const *dev)
  423. {
  424. struct iomuxc *iomux = (struct iomuxc *)
  425. IOMUXC_BASE_ADDR;
  426. u32 reg = readl(&iomux->gpr[2]);
  427. reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
  428. |IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA;
  429. writel(reg, &iomux->gpr[2]);
  430. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  431. }
  432. static void enable_rgb(struct display_info_t const *dev)
  433. {
  434. imx_iomux_v3_setup_multiple_pads(
  435. rgb_pads,
  436. ARRAY_SIZE(rgb_pads));
  437. gpio_direction_output(RGB_BACKLIGHT_GP, 1);
  438. }
  439. struct display_info_t const displays[] = {{
  440. .bus = 1,
  441. .addr = 0x50,
  442. .pixfmt = IPU_PIX_FMT_RGB24,
  443. .detect = detect_i2c,
  444. .enable = do_enable_hdmi,
  445. .mode = {
  446. .name = "HDMI",
  447. .refresh = 60,
  448. .xres = 1024,
  449. .yres = 768,
  450. .pixclock = 15385,
  451. .left_margin = 220,
  452. .right_margin = 40,
  453. .upper_margin = 21,
  454. .lower_margin = 7,
  455. .hsync_len = 60,
  456. .vsync_len = 10,
  457. .sync = FB_SYNC_EXT,
  458. .vmode = FB_VMODE_NONINTERLACED
  459. } }, {
  460. .bus = 0,
  461. .addr = 0,
  462. .pixfmt = IPU_PIX_FMT_RGB24,
  463. .detect = NULL,
  464. .enable = enable_lvds_jeida,
  465. .mode = {
  466. .name = "LDB-WXGA",
  467. .refresh = 60,
  468. .xres = 1280,
  469. .yres = 800,
  470. .pixclock = 14065,
  471. .left_margin = 40,
  472. .right_margin = 40,
  473. .upper_margin = 3,
  474. .lower_margin = 80,
  475. .hsync_len = 10,
  476. .vsync_len = 10,
  477. .sync = FB_SYNC_EXT,
  478. .vmode = FB_VMODE_NONINTERLACED
  479. } }, {
  480. .bus = 0,
  481. .addr = 0,
  482. .pixfmt = IPU_PIX_FMT_RGB24,
  483. .detect = NULL,
  484. .enable = enable_lvds,
  485. .mode = {
  486. .name = "LDB-WXGA-S",
  487. .refresh = 60,
  488. .xres = 1280,
  489. .yres = 800,
  490. .pixclock = 14065,
  491. .left_margin = 40,
  492. .right_margin = 40,
  493. .upper_margin = 3,
  494. .lower_margin = 80,
  495. .hsync_len = 10,
  496. .vsync_len = 10,
  497. .sync = FB_SYNC_EXT,
  498. .vmode = FB_VMODE_NONINTERLACED
  499. } }, {
  500. .bus = 2,
  501. .addr = 0x4,
  502. .pixfmt = IPU_PIX_FMT_LVDS666,
  503. .detect = detect_i2c,
  504. .enable = enable_lvds,
  505. .mode = {
  506. .name = "Hannstar-XGA",
  507. .refresh = 60,
  508. .xres = 1024,
  509. .yres = 768,
  510. .pixclock = 15385,
  511. .left_margin = 220,
  512. .right_margin = 40,
  513. .upper_margin = 21,
  514. .lower_margin = 7,
  515. .hsync_len = 60,
  516. .vsync_len = 10,
  517. .sync = FB_SYNC_EXT,
  518. .vmode = FB_VMODE_NONINTERLACED
  519. } }, {
  520. .bus = 0,
  521. .addr = 0,
  522. .pixfmt = IPU_PIX_FMT_LVDS666,
  523. .detect = NULL,
  524. .enable = enable_lvds,
  525. .mode = {
  526. .name = "LG-9.7",
  527. .refresh = 60,
  528. .xres = 1024,
  529. .yres = 768,
  530. .pixclock = 15385, /* ~65MHz */
  531. .left_margin = 480,
  532. .right_margin = 260,
  533. .upper_margin = 16,
  534. .lower_margin = 6,
  535. .hsync_len = 250,
  536. .vsync_len = 10,
  537. .sync = FB_SYNC_EXT,
  538. .vmode = FB_VMODE_NONINTERLACED
  539. } }, {
  540. .bus = 2,
  541. .addr = 0x38,
  542. .pixfmt = IPU_PIX_FMT_LVDS666,
  543. .detect = detect_i2c,
  544. .enable = enable_lvds,
  545. .mode = {
  546. .name = "wsvga-lvds",
  547. .refresh = 60,
  548. .xres = 1024,
  549. .yres = 600,
  550. .pixclock = 15385,
  551. .left_margin = 220,
  552. .right_margin = 40,
  553. .upper_margin = 21,
  554. .lower_margin = 7,
  555. .hsync_len = 60,
  556. .vsync_len = 10,
  557. .sync = FB_SYNC_EXT,
  558. .vmode = FB_VMODE_NONINTERLACED
  559. } }, {
  560. .bus = 2,
  561. .addr = 0x10,
  562. .pixfmt = IPU_PIX_FMT_RGB666,
  563. .detect = detect_i2c,
  564. .enable = enable_rgb,
  565. .mode = {
  566. .name = "fusion7",
  567. .refresh = 60,
  568. .xres = 800,
  569. .yres = 480,
  570. .pixclock = 33898,
  571. .left_margin = 96,
  572. .right_margin = 24,
  573. .upper_margin = 3,
  574. .lower_margin = 10,
  575. .hsync_len = 72,
  576. .vsync_len = 7,
  577. .sync = 0x40000002,
  578. .vmode = FB_VMODE_NONINTERLACED
  579. } }, {
  580. .bus = 0,
  581. .addr = 0,
  582. .pixfmt = IPU_PIX_FMT_RGB666,
  583. .detect = NULL,
  584. .enable = enable_rgb,
  585. .mode = {
  586. .name = "svga",
  587. .refresh = 60,
  588. .xres = 800,
  589. .yres = 600,
  590. .pixclock = 15385,
  591. .left_margin = 220,
  592. .right_margin = 40,
  593. .upper_margin = 21,
  594. .lower_margin = 7,
  595. .hsync_len = 60,
  596. .vsync_len = 10,
  597. .sync = 0,
  598. .vmode = FB_VMODE_NONINTERLACED
  599. } }, {
  600. .bus = 2,
  601. .addr = 0x41,
  602. .pixfmt = IPU_PIX_FMT_LVDS666,
  603. .detect = detect_i2c,
  604. .enable = enable_lvds,
  605. .mode = {
  606. .name = "amp1024x600",
  607. .refresh = 60,
  608. .xres = 1024,
  609. .yres = 600,
  610. .pixclock = 15385,
  611. .left_margin = 220,
  612. .right_margin = 40,
  613. .upper_margin = 21,
  614. .lower_margin = 7,
  615. .hsync_len = 60,
  616. .vsync_len = 10,
  617. .sync = FB_SYNC_EXT,
  618. .vmode = FB_VMODE_NONINTERLACED
  619. } }, {
  620. .bus = 0,
  621. .addr = 0,
  622. .pixfmt = IPU_PIX_FMT_LVDS666,
  623. .detect = 0,
  624. .enable = enable_lvds,
  625. .mode = {
  626. .name = "wvga-lvds",
  627. .refresh = 57,
  628. .xres = 800,
  629. .yres = 480,
  630. .pixclock = 15385,
  631. .left_margin = 220,
  632. .right_margin = 40,
  633. .upper_margin = 21,
  634. .lower_margin = 7,
  635. .hsync_len = 60,
  636. .vsync_len = 10,
  637. .sync = FB_SYNC_EXT,
  638. .vmode = FB_VMODE_NONINTERLACED
  639. } }, {
  640. .bus = 2,
  641. .addr = 0x48,
  642. .pixfmt = IPU_PIX_FMT_RGB666,
  643. .detect = detect_i2c,
  644. .enable = enable_rgb,
  645. .mode = {
  646. .name = "wvga-rgb",
  647. .refresh = 57,
  648. .xres = 800,
  649. .yres = 480,
  650. .pixclock = 37037,
  651. .left_margin = 40,
  652. .right_margin = 60,
  653. .upper_margin = 10,
  654. .lower_margin = 10,
  655. .hsync_len = 20,
  656. .vsync_len = 10,
  657. .sync = 0,
  658. .vmode = FB_VMODE_NONINTERLACED
  659. } }, {
  660. .bus = 0,
  661. .addr = 0,
  662. .pixfmt = IPU_PIX_FMT_RGB24,
  663. .detect = NULL,
  664. .enable = enable_rgb,
  665. .mode = {
  666. .name = "qvga",
  667. .refresh = 60,
  668. .xres = 320,
  669. .yres = 240,
  670. .pixclock = 37037,
  671. .left_margin = 38,
  672. .right_margin = 37,
  673. .upper_margin = 16,
  674. .lower_margin = 15,
  675. .hsync_len = 30,
  676. .vsync_len = 3,
  677. .sync = 0,
  678. .vmode = FB_VMODE_NONINTERLACED
  679. } } };
  680. size_t display_count = ARRAY_SIZE(displays);
  681. int board_cfb_skip(void)
  682. {
  683. return NULL != env_get("novideo");
  684. }
  685. static void setup_display(void)
  686. {
  687. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  688. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  689. int reg;
  690. enable_ipu_clock();
  691. imx_setup_hdmi();
  692. /* Turn on LDB0,IPU,IPU DI0 clocks */
  693. reg = __raw_readl(&mxc_ccm->CCGR3);
  694. reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
  695. writel(reg, &mxc_ccm->CCGR3);
  696. /* set LDB0, LDB1 clk select to 011/011 */
  697. reg = readl(&mxc_ccm->cs2cdr);
  698. reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
  699. |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
  700. reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
  701. |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
  702. writel(reg, &mxc_ccm->cs2cdr);
  703. reg = readl(&mxc_ccm->cscmr2);
  704. reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
  705. writel(reg, &mxc_ccm->cscmr2);
  706. reg = readl(&mxc_ccm->chsccdr);
  707. reg |= (CHSCCDR_CLK_SEL_LDB_DI0
  708. <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  709. writel(reg, &mxc_ccm->chsccdr);
  710. reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
  711. |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
  712. |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
  713. |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
  714. |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
  715. |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
  716. |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
  717. |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
  718. |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
  719. writel(reg, &iomux->gpr[2]);
  720. reg = readl(&iomux->gpr[3]);
  721. reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
  722. |IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
  723. | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
  724. <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
  725. writel(reg, &iomux->gpr[3]);
  726. /* backlights off until needed */
  727. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  728. ARRAY_SIZE(backlight_pads));
  729. gpio_direction_input(LVDS_BACKLIGHT_GP);
  730. gpio_direction_input(RGB_BACKLIGHT_GP);
  731. }
  732. #endif
  733. static iomux_v3_cfg_t const init_pads[] = {
  734. /* SGTL5000 sys_mclk */
  735. NEW_PAD_CTRL(MX6_PAD_GPIO_0__CCM_CLKO1, OUTPUT_40OHM),
  736. /* J5 - Camera MCLK */
  737. NEW_PAD_CTRL(MX6_PAD_GPIO_3__CCM_CLKO2, OUTPUT_40OHM),
  738. /* wl1271 pads on nitrogen6x */
  739. /* WL12XX_WL_IRQ_GP */
  740. NEW_PAD_CTRL(MX6_PAD_NANDF_CS1__GPIO6_IO14, WEAK_PULLDOWN),
  741. /* WL12XX_WL_ENABLE_GP */
  742. NEW_PAD_CTRL(MX6_PAD_NANDF_CS2__GPIO6_IO15, OUTPUT_40OHM),
  743. /* WL12XX_BT_ENABLE_GP */
  744. NEW_PAD_CTRL(MX6_PAD_NANDF_CS3__GPIO6_IO16, OUTPUT_40OHM),
  745. /* USB otg power */
  746. NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, OUTPUT_40OHM),
  747. NEW_PAD_CTRL(MX6_PAD_NANDF_D5__GPIO2_IO05, OUTPUT_40OHM),
  748. NEW_PAD_CTRL(MX6_PAD_NANDF_WP_B__GPIO6_IO09, OUTPUT_40OHM),
  749. NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, OUTPUT_40OHM),
  750. NEW_PAD_CTRL(MX6_PAD_GPIO_6__GPIO1_IO06, OUTPUT_40OHM),
  751. };
  752. #define WL12XX_WL_IRQ_GP IMX_GPIO_NR(6, 14)
  753. static unsigned gpios_out_low[] = {
  754. /* Disable wl1271 */
  755. IMX_GPIO_NR(6, 15), /* disable wireless */
  756. IMX_GPIO_NR(6, 16), /* disable bluetooth */
  757. IMX_GPIO_NR(3, 22), /* disable USB otg power */
  758. IMX_GPIO_NR(2, 5), /* ov5640 mipi camera reset */
  759. IMX_GPIO_NR(1, 8), /* ov5642 reset */
  760. };
  761. static unsigned gpios_out_high[] = {
  762. IMX_GPIO_NR(1, 6), /* ov5642 powerdown */
  763. IMX_GPIO_NR(6, 9), /* ov5640 mipi camera power down */
  764. };
  765. static void set_gpios(unsigned *p, int cnt, int val)
  766. {
  767. int i;
  768. for (i = 0; i < cnt; i++)
  769. gpio_direction_output(*p++, val);
  770. }
  771. int board_early_init_f(void)
  772. {
  773. setup_iomux_uart();
  774. set_gpios(gpios_out_high, ARRAY_SIZE(gpios_out_high), 1);
  775. set_gpios(gpios_out_low, ARRAY_SIZE(gpios_out_low), 0);
  776. gpio_direction_input(WL12XX_WL_IRQ_GP);
  777. imx_iomux_v3_setup_multiple_pads(wl12xx_pads, ARRAY_SIZE(wl12xx_pads));
  778. imx_iomux_v3_setup_multiple_pads(init_pads, ARRAY_SIZE(init_pads));
  779. setup_buttons();
  780. #if defined(CONFIG_VIDEO_IPUV3)
  781. setup_display();
  782. #endif
  783. return 0;
  784. }
  785. /*
  786. * Do not overwrite the console
  787. * Use always serial for U-Boot console
  788. */
  789. int overwrite_console(void)
  790. {
  791. return 1;
  792. }
  793. int board_init(void)
  794. {
  795. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  796. clrsetbits_le32(&iomuxc_regs->gpr[1],
  797. IOMUXC_GPR1_OTG_ID_MASK,
  798. IOMUXC_GPR1_OTG_ID_GPIO1);
  799. imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads));
  800. /* address of boot parameters */
  801. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  802. #ifdef CONFIG_MXC_SPI
  803. setup_spi();
  804. #endif
  805. imx_iomux_v3_setup_multiple_pads(
  806. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  807. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  808. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  809. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  810. #ifdef CONFIG_SATA
  811. setup_sata();
  812. #endif
  813. return 0;
  814. }
  815. int checkboard(void)
  816. {
  817. if (gpio_get_value(WL12XX_WL_IRQ_GP))
  818. puts("Board: Nitrogen6X\n");
  819. else
  820. puts("Board: SABRE Lite\n");
  821. return 0;
  822. }
  823. struct button_key {
  824. char const *name;
  825. unsigned gpnum;
  826. char ident;
  827. };
  828. static struct button_key const buttons[] = {
  829. {"back", IMX_GPIO_NR(2, 2), 'B'},
  830. {"home", IMX_GPIO_NR(2, 4), 'H'},
  831. {"menu", IMX_GPIO_NR(2, 1), 'M'},
  832. {"search", IMX_GPIO_NR(2, 3), 'S'},
  833. {"volup", IMX_GPIO_NR(7, 13), 'V'},
  834. {"voldown", IMX_GPIO_NR(4, 5), 'v'},
  835. };
  836. /*
  837. * generate a null-terminated string containing the buttons pressed
  838. * returns number of keys pressed
  839. */
  840. static int read_keys(char *buf)
  841. {
  842. int i, numpressed = 0;
  843. for (i = 0; i < ARRAY_SIZE(buttons); i++) {
  844. if (!gpio_get_value(buttons[i].gpnum))
  845. buf[numpressed++] = buttons[i].ident;
  846. }
  847. buf[numpressed] = '\0';
  848. return numpressed;
  849. }
  850. static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  851. {
  852. char envvalue[ARRAY_SIZE(buttons)+1];
  853. int numpressed = read_keys(envvalue);
  854. env_set("keybd", envvalue);
  855. return numpressed == 0;
  856. }
  857. U_BOOT_CMD(
  858. kbd, 1, 1, do_kbd,
  859. "Tests for keypresses, sets 'keybd' environment variable",
  860. "Returns 0 (true) to shell if key is pressed."
  861. );
  862. #ifdef CONFIG_PREBOOT
  863. static char const kbd_magic_prefix[] = "key_magic";
  864. static char const kbd_command_prefix[] = "key_cmd";
  865. static void preboot_keys(void)
  866. {
  867. int numpressed;
  868. char keypress[ARRAY_SIZE(buttons)+1];
  869. numpressed = read_keys(keypress);
  870. if (numpressed) {
  871. char *kbd_magic_keys = env_get("magic_keys");
  872. char *suffix;
  873. /*
  874. * loop over all magic keys
  875. */
  876. for (suffix = kbd_magic_keys; *suffix; ++suffix) {
  877. char *keys;
  878. char magic[sizeof(kbd_magic_prefix) + 1];
  879. sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
  880. keys = env_get(magic);
  881. if (keys) {
  882. if (!strcmp(keys, keypress))
  883. break;
  884. }
  885. }
  886. if (*suffix) {
  887. char cmd_name[sizeof(kbd_command_prefix) + 1];
  888. char *cmd;
  889. sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
  890. cmd = env_get(cmd_name);
  891. if (cmd) {
  892. env_set("preboot", cmd);
  893. return;
  894. }
  895. }
  896. }
  897. }
  898. #endif
  899. #ifdef CONFIG_CMD_BMODE
  900. static const struct boot_mode board_boot_modes[] = {
  901. /* 4 bit bus width */
  902. {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  903. {"mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
  904. {NULL, 0},
  905. };
  906. #endif
  907. int misc_init_r(void)
  908. {
  909. #ifdef CONFIG_PREBOOT
  910. preboot_keys();
  911. #endif
  912. #ifdef CONFIG_CMD_BMODE
  913. add_board_boot_modes(board_boot_modes);
  914. #endif
  915. env_set_hex("reset_cause", get_imx_reset_cause());
  916. return 0;
  917. }