titanium.c 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2013 Stefan Roese <sr@denx.de>
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/iomux.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <asm/arch/crm_regs.h>
  12. #include <asm/arch/sys_proto.h>
  13. #include <asm/gpio.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/mach-imx/mxc_i2c.h>
  16. #include <asm/mach-imx/boot_mode.h>
  17. #include <mmc.h>
  18. #include <fsl_esdhc_imx.h>
  19. #include <micrel.h>
  20. #include <miiphy.h>
  21. #include <netdev.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  24. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  25. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
  26. PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  27. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  28. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  29. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  30. PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  31. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  32. int dram_init(void)
  33. {
  34. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  35. return 0;
  36. }
  37. iomux_v3_cfg_t const uart1_pads[] = {
  38. MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  39. MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  40. };
  41. iomux_v3_cfg_t const uart2_pads[] = {
  42. MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  43. MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  44. };
  45. iomux_v3_cfg_t const uart4_pads[] = {
  46. MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  47. MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  48. };
  49. #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  50. struct i2c_pads_info i2c_pad_info0 = {
  51. .scl = {
  52. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC,
  53. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
  54. .gp = IMX_GPIO_NR(5, 27)
  55. },
  56. .sda = {
  57. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC,
  58. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
  59. .gp = IMX_GPIO_NR(5, 26)
  60. }
  61. };
  62. struct i2c_pads_info i2c_pad_info2 = {
  63. .scl = {
  64. .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
  65. .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
  66. .gp = IMX_GPIO_NR(1, 3)
  67. },
  68. .sda = {
  69. .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | PC,
  70. .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC,
  71. .gp = IMX_GPIO_NR(7, 11)
  72. }
  73. };
  74. iomux_v3_cfg_t const usdhc3_pads[] = {
  75. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  76. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  77. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  78. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  79. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  80. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  82. };
  83. iomux_v3_cfg_t const enet_pads1[] = {
  84. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  85. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  86. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  87. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  88. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  89. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  90. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93. /* pin 35 - 1 (PHY_AD2) on reset */
  94. MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  95. /* pin 32 - 1 - (MODE0) all */
  96. MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
  97. /* pin 31 - 1 - (MODE1) all */
  98. MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
  99. /* pin 28 - 1 - (MODE2) all */
  100. MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  101. /* pin 27 - 1 - (MODE3) all */
  102. MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
  103. /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
  104. MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
  105. /* pin 42 PHY nRST */
  106. MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL),
  107. };
  108. iomux_v3_cfg_t const enet_pads2[] = {
  109. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  110. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  111. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  112. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  113. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  114. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  115. };
  116. iomux_v3_cfg_t nfc_pads[] = {
  117. MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
  118. MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
  119. MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  120. MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  121. MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  122. MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  123. MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  124. MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  125. MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  126. MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  127. MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  128. MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
  129. MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  130. MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
  131. MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  132. MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  133. MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  134. MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  135. MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
  136. };
  137. static void setup_gpmi_nand(void)
  138. {
  139. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  140. /* config gpmi nand iomux */
  141. imx_iomux_v3_setup_multiple_pads(nfc_pads,
  142. ARRAY_SIZE(nfc_pads));
  143. /* config gpmi and bch clock to 100 MHz */
  144. clrsetbits_le32(&mxc_ccm->cs2cdr,
  145. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  146. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  147. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  148. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  149. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  150. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  151. /* enable gpmi and bch clock gating */
  152. setbits_le32(&mxc_ccm->CCGR4,
  153. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  154. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  155. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  156. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  157. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  158. /* enable apbh clock gating */
  159. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  160. }
  161. static void setup_iomux_enet(void)
  162. {
  163. gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
  164. gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
  165. gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
  166. gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
  167. gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
  168. gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
  169. imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
  170. gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
  171. /* Need delay 10ms according to KSZ9021 spec */
  172. udelay(1000 * 10);
  173. gpio_set_value(IMX_GPIO_NR(3, 23), 1);
  174. imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
  175. }
  176. static void setup_iomux_uart(void)
  177. {
  178. imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  179. imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  180. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  181. }
  182. #ifdef CONFIG_USB_EHCI_MX6
  183. int board_ehci_hcd_init(int port)
  184. {
  185. return 0;
  186. }
  187. #endif
  188. #ifdef CONFIG_FSL_ESDHC_IMX
  189. struct fsl_esdhc_cfg usdhc_cfg[1] = {
  190. { USDHC3_BASE_ADDR },
  191. };
  192. int board_mmc_getcd(struct mmc *mmc)
  193. {
  194. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  195. if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
  196. gpio_direction_input(IMX_GPIO_NR(7, 0));
  197. return !gpio_get_value(IMX_GPIO_NR(7, 0));
  198. }
  199. return 0;
  200. }
  201. int board_mmc_init(bd_t *bis)
  202. {
  203. /*
  204. * Only one USDHC controller on titianium
  205. */
  206. imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  207. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  208. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  209. }
  210. #endif
  211. int board_phy_config(struct phy_device *phydev)
  212. {
  213. /* min rx data delay */
  214. ksz9021_phy_extended_write(phydev,
  215. MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
  216. /* min tx data delay */
  217. ksz9021_phy_extended_write(phydev,
  218. MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
  219. /* max rx/tx clock delay, min rx/tx control */
  220. ksz9021_phy_extended_write(phydev,
  221. MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
  222. if (phydev->drv->config)
  223. phydev->drv->config(phydev);
  224. return 0;
  225. }
  226. int board_eth_init(bd_t *bis)
  227. {
  228. setup_iomux_enet();
  229. return cpu_eth_init(bis);
  230. }
  231. int board_early_init_f(void)
  232. {
  233. setup_iomux_uart();
  234. return 0;
  235. }
  236. int board_init(void)
  237. {
  238. /* address of boot parameters */
  239. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  240. setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
  241. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  242. setup_gpmi_nand();
  243. return 0;
  244. }
  245. int checkboard(void)
  246. {
  247. puts("Board: Titanium\n");
  248. return 0;
  249. }
  250. #ifdef CONFIG_CMD_BMODE
  251. static const struct boot_mode board_boot_modes[] = {
  252. /* NAND */
  253. { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
  254. /* 4 bit bus width */
  255. { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
  256. { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
  257. { NULL, 0 },
  258. };
  259. #endif
  260. int misc_init_r(void)
  261. {
  262. #ifdef CONFIG_CMD_BMODE
  263. add_board_boot_modes(board_boot_modes);
  264. #endif
  265. return 0;
  266. }