platinum.c 5.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2014, Barco (www.barco.com)
  4. * Copyright (C) 2014 Stefan Roese <sr@denx.de>
  5. */
  6. #include <common.h>
  7. #include <mmc.h>
  8. #include <fsl_esdhc_imx.h>
  9. #include <miiphy.h>
  10. #include <netdev.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/clock.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/iomux.h>
  15. #include <asm/arch/mx6-pins.h>
  16. #include <asm/arch/crm_regs.h>
  17. #include <asm/arch/sys_proto.h>
  18. #include <asm/gpio.h>
  19. #include <asm/mach-imx/iomux-v3.h>
  20. #include <asm/mach-imx/boot_mode.h>
  21. #include "platinum.h"
  22. DECLARE_GLOBAL_DATA_PTR;
  23. iomux_v3_cfg_t const usdhc3_pads[] = {
  24. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  25. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  26. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  27. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  28. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  29. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  30. MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  31. };
  32. iomux_v3_cfg_t nfc_pads[] = {
  33. MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
  34. MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
  35. MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  36. MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  37. MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  38. MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  39. MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  40. MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  41. MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  42. MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  43. MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  44. MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
  45. MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
  46. MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
  47. MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  48. MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  49. MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
  50. MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
  51. MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
  52. };
  53. struct fsl_esdhc_cfg usdhc_cfg[] = {
  54. { USDHC3_BASE_ADDR },
  55. };
  56. void setup_gpmi_nand(void)
  57. {
  58. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  59. /* config gpmi nand iomux */
  60. imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
  61. /* config gpmi and bch clock to 100 MHz */
  62. clrsetbits_le32(&mxc_ccm->cs2cdr,
  63. MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  64. MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  65. MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  66. MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  67. MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  68. MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  69. /* enable gpmi and bch clock gating */
  70. setbits_le32(&mxc_ccm->CCGR4,
  71. MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  72. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  73. MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  74. MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  75. MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  76. /* enable apbh clock gating */
  77. setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  78. }
  79. int dram_init(void)
  80. {
  81. gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  82. return 0;
  83. }
  84. int board_ehci_hcd_init(int port)
  85. {
  86. return 0;
  87. }
  88. int board_mmc_getcd(struct mmc *mmc)
  89. {
  90. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  91. if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) {
  92. unsigned sd3_cd = IMX_GPIO_NR(7, 0);
  93. gpio_direction_input(sd3_cd);
  94. return !gpio_get_value(sd3_cd);
  95. }
  96. return 0;
  97. }
  98. int board_mmc_init(bd_t *bis)
  99. {
  100. imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  101. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  102. return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
  103. }
  104. void board_init_gpio(void)
  105. {
  106. platinum_init_gpio();
  107. }
  108. void board_init_gpmi_nand(void)
  109. {
  110. setup_gpmi_nand();
  111. }
  112. void board_init_i2c(void)
  113. {
  114. platinum_setup_i2c();
  115. }
  116. void board_init_spi(void)
  117. {
  118. platinum_setup_spi();
  119. }
  120. void board_init_uart(void)
  121. {
  122. platinum_setup_uart();
  123. }
  124. void board_init_usb(void)
  125. {
  126. platinum_init_usb();
  127. }
  128. void board_init_finished(void)
  129. {
  130. platinum_init_finished();
  131. }
  132. int board_phy_config(struct phy_device *phydev)
  133. {
  134. return platinum_phy_config(phydev);
  135. }
  136. int board_eth_init(bd_t *bis)
  137. {
  138. return cpu_eth_init(bis);
  139. }
  140. int board_early_init_f(void)
  141. {
  142. board_init_uart();
  143. return 0;
  144. }
  145. int board_init(void)
  146. {
  147. /* address of boot parameters */
  148. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  149. board_init_spi();
  150. board_init_i2c();
  151. board_init_gpmi_nand();
  152. board_init_gpio();
  153. board_init_usb();
  154. board_init_finished();
  155. return 0;
  156. }
  157. int checkboard(void)
  158. {
  159. puts("Board: " CONFIG_PLATINUM_BOARD "\n");
  160. return 0;
  161. }
  162. static const struct boot_mode board_boot_modes[] = {
  163. /* NAND */
  164. { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
  165. /* 4 bit bus width */
  166. { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
  167. { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
  168. { NULL, 0 },
  169. };
  170. int misc_init_r(void)
  171. {
  172. add_board_boot_modes(board_boot_modes);
  173. return 0;
  174. }