dms-ba16.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Timesys Corporation
  4. * Copyright 2016 Advantech Corporation
  5. * Copyright 2012 Freescale Semiconductor, Inc.
  6. */
  7. #include <asm/arch/clock.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <asm/arch/iomux.h>
  10. #include <asm/arch/mx6-pins.h>
  11. #include <linux/errno.h>
  12. #include <asm/gpio.h>
  13. #include <asm/mach-imx/mxc_i2c.h>
  14. #include <asm/mach-imx/iomux-v3.h>
  15. #include <asm/mach-imx/boot_mode.h>
  16. #include <asm/mach-imx/video.h>
  17. #include <mmc.h>
  18. #include <fsl_esdhc_imx.h>
  19. #include <miiphy.h>
  20. #include <netdev.h>
  21. #include <asm/arch/mxc_hdmi.h>
  22. #include <asm/arch/crm_regs.h>
  23. #include <asm/io.h>
  24. #include <asm/arch/sys_proto.h>
  25. #include <i2c.h>
  26. #include <input.h>
  27. #include <pwm.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  30. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  31. PAD_CTL_HYS)
  32. #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  33. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
  34. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  35. #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
  36. PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
  37. PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  38. #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
  39. PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
  40. #define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
  41. PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)
  42. #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  43. PAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)
  44. #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  45. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  46. #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
  47. PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
  48. PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  49. #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  50. int dram_init(void)
  51. {
  52. gd->ram_size = imx_ddr_size();
  53. return 0;
  54. }
  55. static iomux_v3_cfg_t const uart3_pads[] = {
  56. MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  57. MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
  58. MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  59. MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  60. };
  61. static iomux_v3_cfg_t const uart4_pads[] = {
  62. MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  63. MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  64. };
  65. static iomux_v3_cfg_t const enet_pads[] = {
  66. MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67. MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68. MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69. MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70. MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71. MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72. MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73. MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74. MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
  75. MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  76. MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  77. MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  78. MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  79. MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  80. MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
  81. /* AR8033 PHY Reset */
  82. MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
  83. };
  84. static void setup_iomux_enet(void)
  85. {
  86. imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  87. /* Reset AR8033 PHY */
  88. gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
  89. mdelay(10);
  90. gpio_set_value(IMX_GPIO_NR(1, 28), 1);
  91. mdelay(1);
  92. }
  93. static iomux_v3_cfg_t const usdhc2_pads[] = {
  94. MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  95. MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  96. MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  97. MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98. MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99. MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  100. MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
  101. };
  102. static iomux_v3_cfg_t const usdhc3_pads[] = {
  103. MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  104. MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  105. MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  106. MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  107. MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  108. MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  109. MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  110. MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  111. MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  112. MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  113. MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  114. };
  115. static iomux_v3_cfg_t const usdhc4_pads[] = {
  116. MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  117. MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  118. MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  119. MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  120. MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  121. MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  122. MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  123. MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  124. MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  125. MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  126. MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  127. MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  128. };
  129. static iomux_v3_cfg_t const ecspi1_pads[] = {
  130. MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  131. MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  132. MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  133. MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
  134. };
  135. static struct i2c_pads_info i2c_pad_info1 = {
  136. .scl = {
  137. .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
  138. .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
  139. .gp = IMX_GPIO_NR(5, 27)
  140. },
  141. .sda = {
  142. .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
  143. .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
  144. .gp = IMX_GPIO_NR(5, 26)
  145. }
  146. };
  147. static struct i2c_pads_info i2c_pad_info2 = {
  148. .scl = {
  149. .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
  150. .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
  151. .gp = IMX_GPIO_NR(4, 12)
  152. },
  153. .sda = {
  154. .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
  155. .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
  156. .gp = IMX_GPIO_NR(4, 13)
  157. }
  158. };
  159. static struct i2c_pads_info i2c_pad_info3 = {
  160. .scl = {
  161. .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
  162. .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
  163. .gp = IMX_GPIO_NR(1, 3)
  164. },
  165. .sda = {
  166. .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
  167. .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
  168. .gp = IMX_GPIO_NR(1, 6)
  169. }
  170. };
  171. #ifdef CONFIG_MXC_SPI
  172. int board_spi_cs_gpio(unsigned bus, unsigned cs)
  173. {
  174. return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
  175. }
  176. static void setup_spi(void)
  177. {
  178. imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
  179. }
  180. #endif
  181. static iomux_v3_cfg_t const pcie_pads[] = {
  182. MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
  183. MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
  184. };
  185. static void setup_pcie(void)
  186. {
  187. imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
  188. }
  189. static void setup_iomux_uart(void)
  190. {
  191. imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
  192. imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
  193. }
  194. #ifdef CONFIG_FSL_ESDHC_IMX
  195. struct fsl_esdhc_cfg usdhc_cfg[3] = {
  196. {USDHC2_BASE_ADDR},
  197. {USDHC3_BASE_ADDR},
  198. {USDHC4_BASE_ADDR},
  199. };
  200. #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
  201. #define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
  202. int board_mmc_getcd(struct mmc *mmc)
  203. {
  204. struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  205. int ret = 0;
  206. switch (cfg->esdhc_base) {
  207. case USDHC2_BASE_ADDR:
  208. ret = !gpio_get_value(USDHC2_CD_GPIO);
  209. break;
  210. case USDHC3_BASE_ADDR:
  211. ret = 1; /* eMMC is always present */
  212. break;
  213. case USDHC4_BASE_ADDR:
  214. ret = !gpio_get_value(USDHC4_CD_GPIO);
  215. break;
  216. }
  217. return ret;
  218. }
  219. int board_mmc_init(bd_t *bis)
  220. {
  221. int ret;
  222. int i;
  223. for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  224. switch (i) {
  225. case 0:
  226. imx_iomux_v3_setup_multiple_pads(
  227. usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
  228. gpio_direction_input(USDHC2_CD_GPIO);
  229. usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  230. break;
  231. case 1:
  232. imx_iomux_v3_setup_multiple_pads(
  233. usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  234. usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  235. break;
  236. case 2:
  237. imx_iomux_v3_setup_multiple_pads(
  238. usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
  239. gpio_direction_input(USDHC4_CD_GPIO);
  240. usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
  241. break;
  242. default:
  243. printf("Warning: you configured more USDHC controllers\n"
  244. "(%d) then supported by the board (%d)\n",
  245. i + 1, CONFIG_SYS_FSL_USDHC_NUM);
  246. return -EINVAL;
  247. }
  248. ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  249. if (ret)
  250. return ret;
  251. }
  252. return 0;
  253. }
  254. #endif
  255. static int mx6_rgmii_rework(struct phy_device *phydev)
  256. {
  257. /* set device address 0x7 */
  258. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  259. /* offset 0x8016: CLK_25M Clock Select */
  260. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  261. /* enable register write, no post increment, address 0x7 */
  262. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  263. /* set to 125 MHz from local PLL source */
  264. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
  265. /* set debug port address: SerDes Test and System Mode Control */
  266. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  267. /* enable rgmii tx clock delay */
  268. /* set the reserved bits to avoid board specific voltage peak issue*/
  269. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47);
  270. return 0;
  271. }
  272. int board_phy_config(struct phy_device *phydev)
  273. {
  274. mx6_rgmii_rework(phydev);
  275. if (phydev->drv->config)
  276. phydev->drv->config(phydev);
  277. return 0;
  278. }
  279. #if defined(CONFIG_VIDEO_IPUV3)
  280. static iomux_v3_cfg_t const backlight_pads[] = {
  281. /* Power for LVDS Display */
  282. MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
  283. #define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
  284. /* Backlight enable for LVDS display */
  285. MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
  286. #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
  287. /* backlight PWM brightness control */
  288. MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
  289. };
  290. static void do_enable_hdmi(struct display_info_t const *dev)
  291. {
  292. imx_enable_hdmi_phy();
  293. }
  294. int board_cfb_skip(void)
  295. {
  296. gpio_direction_output(LVDS_POWER_GP, 1);
  297. return 0;
  298. }
  299. static int detect_baseboard(struct display_info_t const *dev)
  300. {
  301. return 0 == dev->addr;
  302. }
  303. struct display_info_t const displays[] = {{
  304. .bus = -1,
  305. .addr = 0,
  306. .pixfmt = IPU_PIX_FMT_RGB24,
  307. .detect = detect_baseboard,
  308. .enable = NULL,
  309. .mode = {
  310. .name = "SHARP-LQ156M1LG21",
  311. .refresh = 60,
  312. .xres = 1920,
  313. .yres = 1080,
  314. .pixclock = 7851,
  315. .left_margin = 100,
  316. .right_margin = 40,
  317. .upper_margin = 30,
  318. .lower_margin = 3,
  319. .hsync_len = 10,
  320. .vsync_len = 2,
  321. .sync = FB_SYNC_EXT,
  322. .vmode = FB_VMODE_NONINTERLACED
  323. } }, {
  324. .bus = -1,
  325. .addr = 3,
  326. .pixfmt = IPU_PIX_FMT_RGB24,
  327. .detect = detect_hdmi,
  328. .enable = do_enable_hdmi,
  329. .mode = {
  330. .name = "HDMI",
  331. .refresh = 60,
  332. .xres = 1024,
  333. .yres = 768,
  334. .pixclock = 15385,
  335. .left_margin = 220,
  336. .right_margin = 40,
  337. .upper_margin = 21,
  338. .lower_margin = 7,
  339. .hsync_len = 60,
  340. .vsync_len = 10,
  341. .sync = FB_SYNC_EXT,
  342. .vmode = FB_VMODE_NONINTERLACED
  343. } } };
  344. size_t display_count = ARRAY_SIZE(displays);
  345. static void setup_display(void)
  346. {
  347. struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  348. struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  349. clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  350. imx_setup_hdmi();
  351. /* Set LDB_DI0 as clock source for IPU_DI0 */
  352. clrsetbits_le32(&mxc_ccm->chsccdr,
  353. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
  354. (CHSCCDR_CLK_SEL_LDB_DI0 <<
  355. MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
  356. /* Turn on IPU LDB DI0 clocks */
  357. setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  358. enable_ipu_clock();
  359. writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  360. IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
  361. IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  362. IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  363. IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
  364. IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  365. IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
  366. IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
  367. IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
  368. IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
  369. &iomux->gpr[2]);
  370. clrsetbits_le32(&iomux->gpr[3],
  371. IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
  372. IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
  373. IOMUXC_GPR3_HDMI_MUX_CTL_MASK,
  374. (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
  375. IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
  376. /* backlights off until needed */
  377. imx_iomux_v3_setup_multiple_pads(backlight_pads,
  378. ARRAY_SIZE(backlight_pads));
  379. gpio_direction_input(LVDS_POWER_GP);
  380. gpio_direction_input(LVDS_BACKLIGHT_GP);
  381. }
  382. #endif /* CONFIG_VIDEO_IPUV3 */
  383. /*
  384. * Do not overwrite the console
  385. * Use always serial for U-Boot console
  386. */
  387. int overwrite_console(void)
  388. {
  389. return 1;
  390. }
  391. int board_eth_init(bd_t *bis)
  392. {
  393. setup_iomux_enet();
  394. setup_pcie();
  395. return cpu_eth_init(bis);
  396. }
  397. static iomux_v3_cfg_t const misc_pads[] = {
  398. MX6_PAD_KEY_ROW2__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  399. MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NC_PAD_CTRL),
  400. MX6_PAD_EIM_CS0__GPIO2_IO23 | MUX_PAD_CTRL(NC_PAD_CTRL),
  401. MX6_PAD_EIM_CS1__GPIO2_IO24 | MUX_PAD_CTRL(NC_PAD_CTRL),
  402. MX6_PAD_EIM_OE__GPIO2_IO25 | MUX_PAD_CTRL(NC_PAD_CTRL),
  403. MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NC_PAD_CTRL),
  404. MX6_PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NC_PAD_CTRL),
  405. };
  406. #define SUS_S3_OUT IMX_GPIO_NR(4, 11)
  407. #define WIFI_EN IMX_GPIO_NR(6, 14)
  408. int setup_ba16_sata(void)
  409. {
  410. struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  411. int ret;
  412. ret = enable_sata_clock();
  413. if (ret)
  414. return ret;
  415. clrsetbits_le32(&iomuxc_regs->gpr[13],
  416. IOMUXC_GPR13_SATA_MASK,
  417. IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
  418. |IOMUXC_GPR13_SATA_PHY_7_SATA2M
  419. |IOMUXC_GPR13_SATA_SPEED_3G
  420. |(1<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
  421. |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
  422. |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_12_16
  423. |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_3P33_DB
  424. |IOMUXC_GPR13_SATA_PHY_2_TX_1P133V
  425. |IOMUXC_GPR13_SATA_PHY_1_SLOW);
  426. return 0;
  427. }
  428. int board_early_init_f(void)
  429. {
  430. imx_iomux_v3_setup_multiple_pads(misc_pads,
  431. ARRAY_SIZE(misc_pads));
  432. setup_iomux_uart();
  433. #if defined(CONFIG_VIDEO_IPUV3)
  434. /* Set LDB clock to PLL2 PFD0 */
  435. select_ldb_di_clock_source(MXC_PLL2_PFD0_CLK);
  436. #endif
  437. return 0;
  438. }
  439. int board_init(void)
  440. {
  441. gpio_direction_output(SUS_S3_OUT, 1);
  442. gpio_direction_output(WIFI_EN, 1);
  443. #if defined(CONFIG_VIDEO_IPUV3)
  444. setup_display();
  445. #endif
  446. /* address of boot parameters */
  447. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  448. #ifdef CONFIG_MXC_SPI
  449. setup_spi();
  450. #endif
  451. setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  452. setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  453. setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
  454. return 0;
  455. }
  456. #ifdef CONFIG_CMD_BMODE
  457. static const struct boot_mode board_boot_modes[] = {
  458. /* 4 bit bus width */
  459. {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
  460. {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  461. {NULL, 0},
  462. };
  463. #endif
  464. void pmic_init(void)
  465. {
  466. #define DA9063_ADDR 0x58
  467. #define BCORE2_CONF 0x9D
  468. #define BCORE1_CONF 0x9E
  469. #define BPRO_CONF 0x9F
  470. #define BIO_CONF 0xA0
  471. #define BMEM_CONF 0xA1
  472. #define BPERI_CONF 0xA2
  473. #define MODE_BIT_H 7
  474. #define MODE_BIT_L 6
  475. uchar val;
  476. i2c_set_bus_num(2);
  477. i2c_read(DA9063_ADDR, BCORE2_CONF, 1, &val, 1);
  478. val |= (1 << MODE_BIT_H);
  479. val &= ~(1 << MODE_BIT_L);
  480. i2c_write(DA9063_ADDR, BCORE2_CONF , 1, &val, 1);
  481. i2c_read(DA9063_ADDR, BCORE1_CONF, 1, &val, 1);
  482. val |= (1 << MODE_BIT_H);
  483. val &= ~(1 << MODE_BIT_L);
  484. i2c_write(DA9063_ADDR, BCORE1_CONF , 1, &val, 1);
  485. i2c_read(DA9063_ADDR, BPRO_CONF, 1, &val, 1);
  486. val |= (1 << MODE_BIT_H);
  487. val &= ~(1 << MODE_BIT_L);
  488. i2c_write(DA9063_ADDR, BPRO_CONF , 1, &val, 1);
  489. i2c_read(DA9063_ADDR, BIO_CONF, 1, &val, 1);
  490. val |= (1 << MODE_BIT_H);
  491. val &= ~(1 << MODE_BIT_L);
  492. i2c_write(DA9063_ADDR, BIO_CONF , 1, &val, 1);
  493. i2c_read(DA9063_ADDR, BMEM_CONF, 1, &val, 1);
  494. val |= (1 << MODE_BIT_H);
  495. val &= ~(1 << MODE_BIT_L);
  496. i2c_write(DA9063_ADDR, BMEM_CONF , 1, &val, 1);
  497. i2c_read(DA9063_ADDR, BPERI_CONF, 1, &val, 1);
  498. val |= (1 << MODE_BIT_H);
  499. val &= ~(1 << MODE_BIT_L);
  500. i2c_write(DA9063_ADDR, BPERI_CONF , 1, &val, 1);
  501. }
  502. int board_late_init(void)
  503. {
  504. #ifdef CONFIG_CMD_BMODE
  505. add_board_boot_modes(board_boot_modes);
  506. #endif
  507. #if defined(CONFIG_VIDEO_IPUV3)
  508. /*
  509. * We need at least 200ms between power on and backlight on
  510. * as per specifications from CHI MEI
  511. */
  512. mdelay(250);
  513. /* enable backlight PWM 1 */
  514. pwm_init(0, 0, 0);
  515. /* duty cycle 5000000ns, period: 5000000ns */
  516. pwm_config(0, 5000000, 5000000);
  517. /* Backlight Power */
  518. gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
  519. pwm_enable(0);
  520. #endif
  521. #ifdef CONFIG_SATA
  522. setup_ba16_sata();
  523. #endif
  524. /* board specific pmic init */
  525. pmic_init();
  526. return 0;
  527. }
  528. int checkboard(void)
  529. {
  530. printf("BOARD: %s\n", CONFIG_BOARD_NAME);
  531. return 0;
  532. }