cpu_init.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. *
  4. * (C) Copyright 2000-2003
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
  8. * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
  9. */
  10. #include <common.h>
  11. #include <watchdog.h>
  12. #include <asm/immap.h>
  13. #include <asm/processor.h>
  14. #include <asm/rtc.h>
  15. #include <asm/io.h>
  16. #include <linux/compiler.h>
  17. #if defined(CONFIG_CMD_NET)
  18. #include <config.h>
  19. #include <net.h>
  20. #include <asm/fec.h>
  21. #endif
  22. void init_fbcs(void)
  23. {
  24. fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
  25. #if !defined(CONFIG_SERIAL_BOOT)
  26. #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
  27. out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  28. out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  29. out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
  30. #endif
  31. #endif
  32. #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
  33. /* Latch chipselect */
  34. out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  35. out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  36. out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
  37. #endif
  38. #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
  39. out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  40. out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  41. out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
  42. #endif
  43. #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
  44. out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  45. out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  46. out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
  47. #endif
  48. #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
  49. out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  50. out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  51. out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
  52. #endif
  53. #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
  54. out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  55. out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  56. out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
  57. #endif
  58. }
  59. #ifdef CONFIG_CF_DSPI
  60. void cfspi_port_conf(void)
  61. {
  62. gpio_t *gpio = (gpio_t *)MMAP_GPIO;
  63. #ifdef CONFIG_MCF5445x
  64. out_8(&gpio->par_dspi,
  65. GPIO_PAR_DSPI_SIN_SIN |
  66. GPIO_PAR_DSPI_SOUT_SOUT |
  67. GPIO_PAR_DSPI_SCK_SCK);
  68. #endif
  69. #ifdef CONFIG_MCF5441x
  70. pm_t *pm = (pm_t *)MMAP_PM;
  71. out_8(&gpio->par_dspi0,
  72. GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
  73. GPIO_PAR_DSPI0_SCK_DSPI0SCK);
  74. out_8(&gpio->srcr_dspiow, 3);
  75. /* DSPI0 */
  76. out_8(&pm->pmcr0, 23);
  77. #endif
  78. }
  79. #endif
  80. /*
  81. * Breath some life into the CPU...
  82. *
  83. * Set up the memory map,
  84. * initialize a bunch of registers,
  85. * initialize the UPM's
  86. */
  87. void cpu_init_f(void)
  88. {
  89. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  90. #ifdef CONFIG_MCF5441x
  91. scm_t *scm = (scm_t *) MMAP_SCM;
  92. pm_t *pm = (pm_t *) MMAP_PM;
  93. /* Disable Switch */
  94. *(unsigned long *)(MMAP_L2_SW0 + 0x00000024) = 0;
  95. /* Disable core watchdog */
  96. out_be16(&scm->cwcr, 0);
  97. out_8(&gpio->par_fbctl,
  98. GPIO_PAR_FBCTL_ALE_FB_ALE | GPIO_PAR_FBCTL_OE_FB_OE |
  99. GPIO_PAR_FBCTL_FBCLK | GPIO_PAR_FBCTL_RW |
  100. GPIO_PAR_FBCTL_TA_TA);
  101. out_8(&gpio->par_be,
  102. GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
  103. GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
  104. /* eDMA */
  105. out_8(&pm->pmcr0, 17);
  106. /* INTR0 - INTR2 */
  107. out_8(&pm->pmcr0, 18);
  108. out_8(&pm->pmcr0, 19);
  109. out_8(&pm->pmcr0, 20);
  110. /* I2C */
  111. out_8(&pm->pmcr0, 22);
  112. out_8(&pm->pmcr1, 4);
  113. out_8(&pm->pmcr1, 7);
  114. /* DTMR0 - DTMR3*/
  115. out_8(&pm->pmcr0, 28);
  116. out_8(&pm->pmcr0, 29);
  117. out_8(&pm->pmcr0, 30);
  118. out_8(&pm->pmcr0, 31);
  119. /* PIT0 - PIT3 */
  120. out_8(&pm->pmcr0, 32);
  121. out_8(&pm->pmcr0, 33);
  122. out_8(&pm->pmcr0, 34);
  123. out_8(&pm->pmcr0, 35);
  124. /* Edge Port */
  125. out_8(&pm->pmcr0, 36);
  126. out_8(&pm->pmcr0, 37);
  127. /* USB OTG */
  128. out_8(&pm->pmcr0, 44);
  129. /* USB Host */
  130. out_8(&pm->pmcr0, 45);
  131. /* ESDHC */
  132. out_8(&pm->pmcr0, 51);
  133. /* ENET0 - ENET1 */
  134. out_8(&pm->pmcr0, 53);
  135. out_8(&pm->pmcr0, 54);
  136. /* NAND */
  137. out_8(&pm->pmcr0, 63);
  138. #ifdef CONFIG_SYS_I2C_0
  139. out_8(&gpio->par_cani2c, 0xF0);
  140. /* I2C0 pull up */
  141. out_be16(&gpio->pcr_b, 0x003C);
  142. /* I2C0 max speed */
  143. out_8(&gpio->srcr_cani2c, 0x03);
  144. #endif
  145. #ifdef CONFIG_SYS_I2C_2
  146. /* I2C2 */
  147. out_8(&gpio->par_ssi0h, 0xA0);
  148. /* I2C2, UART7 */
  149. out_8(&gpio->par_ssi0h, 0xA8);
  150. /* UART7 */
  151. out_8(&gpio->par_ssi0l, 0x2);
  152. /* UART8, UART9 */
  153. out_8(&gpio->par_cani2c, 0xAA);
  154. /* UART4, UART0 */
  155. out_8(&gpio->par_uart0, 0xAF);
  156. /* UART5, UART1 */
  157. out_8(&gpio->par_uart1, 0xAF);
  158. /* UART6, UART2 */
  159. out_8(&gpio->par_uart2, 0xAF);
  160. /* I2C2 pull up */
  161. out_be16(&gpio->pcr_h, 0xF000);
  162. #endif
  163. #ifdef CONFIG_SYS_I2C_5
  164. /* I2C5 */
  165. out_8(&gpio->par_uart1, 0x0A);
  166. /* I2C5 pull up */
  167. out_be16(&gpio->pcr_e, 0x0003);
  168. out_be16(&gpio->pcr_f, 0xC000);
  169. #endif
  170. /* Lowest slew rate for UART0,1,2 */
  171. out_8(&gpio->srcr_uart, 0x00);
  172. #ifdef CONFIG_FSL_ESDHC_IMX
  173. /* eSDHC pin as faster speed */
  174. out_8(&gpio->srcr_sdhc, 0x03);
  175. /* All esdhc pins as SD */
  176. out_8(&gpio->par_sdhch, 0xff);
  177. out_8(&gpio->par_sdhcl, 0xff);
  178. #endif
  179. #endif /* CONFIG_MCF5441x */
  180. #ifdef CONFIG_MCF5445x
  181. scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  182. out_be32(&scm1->mpr, 0x77777777);
  183. out_be32(&scm1->pacra, 0);
  184. out_be32(&scm1->pacrb, 0);
  185. out_be32(&scm1->pacrc, 0);
  186. out_be32(&scm1->pacrd, 0);
  187. out_be32(&scm1->pacre, 0);
  188. out_be32(&scm1->pacrf, 0);
  189. out_be32(&scm1->pacrg, 0);
  190. /* FlexBus */
  191. out_8(&gpio->par_be,
  192. GPIO_PAR_BE_BE3_BE3 | GPIO_PAR_BE_BE2_BE2 |
  193. GPIO_PAR_BE_BE1_BE1 | GPIO_PAR_BE_BE0_BE0);
  194. out_8(&gpio->par_fbctl,
  195. GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
  196. GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
  197. #ifdef CONFIG_CF_SPI
  198. cfspi_port_conf();
  199. #endif
  200. #ifdef CONFIG_SYS_FSL_I2C
  201. out_be16(&gpio->par_feci2c,
  202. GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
  203. #endif
  204. #endif /* CONFIG_MCF5445x */
  205. /* FlexBus Chipselect */
  206. init_fbcs();
  207. #ifdef CONFIG_SYS_CS0_BASE
  208. /*
  209. * now the flash base address is no longer at 0 (Newer ColdFire family
  210. * boot at address 0 instead of 0xFFnn_nnnn). The vector table must
  211. * also move to the new location.
  212. */
  213. if (CONFIG_SYS_CS0_BASE != 0)
  214. setvbr(CONFIG_SYS_CS0_BASE);
  215. #endif
  216. icache_enable();
  217. }
  218. /*
  219. * initialize higher level parts of CPU like timers
  220. */
  221. int cpu_init_r(void)
  222. {
  223. #ifdef CONFIG_MCFRTC
  224. rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
  225. rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
  226. out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
  227. out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
  228. #endif
  229. return (0);
  230. }
  231. void uart_port_conf(int port)
  232. {
  233. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  234. #ifdef CONFIG_MCF5441x
  235. pm_t *pm = (pm_t *) MMAP_PM;
  236. #endif
  237. /* Setup Ports: */
  238. switch (port) {
  239. #ifdef CONFIG_MCF5441x
  240. case 0:
  241. /* UART0 */
  242. out_8(&pm->pmcr0, 24);
  243. clrbits_8(&gpio->par_uart0,
  244. ~(GPIO_PAR_UART0_U0RXD_MASK | GPIO_PAR_UART0_U0TXD_MASK));
  245. setbits_8(&gpio->par_uart0,
  246. GPIO_PAR_UART0_U0RXD_U0RXD | GPIO_PAR_UART0_U0TXD_U0TXD);
  247. break;
  248. case 1:
  249. /* UART1 */
  250. out_8(&pm->pmcr0, 25);
  251. clrbits_8(&gpio->par_uart1,
  252. ~(GPIO_PAR_UART1_U1RXD_MASK | GPIO_PAR_UART1_U1TXD_MASK));
  253. setbits_8(&gpio->par_uart1,
  254. GPIO_PAR_UART1_U1RXD_U1RXD | GPIO_PAR_UART1_U1TXD_U1TXD);
  255. break;
  256. case 2:
  257. /* UART2 */
  258. out_8(&pm->pmcr0, 26);
  259. clrbits_8(&gpio->par_uart2,
  260. ~(GPIO_PAR_UART2_U2RXD_MASK | GPIO_PAR_UART2_U2TXD_MASK));
  261. setbits_8(&gpio->par_uart2,
  262. GPIO_PAR_UART2_U2RXD_U2RXD | GPIO_PAR_UART2_U2TXD_U2TXD);
  263. break;
  264. case 3:
  265. /* UART3 */
  266. out_8(&pm->pmcr0, 27);
  267. clrbits_8(&gpio->par_dspi0,
  268. ~(GPIO_PAR_DSPI0_SIN_MASK | GPIO_PAR_DSPI0_SOUT_MASK));
  269. setbits_8(&gpio->par_dspi0,
  270. GPIO_PAR_DSPI0_SIN_U3RXD | GPIO_PAR_DSPI0_SOUT_U3TXD);
  271. break;
  272. case 4:
  273. /* UART4 */
  274. out_8(&pm->pmcr1, 24);
  275. clrbits_8(&gpio->par_uart0,
  276. ~(GPIO_PAR_UART0_U0CTS_MASK | GPIO_PAR_UART0_U0RTS_MASK));
  277. setbits_8(&gpio->par_uart0,
  278. GPIO_PAR_UART0_U0CTS_U4TXD | GPIO_PAR_UART0_U0RTS_U4RXD);
  279. break;
  280. case 5:
  281. /* UART5 */
  282. out_8(&pm->pmcr1, 25);
  283. clrbits_8(&gpio->par_uart1,
  284. ~(GPIO_PAR_UART1_U1CTS_MASK | GPIO_PAR_UART1_U1RTS_MASK));
  285. setbits_8(&gpio->par_uart1,
  286. GPIO_PAR_UART1_U1CTS_U5TXD | GPIO_PAR_UART1_U1RTS_U5RXD);
  287. break;
  288. case 6:
  289. /* UART6 */
  290. out_8(&pm->pmcr1, 26);
  291. clrbits_8(&gpio->par_uart2,
  292. ~(GPIO_PAR_UART2_U2CTS_MASK | GPIO_PAR_UART2_U2RTS_MASK));
  293. setbits_8(&gpio->par_uart2,
  294. GPIO_PAR_UART2_U2CTS_U6TXD | GPIO_PAR_UART2_U2RTS_U6RXD);
  295. break;
  296. case 7:
  297. /* UART7 */
  298. out_8(&pm->pmcr1, 27);
  299. clrbits_8(&gpio->par_ssi0h, ~GPIO_PAR_SSI0H_RXD_MASK);
  300. clrbits_8(&gpio->par_ssi0l, ~GPIO_PAR_SSI0L_BCLK_MASK);
  301. setbits_8(&gpio->par_ssi0h, GPIO_PAR_SSI0H_FS_U7TXD);
  302. setbits_8(&gpio->par_ssi0l, GPIO_PAR_SSI0L_BCLK_U7RXD);
  303. break;
  304. case 8:
  305. /* UART8 */
  306. out_8(&pm->pmcr0, 28);
  307. clrbits_8(&gpio->par_cani2c,
  308. ~(GPIO_PAR_CANI2C_I2C0SCL_MASK | GPIO_PAR_CANI2C_I2C0SDA_MASK));
  309. setbits_8(&gpio->par_cani2c,
  310. GPIO_PAR_CANI2C_I2C0SCL_U8TXD | GPIO_PAR_CANI2C_I2C0SDA_U8RXD);
  311. break;
  312. case 9:
  313. /* UART9 */
  314. out_8(&pm->pmcr1, 29);
  315. clrbits_8(&gpio->par_cani2c,
  316. ~(GPIO_PAR_CANI2C_CAN1TX_MASK | GPIO_PAR_CANI2C_CAN1RX_MASK));
  317. setbits_8(&gpio->par_cani2c,
  318. GPIO_PAR_CANI2C_CAN1TX_U9TXD | GPIO_PAR_CANI2C_CAN1RX_U9RXD);
  319. break;
  320. #endif
  321. #ifdef CONFIG_MCF5445x
  322. case 0:
  323. clrbits_8(&gpio->par_uart,
  324. GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
  325. setbits_8(&gpio->par_uart,
  326. GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
  327. break;
  328. case 1:
  329. #ifdef CONFIG_SYS_UART1_PRI_GPIO
  330. clrbits_8(&gpio->par_uart,
  331. GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
  332. setbits_8(&gpio->par_uart,
  333. GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
  334. #elif defined(CONFIG_SYS_UART1_ALT1_GPIO)
  335. clrbits_be16(&gpio->par_ssi,
  336. ~(GPIO_PAR_SSI_SRXD_UNMASK | GPIO_PAR_SSI_STXD_UNMASK));
  337. setbits_be16(&gpio->par_ssi,
  338. GPIO_PAR_SSI_SRXD_U1RXD | GPIO_PAR_SSI_STXD_U1TXD);
  339. #endif
  340. break;
  341. case 2:
  342. #if defined(CONFIG_SYS_UART2_ALT1_GPIO)
  343. clrbits_8(&gpio->par_timer,
  344. ~(GPIO_PAR_TIMER_T3IN_UNMASK | GPIO_PAR_TIMER_T2IN_UNMASK));
  345. setbits_8(&gpio->par_timer,
  346. GPIO_PAR_TIMER_T3IN_U2RXD | GPIO_PAR_TIMER_T2IN_U2TXD);
  347. #elif defined(CONFIG_SYS_UART2_ALT2_GPIO)
  348. clrbits_8(&gpio->par_timer,
  349. ~(GPIO_PAR_FECI2C_SCL_UNMASK | GPIO_PAR_FECI2C_SDA_UNMASK));
  350. setbits_8(&gpio->par_timer,
  351. GPIO_PAR_FECI2C_SCL_U2TXD | GPIO_PAR_FECI2C_SDA_U2RXD);
  352. #endif
  353. break;
  354. #endif /* CONFIG_MCF5445x */
  355. }
  356. }
  357. #if defined(CONFIG_CMD_NET)
  358. int fecpin_setclear(struct eth_device *dev, int setclear)
  359. {
  360. gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  361. #ifdef CONFIG_MCF5445x
  362. struct fec_info_s *info = (struct fec_info_s *)dev->priv;
  363. if (setclear) {
  364. #ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
  365. if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
  366. setbits_be16(&gpio->par_feci2c,
  367. GPIO_PAR_FECI2C_MDC0_MDC0 |
  368. GPIO_PAR_FECI2C_MDIO0_MDIO0);
  369. else
  370. setbits_be16(&gpio->par_feci2c,
  371. GPIO_PAR_FECI2C_MDC1_MDC1 |
  372. GPIO_PAR_FECI2C_MDIO1_MDIO1);
  373. #else
  374. setbits_be16(&gpio->par_feci2c,
  375. GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
  376. #endif
  377. if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
  378. setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_RMII_GPIO);
  379. else
  380. setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_RMII_ATA);
  381. } else {
  382. clrbits_be16(&gpio->par_feci2c,
  383. GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
  384. if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
  385. #ifdef CONFIG_SYS_FEC_FULL_MII
  386. setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC0_MII);
  387. #else
  388. clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC0_UNMASK);
  389. #endif
  390. } else {
  391. #ifdef CONFIG_SYS_FEC_FULL_MII
  392. setbits_8(&gpio->par_fec, GPIO_PAR_FEC_FEC1_MII);
  393. #else
  394. clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC1_UNMASK);
  395. #endif
  396. }
  397. }
  398. #endif /* CONFIG_MCF5445x */
  399. #ifdef CONFIG_MCF5441x
  400. if (setclear) {
  401. out_8(&gpio->par_fec, 0x03);
  402. out_8(&gpio->srcr_fec, 0x0F);
  403. clrsetbits_8(&gpio->par_simp0h, ~GPIO_PAR_SIMP0H_DAT_MASK,
  404. GPIO_PAR_SIMP0H_DAT_GPIO);
  405. clrsetbits_8(&gpio->pddr_g, ~GPIO_PDDR_G4_MASK,
  406. GPIO_PDDR_G4_OUTPUT);
  407. clrbits_8(&gpio->podr_g, ~GPIO_PODR_G4_MASK);
  408. } else
  409. clrbits_8(&gpio->par_fec, ~GPIO_PAR_FEC_FEC_MASK);
  410. #endif
  411. return 0;
  412. }
  413. #endif