cpu.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2009 Freescale Semiconductor, Inc.
  7. */
  8. #include <bootm.h>
  9. #include <common.h>
  10. #include <netdev.h>
  11. #include <linux/errno.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/arch/sys_proto.h>
  16. #include <asm/arch/crm_regs.h>
  17. #include <asm/mach-imx/boot_mode.h>
  18. #include <imx_thermal.h>
  19. #include <ipu_pixfmt.h>
  20. #include <thermal.h>
  21. #include <sata.h>
  22. #ifdef CONFIG_FSL_ESDHC_IMX
  23. #include <fsl_esdhc_imx.h>
  24. #endif
  25. static u32 reset_cause = -1;
  26. u32 get_imx_reset_cause(void)
  27. {
  28. struct src *src_regs = (struct src *)SRC_BASE_ADDR;
  29. if (reset_cause == -1) {
  30. reset_cause = readl(&src_regs->srsr);
  31. /* preserve the value for U-Boot proper */
  32. #if !defined(CONFIG_SPL_BUILD)
  33. writel(reset_cause, &src_regs->srsr);
  34. #endif
  35. }
  36. return reset_cause;
  37. }
  38. #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
  39. static char *get_reset_cause(void)
  40. {
  41. switch (get_imx_reset_cause()) {
  42. case 0x00001:
  43. case 0x00011:
  44. return "POR";
  45. case 0x00004:
  46. return "CSU";
  47. case 0x00008:
  48. return "IPP USER";
  49. case 0x00010:
  50. #ifdef CONFIG_MX7
  51. return "WDOG1";
  52. #else
  53. return "WDOG";
  54. #endif
  55. case 0x00020:
  56. return "JTAG HIGH-Z";
  57. case 0x00040:
  58. return "JTAG SW";
  59. case 0x00080:
  60. return "WDOG3";
  61. #ifdef CONFIG_MX7
  62. case 0x00100:
  63. return "WDOG4";
  64. case 0x00200:
  65. return "TEMPSENSE";
  66. #elif defined(CONFIG_IMX8M)
  67. case 0x00100:
  68. return "WDOG2";
  69. case 0x00200:
  70. return "TEMPSENSE";
  71. #else
  72. case 0x00100:
  73. return "TEMPSENSE";
  74. case 0x10000:
  75. return "WARM BOOT";
  76. #endif
  77. default:
  78. return "unknown reset";
  79. }
  80. }
  81. #endif
  82. #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
  83. #if defined(CONFIG_MX53)
  84. #define MEMCTL_BASE ESDCTL_BASE_ADDR
  85. #else
  86. #define MEMCTL_BASE MMDC_P0_BASE_ADDR
  87. #endif
  88. static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
  89. static const unsigned char bank_lookup[] = {3, 2};
  90. /* these MMDC registers are common to the IMX53 and IMX6 */
  91. struct esd_mmdc_regs {
  92. uint32_t ctl;
  93. uint32_t pdc;
  94. uint32_t otc;
  95. uint32_t cfg0;
  96. uint32_t cfg1;
  97. uint32_t cfg2;
  98. uint32_t misc;
  99. };
  100. #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
  101. #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
  102. #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
  103. #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
  104. #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
  105. /*
  106. * imx_ddr_size - return size in bytes of DRAM according MMDC config
  107. * The MMDC MDCTL register holds the number of bits for row, col, and data
  108. * width and the MMDC MDMISC register holds the number of banks. Combine
  109. * all these bits to determine the meme size the MMDC has been configured for
  110. */
  111. unsigned imx_ddr_size(void)
  112. {
  113. struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
  114. unsigned ctl = readl(&mem->ctl);
  115. unsigned misc = readl(&mem->misc);
  116. int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
  117. bits += ESD_MMDC_CTL_GET_ROW(ctl);
  118. bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
  119. bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
  120. bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
  121. bits += ESD_MMDC_CTL_GET_CS1(ctl);
  122. /* The MX6 can do only 3840 MiB of DRAM */
  123. if (bits == 32)
  124. return 0xf0000000;
  125. return 1 << bits;
  126. }
  127. #endif
  128. #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD)
  129. const char *get_imx_type(u32 imxtype)
  130. {
  131. switch (imxtype) {
  132. case MXC_CPU_IMX8MQ:
  133. return "8MQ"; /* Quad-core version of the imx8m */
  134. case MXC_CPU_MX7S:
  135. return "7S"; /* Single-core version of the mx7 */
  136. case MXC_CPU_MX7D:
  137. return "7D"; /* Dual-core version of the mx7 */
  138. case MXC_CPU_MX6QP:
  139. return "6QP"; /* Quad-Plus version of the mx6 */
  140. case MXC_CPU_MX6DP:
  141. return "6DP"; /* Dual-Plus version of the mx6 */
  142. case MXC_CPU_MX6Q:
  143. return "6Q"; /* Quad-core version of the mx6 */
  144. case MXC_CPU_MX6D:
  145. return "6D"; /* Dual-core version of the mx6 */
  146. case MXC_CPU_MX6DL:
  147. return "6DL"; /* Dual Lite version of the mx6 */
  148. case MXC_CPU_MX6SOLO:
  149. return "6SOLO"; /* Solo version of the mx6 */
  150. case MXC_CPU_MX6SL:
  151. return "6SL"; /* Solo-Lite version of the mx6 */
  152. case MXC_CPU_MX6SLL:
  153. return "6SLL"; /* SLL version of the mx6 */
  154. case MXC_CPU_MX6SX:
  155. return "6SX"; /* SoloX version of the mx6 */
  156. case MXC_CPU_MX6UL:
  157. return "6UL"; /* Ultra-Lite version of the mx6 */
  158. case MXC_CPU_MX6ULL:
  159. return "6ULL"; /* ULL version of the mx6 */
  160. case MXC_CPU_MX51:
  161. return "51";
  162. case MXC_CPU_MX53:
  163. return "53";
  164. default:
  165. return "??";
  166. }
  167. }
  168. int print_cpuinfo(void)
  169. {
  170. u32 cpurev;
  171. __maybe_unused u32 max_freq;
  172. cpurev = get_cpu_rev();
  173. #if defined(CONFIG_IMX_THERMAL)
  174. struct udevice *thermal_dev;
  175. int cpu_tmp, minc, maxc, ret;
  176. printf("CPU: Freescale i.MX%s rev%d.%d",
  177. get_imx_type((cpurev & 0xFF000) >> 12),
  178. (cpurev & 0x000F0) >> 4,
  179. (cpurev & 0x0000F) >> 0);
  180. max_freq = get_cpu_speed_grade_hz();
  181. if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
  182. printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  183. } else {
  184. printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
  185. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  186. }
  187. #else
  188. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  189. get_imx_type((cpurev & 0xFF000) >> 12),
  190. (cpurev & 0x000F0) >> 4,
  191. (cpurev & 0x0000F) >> 0,
  192. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  193. #endif
  194. #if defined(CONFIG_IMX_THERMAL)
  195. puts("CPU: ");
  196. switch (get_cpu_temp_grade(&minc, &maxc)) {
  197. case TEMP_AUTOMOTIVE:
  198. puts("Automotive temperature grade ");
  199. break;
  200. case TEMP_INDUSTRIAL:
  201. puts("Industrial temperature grade ");
  202. break;
  203. case TEMP_EXTCOMMERCIAL:
  204. puts("Extended Commercial temperature grade ");
  205. break;
  206. default:
  207. puts("Commercial temperature grade ");
  208. break;
  209. }
  210. printf("(%dC to %dC)", minc, maxc);
  211. ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
  212. if (!ret) {
  213. ret = thermal_get_temp(thermal_dev, &cpu_tmp);
  214. if (!ret)
  215. printf(" at %dC\n", cpu_tmp);
  216. else
  217. debug(" - invalid sensor data\n");
  218. } else {
  219. debug(" - invalid sensor device\n");
  220. }
  221. #endif
  222. printf("Reset cause: %s\n", get_reset_cause());
  223. return 0;
  224. }
  225. #endif
  226. int cpu_eth_init(bd_t *bis)
  227. {
  228. int rc = -ENODEV;
  229. #if defined(CONFIG_FEC_MXC)
  230. rc = fecmxc_initialize(bis);
  231. #endif
  232. return rc;
  233. }
  234. #ifdef CONFIG_FSL_ESDHC_IMX
  235. /*
  236. * Initializes on-chip MMC controllers.
  237. * to override, implement board_mmc_init()
  238. */
  239. int cpu_mmc_init(bd_t *bis)
  240. {
  241. return fsl_esdhc_mmc_init(bis);
  242. }
  243. #endif
  244. #if !(defined(CONFIG_MX7) || defined(CONFIG_IMX8M))
  245. u32 get_ahb_clk(void)
  246. {
  247. struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  248. u32 reg, ahb_podf;
  249. reg = __raw_readl(&imx_ccm->cbcdr);
  250. reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
  251. ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
  252. return get_periph_clk() / (ahb_podf + 1);
  253. }
  254. #endif
  255. void arch_preboot_os(void)
  256. {
  257. #if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
  258. imx_pcie_remove();
  259. #endif
  260. #if defined(CONFIG_SATA)
  261. sata_remove(0);
  262. #if defined(CONFIG_MX6)
  263. disable_sata_clock();
  264. #endif
  265. #endif
  266. #if defined(CONFIG_VIDEO_IPUV3)
  267. /* disable video before launching O/S */
  268. ipuv3_fb_shutdown();
  269. #endif
  270. #if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO)
  271. lcdif_power_down();
  272. #endif
  273. }
  274. #ifndef CONFIG_IMX8M
  275. void set_chipselect_size(int const cs_size)
  276. {
  277. unsigned int reg;
  278. struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
  279. reg = readl(&iomuxc_regs->gpr[1]);
  280. switch (cs_size) {
  281. case CS0_128:
  282. reg &= ~0x7; /* CS0=128MB, CS1=0, CS2=0, CS3=0 */
  283. reg |= 0x5;
  284. break;
  285. case CS0_64M_CS1_64M:
  286. reg &= ~0x3F; /* CS0=64MB, CS1=64MB, CS2=0, CS3=0 */
  287. reg |= 0x1B;
  288. break;
  289. case CS0_64M_CS1_32M_CS2_32M:
  290. reg &= ~0x1FF; /* CS0=64MB, CS1=32MB, CS2=32MB, CS3=0 */
  291. reg |= 0x4B;
  292. break;
  293. case CS0_32M_CS1_32M_CS2_32M_CS3_32M:
  294. reg &= ~0xFFF; /* CS0=32MB, CS1=32MB, CS2=32MB, CS3=32MB */
  295. reg |= 0x249;
  296. break;
  297. default:
  298. printf("Unknown chip select size: %d\n", cs_size);
  299. break;
  300. }
  301. writel(reg, &iomuxc_regs->gpr[1]);
  302. }
  303. #endif
  304. #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
  305. /*
  306. * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  307. * defines a 2-bit SPEED_GRADING
  308. */
  309. #define OCOTP_TESTER3_SPEED_SHIFT 8
  310. enum cpu_speed {
  311. OCOTP_TESTER3_SPEED_GRADE0,
  312. OCOTP_TESTER3_SPEED_GRADE1,
  313. OCOTP_TESTER3_SPEED_GRADE2,
  314. OCOTP_TESTER3_SPEED_GRADE3,
  315. };
  316. u32 get_cpu_speed_grade_hz(void)
  317. {
  318. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  319. struct fuse_bank *bank = &ocotp->bank[1];
  320. struct fuse_bank1_regs *fuse =
  321. (struct fuse_bank1_regs *)bank->fuse_regs;
  322. uint32_t val;
  323. val = readl(&fuse->tester3);
  324. val >>= OCOTP_TESTER3_SPEED_SHIFT;
  325. val &= 0x3;
  326. switch(val) {
  327. case OCOTP_TESTER3_SPEED_GRADE0:
  328. return 800000000;
  329. case OCOTP_TESTER3_SPEED_GRADE1:
  330. return is_mx7() ? 500000000 : 1000000000;
  331. case OCOTP_TESTER3_SPEED_GRADE2:
  332. return is_mx7() ? 1000000000 : 1300000000;
  333. case OCOTP_TESTER3_SPEED_GRADE3:
  334. return is_mx7() ? 1200000000 : 1500000000;
  335. }
  336. return 0;
  337. }
  338. /*
  339. * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
  340. * defines a 2-bit SPEED_GRADING
  341. */
  342. #define OCOTP_TESTER3_TEMP_SHIFT 6
  343. u32 get_cpu_temp_grade(int *minc, int *maxc)
  344. {
  345. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  346. struct fuse_bank *bank = &ocotp->bank[1];
  347. struct fuse_bank1_regs *fuse =
  348. (struct fuse_bank1_regs *)bank->fuse_regs;
  349. uint32_t val;
  350. val = readl(&fuse->tester3);
  351. val >>= OCOTP_TESTER3_TEMP_SHIFT;
  352. val &= 0x3;
  353. if (minc && maxc) {
  354. if (val == TEMP_AUTOMOTIVE) {
  355. *minc = -40;
  356. *maxc = 125;
  357. } else if (val == TEMP_INDUSTRIAL) {
  358. *minc = -40;
  359. *maxc = 105;
  360. } else if (val == TEMP_EXTCOMMERCIAL) {
  361. *minc = -20;
  362. *maxc = 105;
  363. } else {
  364. *minc = 0;
  365. *maxc = 95;
  366. }
  367. }
  368. return val;
  369. }
  370. #endif
  371. #if defined(CONFIG_MX7) || defined(CONFIG_IMX8M)
  372. enum boot_device get_boot_device(void)
  373. {
  374. struct bootrom_sw_info **p =
  375. (struct bootrom_sw_info **)(ulong)ROM_SW_INFO_ADDR;
  376. enum boot_device boot_dev = SD1_BOOT;
  377. u8 boot_type = (*p)->boot_dev_type;
  378. u8 boot_instance = (*p)->boot_dev_instance;
  379. switch (boot_type) {
  380. case BOOT_TYPE_SD:
  381. boot_dev = boot_instance + SD1_BOOT;
  382. break;
  383. case BOOT_TYPE_MMC:
  384. boot_dev = boot_instance + MMC1_BOOT;
  385. break;
  386. case BOOT_TYPE_NAND:
  387. boot_dev = NAND_BOOT;
  388. break;
  389. case BOOT_TYPE_QSPI:
  390. boot_dev = QSPI_BOOT;
  391. break;
  392. case BOOT_TYPE_WEIM:
  393. boot_dev = WEIM_NOR_BOOT;
  394. break;
  395. case BOOT_TYPE_SPINOR:
  396. boot_dev = SPI_NOR_BOOT;
  397. break;
  398. #ifdef CONFIG_IMX8M
  399. case BOOT_TYPE_USB:
  400. boot_dev = USB_BOOT;
  401. break;
  402. #endif
  403. default:
  404. break;
  405. }
  406. return boot_dev;
  407. }
  408. #endif
  409. #ifdef CONFIG_NXP_BOARD_REVISION
  410. int nxp_board_rev(void)
  411. {
  412. /*
  413. * Get Board ID information from OCOTP_GP1[15:8]
  414. * RevA: 0x1
  415. * RevB: 0x2
  416. * RevC: 0x3
  417. */
  418. struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  419. struct fuse_bank *bank = &ocotp->bank[4];
  420. struct fuse_bank4_regs *fuse =
  421. (struct fuse_bank4_regs *)bank->fuse_regs;
  422. return (readl(&fuse->gp1) >> 8 & 0x0F);
  423. }
  424. char nxp_board_rev_string(void)
  425. {
  426. const char *rev = "A";
  427. return (*rev + nxp_board_rev() - 1);
  428. }
  429. #endif