generic.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013-2016, Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/io.h>
  7. #include <asm/arch/imx-regs.h>
  8. #include <asm/arch/clock.h>
  9. #include <asm/arch/mc_cgm_regs.h>
  10. #include <asm/arch/mc_me_regs.h>
  11. #include <asm/arch/mc_rgm_regs.h>
  12. #include <netdev.h>
  13. #include <div64.h>
  14. #include <errno.h>
  15. u32 get_cpu_rev(void)
  16. {
  17. struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_BASE_ADDR;
  18. u32 cpu = readl(&mscmir->cpxtype);
  19. return cpu;
  20. }
  21. DECLARE_GLOBAL_DATA_PTR;
  22. static uintptr_t get_pllfreq(u32 pll, u32 refclk_freq, u32 plldv,
  23. u32 pllfd, u32 selected_output)
  24. {
  25. u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0;
  26. u32 plldv_rfdphi_div = 0, fout = 0;
  27. u32 dfs_portn = 0, dfs_mfn = 0, dfs_mfi = 0;
  28. if (selected_output > DFS_MAXNUMBER) {
  29. return -1;
  30. }
  31. plldv_prediv =
  32. (plldv & PLLDIG_PLLDV_PREDIV_MASK) >> PLLDIG_PLLDV_PREDIV_OFFSET;
  33. plldv_mfd = (plldv & PLLDIG_PLLDV_MFD_MASK);
  34. pllfd_mfn = (pllfd & PLLDIG_PLLFD_MFN_MASK);
  35. plldv_prediv = plldv_prediv == 0 ? 1 : plldv_prediv;
  36. /* The formula for VCO is from TR manual, rev. D */
  37. vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481);
  38. if (selected_output != 0) {
  39. /* Determine the RFDPHI for PHI1 */
  40. plldv_rfdphi_div =
  41. (plldv & PLLDIG_PLLDV_RFDPHI1_MASK) >>
  42. PLLDIG_PLLDV_RFDPHI1_OFFSET;
  43. plldv_rfdphi_div = plldv_rfdphi_div == 0 ? 1 : plldv_rfdphi_div;
  44. if (pll == ARM_PLL || pll == ENET_PLL || pll == DDR_PLL) {
  45. dfs_portn =
  46. readl(DFS_DVPORTn(pll, selected_output - 1));
  47. dfs_mfi =
  48. (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
  49. DFS_DVPORTn_MFI_OFFSET;
  50. dfs_mfn =
  51. (dfs_portn & DFS_DVPORTn_MFI_MASK) >>
  52. DFS_DVPORTn_MFI_OFFSET;
  53. fout = vco / (dfs_mfi + (dfs_mfn / 256));
  54. } else {
  55. fout = vco / plldv_rfdphi_div;
  56. }
  57. } else {
  58. /* Determine the RFDPHI for PHI0 */
  59. plldv_rfdphi_div =
  60. (plldv & PLLDIG_PLLDV_RFDPHI_MASK) >>
  61. PLLDIG_PLLDV_RFDPHI_OFFSET;
  62. fout = vco / plldv_rfdphi_div;
  63. }
  64. return fout;
  65. }
  66. /* Implemented for ARMPLL, PERIPH_PLL, ENET_PLL, DDR_PLL, VIDEO_LL */
  67. static uintptr_t decode_pll(enum pll_type pll, u32 refclk_freq,
  68. u32 selected_output)
  69. {
  70. u32 plldv, pllfd;
  71. plldv = readl(PLLDIG_PLLDV(pll));
  72. pllfd = readl(PLLDIG_PLLFD(pll));
  73. return get_pllfreq(pll, refclk_freq, plldv, pllfd, selected_output);
  74. }
  75. static u32 get_mcu_main_clk(void)
  76. {
  77. u32 coreclk_div;
  78. u32 sysclk_sel;
  79. u32 freq = 0;
  80. sysclk_sel = readl(CGM_SC_SS(MC_CGM1_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
  81. sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
  82. coreclk_div =
  83. readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, 0)) & MC_CGM_SC_DCn_PREDIV_MASK;
  84. coreclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
  85. coreclk_div += 1;
  86. switch (sysclk_sel) {
  87. case MC_CGM_SC_SEL_FIRC:
  88. freq = FIRC_CLK_FREQ;
  89. break;
  90. case MC_CGM_SC_SEL_XOSC:
  91. freq = XOSC_CLK_FREQ;
  92. break;
  93. case MC_CGM_SC_SEL_ARMPLL:
  94. /* ARMPLL has as source XOSC and CORE_CLK has as input PHI0 */
  95. freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 0);
  96. break;
  97. case MC_CGM_SC_SEL_CLKDISABLE:
  98. printf("Sysclk is disabled\n");
  99. break;
  100. default:
  101. printf("unsupported system clock select\n");
  102. }
  103. return freq / coreclk_div;
  104. }
  105. static u32 get_sys_clk(u32 number)
  106. {
  107. u32 sysclk_div, sysclk_div_number;
  108. u32 sysclk_sel;
  109. u32 freq = 0;
  110. switch (number) {
  111. case 3:
  112. sysclk_div_number = 0;
  113. break;
  114. case 6:
  115. sysclk_div_number = 1;
  116. break;
  117. default:
  118. printf("unsupported system clock \n");
  119. return -1;
  120. }
  121. sysclk_sel = readl(CGM_SC_SS(MC_CGM0_BASE_ADDR)) & MC_CGM_SC_SEL_MASK;
  122. sysclk_sel >>= MC_CGM_SC_SEL_OFFSET;
  123. sysclk_div =
  124. readl(CGM_SC_DCn(MC_CGM1_BASE_ADDR, sysclk_div_number)) &
  125. MC_CGM_SC_DCn_PREDIV_MASK;
  126. sysclk_div >>= MC_CGM_SC_DCn_PREDIV_OFFSET;
  127. sysclk_div += 1;
  128. switch (sysclk_sel) {
  129. case MC_CGM_SC_SEL_FIRC:
  130. freq = FIRC_CLK_FREQ;
  131. break;
  132. case MC_CGM_SC_SEL_XOSC:
  133. freq = XOSC_CLK_FREQ;
  134. break;
  135. case MC_CGM_SC_SEL_ARMPLL:
  136. /* ARMPLL has as source XOSC and SYSn_CLK has as input DFS1 */
  137. freq = decode_pll(ARM_PLL, XOSC_CLK_FREQ, 1);
  138. break;
  139. case MC_CGM_SC_SEL_CLKDISABLE:
  140. printf("Sysclk is disabled\n");
  141. break;
  142. default:
  143. printf("unsupported system clock select\n");
  144. }
  145. return freq / sysclk_div;
  146. }
  147. static u32 get_peripherals_clk(void)
  148. {
  149. u32 aux5clk_div;
  150. u32 freq = 0;
  151. aux5clk_div =
  152. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 5, 0)) &
  153. MC_CGM_ACn_DCm_PREDIV_MASK;
  154. aux5clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  155. aux5clk_div += 1;
  156. freq = decode_pll(PERIPH_PLL, XOSC_CLK_FREQ, 0);
  157. return freq / aux5clk_div;
  158. }
  159. static u32 get_uart_clk(void)
  160. {
  161. u32 auxclk3_div, auxclk3_sel, freq = 0;
  162. auxclk3_sel =
  163. readl(CGM_ACn_SS(MC_CGM0_BASE_ADDR, 3)) & MC_CGM_ACn_SEL_MASK;
  164. auxclk3_sel >>= MC_CGM_ACn_SEL_OFFSET;
  165. auxclk3_div =
  166. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 3, 0)) &
  167. MC_CGM_ACn_DCm_PREDIV_MASK;
  168. auxclk3_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  169. auxclk3_div += 1;
  170. switch (auxclk3_sel) {
  171. case MC_CGM_ACn_SEL_FIRC:
  172. freq = FIRC_CLK_FREQ;
  173. break;
  174. case MC_CGM_ACn_SEL_XOSC:
  175. freq = XOSC_CLK_FREQ;
  176. break;
  177. case MC_CGM_ACn_SEL_PERPLLDIVX:
  178. freq = get_peripherals_clk() / 3;
  179. break;
  180. case MC_CGM_ACn_SEL_SYSCLK:
  181. freq = get_sys_clk(6);
  182. break;
  183. default:
  184. printf("unsupported system clock select\n");
  185. }
  186. return freq / auxclk3_div;
  187. }
  188. static u32 get_fec_clk(void)
  189. {
  190. u32 aux2clk_div;
  191. u32 freq = 0;
  192. aux2clk_div =
  193. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 2, 0)) &
  194. MC_CGM_ACn_DCm_PREDIV_MASK;
  195. aux2clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  196. aux2clk_div += 1;
  197. freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 0);
  198. return freq / aux2clk_div;
  199. }
  200. static u32 get_usdhc_clk(void)
  201. {
  202. u32 aux15clk_div;
  203. u32 freq = 0;
  204. aux15clk_div =
  205. readl(CGM_ACn_DCm(MC_CGM0_BASE_ADDR, 15, 0)) &
  206. MC_CGM_ACn_DCm_PREDIV_MASK;
  207. aux15clk_div >>= MC_CGM_ACn_DCm_PREDIV_OFFSET;
  208. aux15clk_div += 1;
  209. freq = decode_pll(ENET_PLL, XOSC_CLK_FREQ, 4);
  210. return freq / aux15clk_div;
  211. }
  212. static u32 get_i2c_clk(void)
  213. {
  214. return get_peripherals_clk();
  215. }
  216. /* return clocks in Hz */
  217. unsigned int mxc_get_clock(enum mxc_clock clk)
  218. {
  219. switch (clk) {
  220. case MXC_ARM_CLK:
  221. return get_mcu_main_clk();
  222. case MXC_PERIPHERALS_CLK:
  223. return get_peripherals_clk();
  224. case MXC_UART_CLK:
  225. return get_uart_clk();
  226. case MXC_FEC_CLK:
  227. return get_fec_clk();
  228. case MXC_I2C_CLK:
  229. return get_i2c_clk();
  230. case MXC_USDHC_CLK:
  231. return get_usdhc_clk();
  232. default:
  233. break;
  234. }
  235. printf("Error: Unsupported function to read the frequency! \
  236. Please define it correctly!");
  237. return -1;
  238. }
  239. /* Not yet implemented - int soc_clk_dump(); */
  240. #if defined(CONFIG_DISPLAY_CPUINFO)
  241. static char *get_reset_cause(void)
  242. {
  243. u32 cause = readl(MC_RGM_BASE_ADDR + 0x300);
  244. switch (cause) {
  245. case F_SWT4:
  246. return "WDOG";
  247. case F_JTAG:
  248. return "JTAG";
  249. case F_FCCU_SOFT:
  250. return "FCCU soft reaction";
  251. case F_FCCU_HARD:
  252. return "FCCU hard reaction";
  253. case F_SOFT_FUNC:
  254. return "Software Functional reset";
  255. case F_ST_DONE:
  256. return "Self Test done reset";
  257. case F_EXT_RST:
  258. return "External reset";
  259. default:
  260. return "unknown reset";
  261. }
  262. }
  263. #define SRC_SCR_SW_RST (1<<12)
  264. void reset_cpu(ulong addr)
  265. {
  266. printf("Feature not supported.\n");
  267. };
  268. int print_cpuinfo(void)
  269. {
  270. printf("CPU: Freescale Treerunner S32V234 at %d MHz\n",
  271. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  272. printf("Reset cause: %s\n", get_reset_cause());
  273. return 0;
  274. }
  275. #endif
  276. int cpu_eth_init(bd_t * bis)
  277. {
  278. int rc = -ENODEV;
  279. #if defined(CONFIG_FEC_MXC)
  280. rc = fecmxc_initialize(bis);
  281. #endif
  282. return rc;
  283. }
  284. int get_clocks(void)
  285. {
  286. #ifdef CONFIG_FSL_ESDHC_IMX
  287. gd->arch.sdhc_clk = mxc_get_clock(MXC_USDHC_CLK);
  288. #endif
  289. return 0;
  290. }