generic.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 DENX Software Engineering
  4. * Author: John Rigby <jrigby@gmail.com>
  5. *
  6. * Based on mx27/generic.c:
  7. * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
  8. * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
  9. */
  10. #include <common.h>
  11. #include <div64.h>
  12. #include <netdev.h>
  13. #include <asm/io.h>
  14. #include <asm/arch-imx/cpu.h>
  15. #include <asm/arch/imx-regs.h>
  16. #include <asm/arch/clock.h>
  17. #ifdef CONFIG_FSL_ESDHC_IMX
  18. #include <fsl_esdhc_imx.h>
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #endif
  21. /*
  22. * get the system pll clock in Hz
  23. *
  24. * mfi + mfn / (mfd +1)
  25. * f = 2 * f_ref * --------------------
  26. * pd + 1
  27. */
  28. static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
  29. {
  30. unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
  31. & CCM_PLL_MFI_MASK;
  32. int mfn = (pll >> CCM_PLL_MFN_SHIFT)
  33. & CCM_PLL_MFN_MASK;
  34. unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
  35. & CCM_PLL_MFD_MASK;
  36. unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
  37. & CCM_PLL_PD_MASK;
  38. mfi = mfi <= 5 ? 5 : mfi;
  39. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  40. mfd += 1;
  41. pd += 1;
  42. return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
  43. mfd * pd);
  44. }
  45. static ulong imx_get_mpllclk(void)
  46. {
  47. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  48. ulong fref = MXC_HCLK;
  49. return imx_decode_pll(readl(&ccm->mpctl), fref);
  50. }
  51. static ulong imx_get_upllclk(void)
  52. {
  53. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  54. ulong fref = MXC_HCLK;
  55. return imx_decode_pll(readl(&ccm->upctl), fref);
  56. }
  57. static ulong imx_get_armclk(void)
  58. {
  59. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  60. ulong cctl = readl(&ccm->cctl);
  61. ulong fref = imx_get_mpllclk();
  62. ulong div;
  63. if (cctl & CCM_CCTL_ARM_SRC)
  64. fref = lldiv((u64) fref * 3, 4);
  65. div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
  66. & CCM_CCTL_ARM_DIV_MASK) + 1;
  67. return fref / div;
  68. }
  69. static ulong imx_get_ahbclk(void)
  70. {
  71. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  72. ulong cctl = readl(&ccm->cctl);
  73. ulong fref = imx_get_armclk();
  74. ulong div;
  75. div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
  76. & CCM_CCTL_AHB_DIV_MASK) + 1;
  77. return fref / div;
  78. }
  79. static ulong imx_get_ipgclk(void)
  80. {
  81. return imx_get_ahbclk() / 2;
  82. }
  83. static ulong imx_get_perclk(int clk)
  84. {
  85. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  86. ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
  87. imx_get_ahbclk();
  88. ulong div;
  89. div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
  90. div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
  91. return fref / div;
  92. }
  93. int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
  94. {
  95. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  96. ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
  97. ulong div = (fref + freq - 1) / freq;
  98. if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
  99. return -EINVAL;
  100. clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
  101. CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
  102. div << CCM_PERCLK_SHIFT(clk));
  103. if (from_upll)
  104. setbits_le32(&ccm->mcr, 1 << clk);
  105. else
  106. clrbits_le32(&ccm->mcr, 1 << clk);
  107. return 0;
  108. }
  109. unsigned int mxc_get_clock(enum mxc_clock clk)
  110. {
  111. if (clk >= MXC_CLK_NUM)
  112. return -1;
  113. switch (clk) {
  114. case MXC_ARM_CLK:
  115. return imx_get_armclk();
  116. case MXC_AHB_CLK:
  117. return imx_get_ahbclk();
  118. case MXC_IPG_CLK:
  119. case MXC_CSPI_CLK:
  120. case MXC_FEC_CLK:
  121. return imx_get_ipgclk();
  122. default:
  123. return imx_get_perclk(clk);
  124. }
  125. }
  126. u32 get_cpu_rev(void)
  127. {
  128. u32 srev;
  129. u32 system_rev = 0x25000;
  130. /* read SREV register from IIM module */
  131. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  132. srev = readl(&iim->iim_srev);
  133. switch (srev) {
  134. case 0x00:
  135. system_rev |= CHIP_REV_1_0;
  136. break;
  137. case 0x01:
  138. system_rev |= CHIP_REV_1_1;
  139. break;
  140. case 0x02:
  141. system_rev |= CHIP_REV_1_2;
  142. break;
  143. default:
  144. system_rev |= 0x8000;
  145. break;
  146. }
  147. return system_rev;
  148. }
  149. #if defined(CONFIG_DISPLAY_CPUINFO)
  150. static char *get_reset_cause(void)
  151. {
  152. /* read RCSR register from CCM module */
  153. struct ccm_regs *ccm =
  154. (struct ccm_regs *)IMX_CCM_BASE;
  155. u32 cause = readl(&ccm->rcsr) & 0x0f;
  156. if (cause == 0)
  157. return "POR";
  158. else if (cause == 1)
  159. return "RST";
  160. else if ((cause & 2) == 2)
  161. return "WDOG";
  162. else if ((cause & 4) == 4)
  163. return "SW RESET";
  164. else if ((cause & 8) == 8)
  165. return "JTAG";
  166. else
  167. return "unknown reset";
  168. }
  169. int print_cpuinfo(void)
  170. {
  171. char buf[32];
  172. u32 cpurev = get_cpu_rev();
  173. printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
  174. (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
  175. ((cpurev & 0x8000) ? " unknown" : ""),
  176. strmhz(buf, imx_get_armclk()));
  177. printf("Reset cause: %s\n", get_reset_cause());
  178. return 0;
  179. }
  180. #endif
  181. #if defined(CONFIG_FEC_MXC)
  182. /*
  183. * Initializes on-chip ethernet controllers.
  184. * to override, implement board_eth_init()
  185. */
  186. int cpu_eth_init(bd_t *bis)
  187. {
  188. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  189. ulong val;
  190. val = readl(&ccm->cgr0);
  191. val |= (1 << 23);
  192. writel(val, &ccm->cgr0);
  193. return fecmxc_initialize(bis);
  194. }
  195. #endif
  196. int get_clocks(void)
  197. {
  198. #ifdef CONFIG_FSL_ESDHC_IMX
  199. #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
  200. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  201. #else
  202. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  203. #endif
  204. #endif
  205. return 0;
  206. }
  207. #ifdef CONFIG_FSL_ESDHC_IMX
  208. /*
  209. * Initializes on-chip MMC controllers.
  210. * to override, implement board_mmc_init()
  211. */
  212. int cpu_mmc_init(bd_t *bis)
  213. {
  214. return fsl_esdhc_mmc_init(bis);
  215. }
  216. #endif
  217. #ifdef CONFIG_FEC_MXC
  218. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  219. {
  220. int i;
  221. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  222. struct fuse_bank *bank = &iim->bank[0];
  223. struct fuse_bank0_regs *fuse =
  224. (struct fuse_bank0_regs *)bank->fuse_regs;
  225. for (i = 0; i < 6; i++)
  226. mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
  227. }
  228. #endif /* CONFIG_FEC_MXC */