board.c 25 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  4. * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  5. *
  6. * (C) Copyright 2007-2011
  7. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  8. * Tom Cubie <tangliang@allwinnertech.com>
  9. *
  10. * Some board init for the Allwinner A10-evb board.
  11. */
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <env.h>
  15. #include <hang.h>
  16. #include <image.h>
  17. #include <init.h>
  18. #include <log.h>
  19. #include <mmc.h>
  20. #include <axp_pmic.h>
  21. #include <generic-phy.h>
  22. #include <phy-sun4i-usb.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/cpu.h>
  25. #include <asm/arch/display.h>
  26. #include <asm/arch/dram.h>
  27. #include <asm/arch/gpio.h>
  28. #include <asm/arch/mmc.h>
  29. #include <asm/arch/spl.h>
  30. #include <linux/delay.h>
  31. #include <u-boot/crc.h>
  32. #ifndef CONFIG_ARM64
  33. #include <asm/armv7.h>
  34. #endif
  35. #include <asm/gpio.h>
  36. #include <asm/io.h>
  37. #include <u-boot/crc.h>
  38. #include <env_internal.h>
  39. #include <linux/libfdt.h>
  40. #include <nand.h>
  41. #include <net.h>
  42. #include <spl.h>
  43. #include <sy8106a.h>
  44. #include <asm/setup.h>
  45. #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
  46. /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
  47. int soft_i2c_gpio_sda;
  48. int soft_i2c_gpio_scl;
  49. static int soft_i2c_board_init(void)
  50. {
  51. int ret;
  52. soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
  53. if (soft_i2c_gpio_sda < 0) {
  54. printf("Error invalid soft i2c sda pin: '%s', err %d\n",
  55. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
  56. return soft_i2c_gpio_sda;
  57. }
  58. ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
  59. if (ret) {
  60. printf("Error requesting soft i2c sda pin: '%s', err %d\n",
  61. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
  62. return ret;
  63. }
  64. soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
  65. if (soft_i2c_gpio_scl < 0) {
  66. printf("Error invalid soft i2c scl pin: '%s', err %d\n",
  67. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
  68. return soft_i2c_gpio_scl;
  69. }
  70. ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
  71. if (ret) {
  72. printf("Error requesting soft i2c scl pin: '%s', err %d\n",
  73. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
  74. return ret;
  75. }
  76. return 0;
  77. }
  78. #else
  79. static int soft_i2c_board_init(void) { return 0; }
  80. #endif
  81. DECLARE_GLOBAL_DATA_PTR;
  82. void i2c_init_board(void)
  83. {
  84. #ifdef CONFIG_I2C0_ENABLE
  85. #if defined(CONFIG_MACH_SUN4I) || \
  86. defined(CONFIG_MACH_SUN5I) || \
  87. defined(CONFIG_MACH_SUN7I) || \
  88. defined(CONFIG_MACH_SUN8I_R40)
  89. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
  90. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
  91. clock_twi_onoff(0, 1);
  92. #elif defined(CONFIG_MACH_SUN6I)
  93. sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
  94. sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
  95. clock_twi_onoff(0, 1);
  96. #elif defined(CONFIG_MACH_SUN8I_V3S)
  97. sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_GPH_TWI0);
  98. sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_GPH_TWI0);
  99. clock_twi_onoff(0, 1);
  100. #elif defined(CONFIG_MACH_SUN8I)
  101. sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
  102. sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
  103. clock_twi_onoff(0, 1);
  104. #elif defined(CONFIG_MACH_SUN50I)
  105. sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
  106. sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
  107. clock_twi_onoff(0, 1);
  108. #endif
  109. #endif
  110. #ifdef CONFIG_I2C1_ENABLE
  111. #if defined(CONFIG_MACH_SUN4I) || \
  112. defined(CONFIG_MACH_SUN7I) || \
  113. defined(CONFIG_MACH_SUN8I_R40)
  114. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
  115. sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
  116. clock_twi_onoff(1, 1);
  117. #elif defined(CONFIG_MACH_SUN5I)
  118. sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
  119. sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
  120. clock_twi_onoff(1, 1);
  121. #elif defined(CONFIG_MACH_SUN6I)
  122. sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
  123. sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
  124. clock_twi_onoff(1, 1);
  125. #elif defined(CONFIG_MACH_SUN8I)
  126. sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
  127. sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
  128. clock_twi_onoff(1, 1);
  129. #elif defined(CONFIG_MACH_SUN50I)
  130. sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
  131. sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
  132. clock_twi_onoff(1, 1);
  133. #endif
  134. #endif
  135. #ifdef CONFIG_I2C2_ENABLE
  136. #if defined(CONFIG_MACH_SUN4I) || \
  137. defined(CONFIG_MACH_SUN7I) || \
  138. defined(CONFIG_MACH_SUN8I_R40)
  139. sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
  140. sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
  141. clock_twi_onoff(2, 1);
  142. #elif defined(CONFIG_MACH_SUN5I)
  143. sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
  144. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
  145. clock_twi_onoff(2, 1);
  146. #elif defined(CONFIG_MACH_SUN6I)
  147. sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
  148. sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
  149. clock_twi_onoff(2, 1);
  150. #elif defined(CONFIG_MACH_SUN8I)
  151. sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
  152. sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
  153. clock_twi_onoff(2, 1);
  154. #elif defined(CONFIG_MACH_SUN50I)
  155. sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
  156. sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
  157. clock_twi_onoff(2, 1);
  158. #endif
  159. #endif
  160. #ifdef CONFIG_I2C3_ENABLE
  161. #if defined(CONFIG_MACH_SUN6I)
  162. sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
  163. sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
  164. clock_twi_onoff(3, 1);
  165. #elif defined(CONFIG_MACH_SUN7I) || \
  166. defined(CONFIG_MACH_SUN8I_R40)
  167. sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
  168. sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
  169. clock_twi_onoff(3, 1);
  170. #endif
  171. #endif
  172. #ifdef CONFIG_I2C4_ENABLE
  173. #if defined(CONFIG_MACH_SUN7I) || \
  174. defined(CONFIG_MACH_SUN8I_R40)
  175. sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
  176. sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
  177. clock_twi_onoff(4, 1);
  178. #endif
  179. #endif
  180. #ifdef CONFIG_R_I2C_ENABLE
  181. #ifdef CONFIG_MACH_SUN50I
  182. clock_twi_onoff(5, 1);
  183. sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
  184. sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
  185. #else
  186. clock_twi_onoff(5, 1);
  187. sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
  188. sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
  189. #endif
  190. #endif
  191. }
  192. #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
  193. enum env_location env_get_location(enum env_operation op, int prio)
  194. {
  195. switch (prio) {
  196. case 0:
  197. return ENVL_FAT;
  198. case 1:
  199. return ENVL_MMC;
  200. default:
  201. return ENVL_UNKNOWN;
  202. }
  203. }
  204. #endif
  205. #ifdef CONFIG_DM_MMC
  206. static void mmc_pinmux_setup(int sdc);
  207. #endif
  208. /* add board specific code here */
  209. int board_init(void)
  210. {
  211. __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
  212. gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
  213. #ifndef CONFIG_ARM64
  214. asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
  215. debug("id_pfr1: 0x%08x\n", id_pfr1);
  216. /* Generic Timer Extension available? */
  217. if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
  218. uint32_t freq;
  219. debug("Setting CNTFRQ\n");
  220. /*
  221. * CNTFRQ is a secure register, so we will crash if we try to
  222. * write this from the non-secure world (read is OK, though).
  223. * In case some bootcode has already set the correct value,
  224. * we avoid the risk of writing to it.
  225. */
  226. asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
  227. if (freq != COUNTER_FREQUENCY) {
  228. debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
  229. freq, COUNTER_FREQUENCY);
  230. #ifdef CONFIG_NON_SECURE
  231. printf("arch timer frequency is wrong, but cannot adjust it\n");
  232. #else
  233. asm volatile("mcr p15, 0, %0, c14, c0, 0"
  234. : : "r"(COUNTER_FREQUENCY));
  235. #endif
  236. }
  237. }
  238. #endif /* !CONFIG_ARM64 */
  239. ret = axp_gpio_init();
  240. if (ret)
  241. return ret;
  242. #ifdef CONFIG_SATAPWR
  243. satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
  244. gpio_request(satapwr_pin, "satapwr");
  245. gpio_direction_output(satapwr_pin, 1);
  246. /* Give attached sata device time to power-up to avoid link timeouts */
  247. mdelay(500);
  248. #endif
  249. #ifdef CONFIG_MACPWR
  250. macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
  251. gpio_request(macpwr_pin, "macpwr");
  252. gpio_direction_output(macpwr_pin, 1);
  253. #endif
  254. #ifdef CONFIG_DM_I2C
  255. /*
  256. * Temporary workaround for enabling I2C clocks until proper sunxi DM
  257. * clk, reset and pinctrl drivers land.
  258. */
  259. i2c_init_board();
  260. #endif
  261. #ifdef CONFIG_DM_MMC
  262. /*
  263. * Temporary workaround for enabling MMC clocks until a sunxi DM
  264. * pinctrl driver lands.
  265. */
  266. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
  267. #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
  268. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  269. #endif
  270. #endif /* CONFIG_DM_MMC */
  271. /* Uses dm gpio code so do this here and not in i2c_init_board() */
  272. return soft_i2c_board_init();
  273. }
  274. /*
  275. * On older SoCs the SPL is actually at address zero, so using NULL as
  276. * an error value does not work.
  277. */
  278. #define INVALID_SPL_HEADER ((void *)~0UL)
  279. static struct boot_file_head * get_spl_header(uint8_t req_version)
  280. {
  281. struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
  282. uint8_t spl_header_version = spl->spl_signature[3];
  283. /* Is there really the SPL header (still) there? */
  284. if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
  285. return INVALID_SPL_HEADER;
  286. if (spl_header_version < req_version) {
  287. printf("sunxi SPL version mismatch: expected %u, got %u\n",
  288. req_version, spl_header_version);
  289. return INVALID_SPL_HEADER;
  290. }
  291. return spl;
  292. }
  293. int dram_init(void)
  294. {
  295. struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
  296. if (spl == INVALID_SPL_HEADER)
  297. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
  298. PHYS_SDRAM_0_SIZE);
  299. else
  300. gd->ram_size = (phys_addr_t)spl->dram_size << 20;
  301. if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
  302. gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
  303. return 0;
  304. }
  305. #if defined(CONFIG_NAND_SUNXI)
  306. static void nand_pinmux_setup(void)
  307. {
  308. unsigned int pin;
  309. for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
  310. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  311. #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
  312. for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
  313. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  314. #endif
  315. /* sun4i / sun7i do have a PC23, but it is not used for nand,
  316. * only sun7i has a PC24 */
  317. #ifdef CONFIG_MACH_SUN7I
  318. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
  319. #endif
  320. }
  321. static void nand_clock_setup(void)
  322. {
  323. struct sunxi_ccm_reg *const ccm =
  324. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  325. setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
  326. #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
  327. defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
  328. setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
  329. #endif
  330. setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
  331. }
  332. void board_nand_init(void)
  333. {
  334. nand_pinmux_setup();
  335. nand_clock_setup();
  336. #ifndef CONFIG_SPL_BUILD
  337. sunxi_nand_init();
  338. #endif
  339. }
  340. #endif
  341. #ifdef CONFIG_MMC
  342. static void mmc_pinmux_setup(int sdc)
  343. {
  344. unsigned int pin;
  345. __maybe_unused int pins;
  346. switch (sdc) {
  347. case 0:
  348. /* SDC0: PF0-PF5 */
  349. for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
  350. sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
  351. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  352. sunxi_gpio_set_drv(pin, 2);
  353. }
  354. break;
  355. case 1:
  356. pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
  357. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  358. defined(CONFIG_MACH_SUN8I_R40)
  359. if (pins == SUNXI_GPIO_H) {
  360. /* SDC1: PH22-PH-27 */
  361. for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
  362. sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
  363. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  364. sunxi_gpio_set_drv(pin, 2);
  365. }
  366. } else {
  367. /* SDC1: PG0-PG5 */
  368. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  369. sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
  370. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  371. sunxi_gpio_set_drv(pin, 2);
  372. }
  373. }
  374. #elif defined(CONFIG_MACH_SUN5I)
  375. /* SDC1: PG3-PG8 */
  376. for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
  377. sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
  378. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  379. sunxi_gpio_set_drv(pin, 2);
  380. }
  381. #elif defined(CONFIG_MACH_SUN6I)
  382. /* SDC1: PG0-PG5 */
  383. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  384. sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
  385. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  386. sunxi_gpio_set_drv(pin, 2);
  387. }
  388. #elif defined(CONFIG_MACH_SUN8I)
  389. if (pins == SUNXI_GPIO_D) {
  390. /* SDC1: PD2-PD7 */
  391. for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
  392. sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
  393. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  394. sunxi_gpio_set_drv(pin, 2);
  395. }
  396. } else {
  397. /* SDC1: PG0-PG5 */
  398. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  399. sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
  400. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  401. sunxi_gpio_set_drv(pin, 2);
  402. }
  403. }
  404. #endif
  405. break;
  406. case 2:
  407. pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
  408. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  409. /* SDC2: PC6-PC11 */
  410. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
  411. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  412. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  413. sunxi_gpio_set_drv(pin, 2);
  414. }
  415. #elif defined(CONFIG_MACH_SUN5I)
  416. if (pins == SUNXI_GPIO_E) {
  417. /* SDC2: PE4-PE9 */
  418. for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
  419. sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
  420. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  421. sunxi_gpio_set_drv(pin, 2);
  422. }
  423. } else {
  424. /* SDC2: PC6-PC15 */
  425. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  426. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  427. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  428. sunxi_gpio_set_drv(pin, 2);
  429. }
  430. }
  431. #elif defined(CONFIG_MACH_SUN6I)
  432. if (pins == SUNXI_GPIO_A) {
  433. /* SDC2: PA9-PA14 */
  434. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  435. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
  436. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  437. sunxi_gpio_set_drv(pin, 2);
  438. }
  439. } else {
  440. /* SDC2: PC6-PC15, PC24 */
  441. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  442. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  443. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  444. sunxi_gpio_set_drv(pin, 2);
  445. }
  446. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  447. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  448. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  449. }
  450. #elif defined(CONFIG_MACH_SUN8I_R40)
  451. /* SDC2: PC6-PC15, PC24 */
  452. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  453. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  454. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  455. sunxi_gpio_set_drv(pin, 2);
  456. }
  457. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  458. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  459. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  460. #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
  461. /* SDC2: PC5-PC6, PC8-PC16 */
  462. for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
  463. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  464. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  465. sunxi_gpio_set_drv(pin, 2);
  466. }
  467. for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
  468. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  469. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  470. sunxi_gpio_set_drv(pin, 2);
  471. }
  472. #elif defined(CONFIG_MACH_SUN50I_H6)
  473. /* SDC2: PC4-PC14 */
  474. for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
  475. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  476. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  477. sunxi_gpio_set_drv(pin, 2);
  478. }
  479. #elif defined(CONFIG_MACH_SUN9I)
  480. /* SDC2: PC6-PC16 */
  481. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
  482. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  483. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  484. sunxi_gpio_set_drv(pin, 2);
  485. }
  486. #endif
  487. break;
  488. case 3:
  489. pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
  490. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  491. defined(CONFIG_MACH_SUN8I_R40)
  492. /* SDC3: PI4-PI9 */
  493. for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
  494. sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
  495. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  496. sunxi_gpio_set_drv(pin, 2);
  497. }
  498. #elif defined(CONFIG_MACH_SUN6I)
  499. if (pins == SUNXI_GPIO_A) {
  500. /* SDC3: PA9-PA14 */
  501. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  502. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
  503. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  504. sunxi_gpio_set_drv(pin, 2);
  505. }
  506. } else {
  507. /* SDC3: PC6-PC15, PC24 */
  508. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  509. sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
  510. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  511. sunxi_gpio_set_drv(pin, 2);
  512. }
  513. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
  514. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  515. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  516. }
  517. #endif
  518. break;
  519. default:
  520. printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
  521. break;
  522. }
  523. }
  524. int board_mmc_init(struct bd_info *bis)
  525. {
  526. __maybe_unused struct mmc *mmc0, *mmc1;
  527. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
  528. mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
  529. if (!mmc0)
  530. return -1;
  531. #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
  532. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  533. mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  534. if (!mmc1)
  535. return -1;
  536. #endif
  537. return 0;
  538. }
  539. #endif
  540. #ifdef CONFIG_SPL_BUILD
  541. static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
  542. {
  543. struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
  544. if (spl == INVALID_SPL_HEADER)
  545. return;
  546. /* Promote the header version for U-Boot proper, if needed. */
  547. if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
  548. spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
  549. spl->dram_size = dram_size >> 20;
  550. }
  551. void sunxi_board_init(void)
  552. {
  553. int power_failed = 0;
  554. #ifdef CONFIG_SY8106A_POWER
  555. power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
  556. #endif
  557. #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
  558. defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  559. defined CONFIG_AXP818_POWER
  560. power_failed = axp_init();
  561. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  562. defined CONFIG_AXP818_POWER
  563. power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
  564. #endif
  565. power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
  566. power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
  567. #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
  568. power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
  569. #endif
  570. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  571. defined CONFIG_AXP818_POWER
  572. power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
  573. #endif
  574. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  575. defined CONFIG_AXP818_POWER
  576. power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
  577. #endif
  578. power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
  579. #if !defined(CONFIG_AXP152_POWER)
  580. power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
  581. #endif
  582. #ifdef CONFIG_AXP209_POWER
  583. power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
  584. #endif
  585. #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
  586. defined(CONFIG_AXP818_POWER)
  587. power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
  588. power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
  589. #if !defined CONFIG_AXP809_POWER
  590. power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
  591. power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
  592. #endif
  593. power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
  594. power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
  595. power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
  596. #endif
  597. #ifdef CONFIG_AXP818_POWER
  598. power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
  599. power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
  600. power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
  601. #endif
  602. #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
  603. power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
  604. #endif
  605. #endif
  606. //printf("DRAM:");
  607. gd->ram_size = sunxi_dram_init();
  608. //printf(" %d MiB\n", (int)(gd->ram_size >> 20));
  609. if (!gd->ram_size)
  610. hang();
  611. sunxi_spl_store_dram_size(gd->ram_size);
  612. /*
  613. * Only clock up the CPU to full speed if we are reasonably
  614. * assured it's being powered with suitable core voltage
  615. */
  616. if (!power_failed)
  617. clock_set_pll1(CONFIG_SYS_CLK_FREQ);
  618. else
  619. printf("Failed to set core voltage! Can't set CPU frequency\n");
  620. }
  621. #endif
  622. #ifdef CONFIG_USB_GADGET
  623. int g_dnl_board_usb_cable_connected(void)
  624. {
  625. struct udevice *dev;
  626. struct phy phy;
  627. int ret;
  628. ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
  629. if (ret) {
  630. pr_err("%s: Cannot find USB device\n", __func__);
  631. return ret;
  632. }
  633. ret = generic_phy_get_by_name(dev, "usb", &phy);
  634. if (ret) {
  635. pr_err("failed to get %s USB PHY\n", dev->name);
  636. return ret;
  637. }
  638. ret = generic_phy_init(&phy);
  639. if (ret) {
  640. pr_debug("failed to init %s USB PHY\n", dev->name);
  641. return ret;
  642. }
  643. ret = sun4i_usb_phy_vbus_detect(&phy);
  644. if (ret == 1) {
  645. pr_err("A charger is plugged into the OTG\n");
  646. return -ENODEV;
  647. }
  648. return ret;
  649. }
  650. #endif
  651. #ifdef CONFIG_SERIAL_TAG
  652. void get_board_serial(struct tag_serialnr *serialnr)
  653. {
  654. char *serial_string;
  655. unsigned long long serial;
  656. serial_string = env_get("serial#");
  657. if (serial_string) {
  658. serial = simple_strtoull(serial_string, NULL, 16);
  659. serialnr->high = (unsigned int) (serial >> 32);
  660. serialnr->low = (unsigned int) (serial & 0xffffffff);
  661. } else {
  662. serialnr->high = 0;
  663. serialnr->low = 0;
  664. }
  665. }
  666. #endif
  667. /*
  668. * Check the SPL header for the "sunxi" variant. If found: parse values
  669. * that might have been passed by the loader ("fel" utility), and update
  670. * the environment accordingly.
  671. */
  672. static void parse_spl_header(const uint32_t spl_addr)
  673. {
  674. struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
  675. if (spl == INVALID_SPL_HEADER)
  676. return;
  677. if (!spl->fel_script_address)
  678. return;
  679. if (spl->fel_uEnv_length != 0) {
  680. /*
  681. * data is expected in uEnv.txt compatible format, so "env
  682. * import -t" the string(s) at fel_script_address right away.
  683. */
  684. himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
  685. spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
  686. return;
  687. }
  688. /* otherwise assume .scr format (mkimage-type script) */
  689. env_set_hex("fel_scriptaddr", spl->fel_script_address);
  690. }
  691. /*
  692. * Note this function gets called multiple times.
  693. * It must not make any changes to env variables which already exist.
  694. */
  695. static void setup_environment(const void *fdt)
  696. {
  697. char serial_string[17] = { 0 };
  698. unsigned int sid[4];
  699. uint8_t mac_addr[6];
  700. char ethaddr[16];
  701. int i, ret;
  702. ret = sunxi_get_sid(sid);
  703. if (ret == 0 && sid[0] != 0) {
  704. /*
  705. * The single words 1 - 3 of the SID have quite a few bits
  706. * which are the same on many models, so we take a crc32
  707. * of all 3 words, to get a more unique value.
  708. *
  709. * Note we only do this on newer SoCs as we cannot change
  710. * the algorithm on older SoCs since those have been using
  711. * fixed mac-addresses based on only using word 3 for a
  712. * long time and changing a fixed mac-address with an
  713. * u-boot update is not good.
  714. */
  715. #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
  716. !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
  717. !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
  718. sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
  719. #endif
  720. /* Ensure the NIC specific bytes of the mac are not all 0 */
  721. if ((sid[3] & 0xffffff) == 0)
  722. sid[3] |= 0x800000;
  723. #if defined(CONFIG_CMD_NET)
  724. for (i = 0; i < 4; i++) {
  725. sprintf(ethaddr, "ethernet%d", i);
  726. if (!fdt_get_alias(fdt, ethaddr))
  727. continue;
  728. if (i == 0)
  729. strcpy(ethaddr, "ethaddr");
  730. else
  731. sprintf(ethaddr, "eth%daddr", i);
  732. if (env_get(ethaddr))
  733. continue;
  734. /* Non OUI / registered MAC address */
  735. mac_addr[0] = (i << 4) | 0x02;
  736. mac_addr[1] = (sid[0] >> 0) & 0xff;
  737. mac_addr[2] = (sid[3] >> 24) & 0xff;
  738. mac_addr[3] = (sid[3] >> 16) & 0xff;
  739. mac_addr[4] = (sid[3] >> 8) & 0xff;
  740. mac_addr[5] = (sid[3] >> 0) & 0xff;
  741. eth_env_set_enetaddr(ethaddr, mac_addr);
  742. }
  743. #endif
  744. if (!env_get("serial#")) {
  745. snprintf(serial_string, sizeof(serial_string),
  746. "%08x%08x", sid[0], sid[3]);
  747. env_set("serial#", serial_string);
  748. }
  749. }
  750. }
  751. int misc_init_r(void)
  752. {
  753. uint boot;
  754. env_set("fel_booted", NULL);
  755. env_set("fel_scriptaddr", NULL);
  756. env_set("mmc_bootdev", NULL);
  757. boot = sunxi_get_boot_device();
  758. /* determine if we are running in FEL mode */
  759. if (boot == BOOT_DEVICE_BOARD) {
  760. env_set("fel_booted", "1");
  761. parse_spl_header(SPL_ADDR);
  762. /* or if we booted from MMC, and which one */
  763. } else if (boot == BOOT_DEVICE_MMC1) {
  764. env_set("mmc_bootdev", "0");
  765. } else if (boot == BOOT_DEVICE_MMC2) {
  766. env_set("mmc_bootdev", "1");
  767. }
  768. setup_environment(gd->fdt_blob);
  769. #ifdef CONFIG_USB_ETHER
  770. usb_ether_init();
  771. #endif
  772. return 0;
  773. }
  774. int ft_board_setup(void *blob, struct bd_info *bd)
  775. {
  776. int __maybe_unused r;
  777. /*
  778. * Call setup_environment again in case the boot fdt has
  779. * ethernet aliases the u-boot copy does not have.
  780. */
  781. setup_environment(blob);
  782. #ifdef CONFIG_VIDEO_DT_SIMPLEFB
  783. r = sunxi_simplefb_setup(blob);
  784. if (r)
  785. return r;
  786. #endif
  787. return 0;
  788. }
  789. #ifdef CONFIG_SPL_LOAD_FIT
  790. int board_fit_config_name_match(const char *name)
  791. {
  792. struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
  793. const char *cmp_str = (const char *)spl;
  794. /* Check if there is a DT name stored in the SPL header and use that. */
  795. if (spl != INVALID_SPL_HEADER && spl->dt_name_offset) {
  796. cmp_str += spl->dt_name_offset;
  797. } else {
  798. #ifdef CONFIG_DEFAULT_DEVICE_TREE
  799. cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
  800. #else
  801. return 0;
  802. #endif
  803. };
  804. #ifdef CONFIG_PINE64_DT_SELECTION
  805. /* Differentiate the two Pine64 board DTs by their DRAM size. */
  806. if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
  807. if ((gd->ram_size > 512 * 1024 * 1024))
  808. return !strstr(name, "plus");
  809. else
  810. return !!strstr(name, "plus");
  811. } else {
  812. return strcmp(name, cmp_str);
  813. }
  814. #endif
  815. return strcmp(name, cmp_str);
  816. }
  817. #endif