rsdproto.h 14 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Murray Jensen <Murray.Jensen@cmst.csiro.au>
  4. *
  5. * (C) Copyright 2000
  6. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  7. * Marius Groeger <mgroeger@sysgo.de>
  8. *
  9. * Configuation settings for the R&S Protocol Board board.
  10. *
  11. * See file CREDITS for list of people who contributed to this
  12. * project.
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU General Public License as
  16. * published by the Free Software Foundation; either version 2 of
  17. * the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, write to the Free Software
  26. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27. * MA 02111-1307 USA
  28. */
  29. #ifndef __CONFIG_H
  30. #define __CONFIG_H
  31. /*
  32. * High Level Configuration Options
  33. * (easy to change)
  34. */
  35. #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
  36. #define CONFIG_RSD_PROTO 1 /* on a R&S Protocol Board */
  37. /*
  38. * select serial console configuration
  39. *
  40. * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  41. * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  42. * for SCC).
  43. *
  44. * if CONFIG_CONS_NONE is defined, then the serial console routines must
  45. * defined elsewhere.
  46. */
  47. #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
  48. #define CONFIG_CONS_ON_SCC /* define if console on SCC */
  49. #undef CONFIG_CONS_NONE /* define if console on neither */
  50. #define CONFIG_CONS_INDEX 1 /* which SMC/SCC channel for console */
  51. /*
  52. * select ethernet configuration
  53. *
  54. * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  55. * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  56. * for FCC)
  57. *
  58. * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  59. * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  60. * from CONFIG_COMMANDS to remove support for networking.
  61. */
  62. #undef CONFIG_ETHER_ON_SCC /* define if ethernet on SCC */
  63. #define CONFIG_ETHER_ON_FCC /* define if ethernet on FCC */
  64. #undef CONFIG_ETHER_NONE /* define if ethernet on neither */
  65. #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
  66. #if (CONFIG_ETHER_INDEX == 2)
  67. /*
  68. * - Rx-CLK is CLK13
  69. * - Tx-CLK is CLK14
  70. * - Select bus for bd/buffers (see 28-13)
  71. * - Enable Full Duplex in FSMR
  72. */
  73. # define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  74. # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  75. # define CFG_CPMFCR_RAMTYPE (0)
  76. # define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
  77. #endif /* CONFIG_ETHER_INDEX */
  78. /* allow to overwrite serial and ethaddr */
  79. #define CONFIG_ENV_OVERWRITE
  80. /* enable I2C */
  81. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  82. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  83. #define CFG_I2C_SLAVE 0x7F
  84. /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  85. #define CONFIG_8260_CLKIN 50000000 /* in Hz */
  86. #define CONFIG_BAUDRATE 115200
  87. #define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_KGDB)
  88. /* Define this if you want to boot from 0x00000100. If you don't define
  89. * this, you will need to program the bootloader to 0xfff00000, and
  90. * get the hardware reset config words at 0xfe000000. The simplest
  91. * way to do that is to program the bootloader at both addresses.
  92. * It is suggested that you just let U-Boot live at 0x00000000.
  93. */
  94. #define CFG_RSD_BOOT_LOW 1
  95. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  96. #include <cmd_confdefs.h>
  97. #define CONFIG_BOOTDELAY 5
  98. #define CONFIG_BOOTARGS "devfs=mount root=ramfs"
  99. #define CONFIG_ETHADDR 08:00:3e:26:0a:5a
  100. #define CONFIG_NETMASK 255.255.0.0
  101. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  102. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  103. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  104. #endif
  105. /*
  106. * Miscellaneous configurable options
  107. */
  108. #define CFG_LONGHELP /* undef to save memory */
  109. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  110. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  111. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  112. #else
  113. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  114. #endif
  115. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  116. #define CFG_MAXARGS 16 /* max number of command args */
  117. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  118. #define CFG_MEMTEST_START 0x00400000 /* memtest works on */
  119. #define CFG_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
  120. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  121. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  122. /* valid baudrates */
  123. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  124. /*
  125. * Low Level Configuration Settings
  126. * (address mappings, register initial values, etc.)
  127. * You should know what you are doing if you make changes here.
  128. */
  129. /*-----------------------------------------------------------------------
  130. * Physical Memory Map
  131. */
  132. #define PHYS_SDRAM_60X 0x00000000 /* SDRAM (60x Bus) */
  133. #define PHYS_SDRAM_60X_SIZE 0x08000000 /* 128 MB */
  134. #define PHYS_SDRAM_LOCAL 0x40000000 /* SDRAM (Local Bus) */
  135. #define PHYS_SDRAM_LOCAL_SIZE 0x04000000 /* 64 MB */
  136. #define PHYS_DPRAM_PCI 0xE8000000 /* DPRAM PPC/PCI */
  137. #define PHYS_DPRAM_PCI_SIZE 0x00020000 /* 128 KB */
  138. /*#define PHYS_DPRAM_PCI_SEM 0x04020000 / * DPRAM PPC/PCI Semaphore */
  139. /*#define PHYS_DPRAM_PCI_SEM_SIZE 0x00000001 / * 1 Byte */
  140. #define PHYS_DPRAM_SHARC 0xE8100000 /* DPRAM PPC/Sharc */
  141. #define PHYS_DPRAM_SHARC_SIZE 0x00040000 /* 256 KB */
  142. /*#define PHYS_DPRAM_SHARC_SEM 0x04140000 / * DPRAM PPC/Sharc Semaphore */
  143. /*#define PHYS_DPRAM_SHARC_SEM_SIZE 0x00000001 / * 1 Byte */
  144. #define PHYS_VIRTEX_REGISTER 0xE8300000 /* FPGA implemented register */
  145. #define PHYS_VIRTEX_REGISTER_SIZE 0x00000100
  146. #define PHYS_USB 0x04200000 /* USB Controller (60x Bus) */
  147. #define PHYS_USB_SIZE 0x00000002 /* 2 Bytes */
  148. #define PHYS_IMMR 0xF0000000 /* Internal Memory Mapped Reg. */
  149. #define PHYS_FLASH 0xFF000000 /* Flash (60x Bus) */
  150. #define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
  151. #define CFG_IMMR PHYS_IMMR
  152. /*-----------------------------------------------------------------------
  153. * Reset Address
  154. *
  155. * In order to reset the CPU, U-Boot jumps to a special address which
  156. * causes a machine check exception. The default address for this is
  157. * CFG_MONITOR_BASE - sizeof (ulong), which might not always work, eg. when
  158. * testing the monitor in RAM using a JTAG debugger.
  159. *
  160. * Just set CFG_RESET_ADDRESS to an address that you know is sure to
  161. * cause a bus error on your hardware.
  162. */
  163. #define CFG_RESET_ADDRESS 0x20000000
  164. /*-----------------------------------------------------------------------
  165. * Hard Reset Configuration Words
  166. */
  167. #if defined(CFG_RSD_BOOT_LOW)
  168. # define CFG_RSD_HRCW_BOOT_FLAGS (HRCW_CIP | HRCW_BMS)
  169. #else
  170. # define CFG_RSD_HRCW_BOOT_FLAGS (0)
  171. #endif /* defined(CFG_RSD_BOOT_LOW) */
  172. /* get the HRCW ISB field from CFG_IMMR */
  173. #define CFG_RSD_HRCW_IMMR ( ((CFG_IMMR & 0x10000000) >> 10) |\
  174. ((CFG_IMMR & 0x01000000) >> 7) |\
  175. ((CFG_IMMR & 0x00100000) >> 4) )
  176. #define CFG_HRCW_MASTER (HRCW_L2CPC10 | \
  177. HRCW_DPPC11 | \
  178. CFG_RSD_HRCW_IMMR |\
  179. HRCW_MMR00 | \
  180. HRCW_APPC10 | \
  181. HRCW_CS10PC00 | \
  182. HRCW_MODCK_H0000 |\
  183. CFG_RSD_HRCW_BOOT_FLAGS)
  184. /* no slaves */
  185. #define CFG_HRCW_SLAVE1 0
  186. #define CFG_HRCW_SLAVE2 0
  187. #define CFG_HRCW_SLAVE3 0
  188. #define CFG_HRCW_SLAVE4 0
  189. #define CFG_HRCW_SLAVE5 0
  190. #define CFG_HRCW_SLAVE6 0
  191. #define CFG_HRCW_SLAVE7 0
  192. /*-----------------------------------------------------------------------
  193. * Definitions for initial stack pointer and data area (in DPRAM)
  194. */
  195. #define CFG_INIT_RAM_ADDR CFG_IMMR
  196. #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
  197. #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  198. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  199. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  200. /*-----------------------------------------------------------------------
  201. * Start addresses for the final memory configuration
  202. * (Set up by the startup code)
  203. * Please note that CFG_SDRAM_BASE _must_ start at 0
  204. * Note also that the logic that sets CFG_RAMBOOT is platform dependend.
  205. */
  206. #define CFG_SDRAM_BASE PHYS_SDRAM_60X
  207. #define CFG_FLASH_BASE PHYS_FLASH
  208. /*#define CFG_MONITOR_BASE 0x200000 */
  209. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  210. #if CFG_MONITOR_BASE < CFG_FLASH_BASE
  211. #define CFG_RAMBOOT
  212. #endif
  213. #define CFG_MONITOR_LEN (160 << 10) /* Reserve 160 kB for Monitor */
  214. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  215. /*
  216. * For booting Linux, the board info and command line data
  217. * have to be in the first 8 MB of memory, since this is
  218. * the maximum mapped by the Linux kernel during initialization.
  219. */
  220. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  221. /*-----------------------------------------------------------------------
  222. * FLASH and environment organization
  223. */
  224. #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  225. #define CFG_MAX_FLASH_SECT 63 /* max number of sectors on one chip */
  226. #define CFG_FLASH_ERASE_TOUT 12000 /* Timeout for Flash Erase (in ms) */
  227. #define CFG_FLASH_WRITE_TOUT 3000 /* Timeout for Flash Write (in ms) */
  228. /* turn off NVRAM env feature */
  229. #undef CONFIG_NVRAM_ENV
  230. #define CFG_ENV_IS_IN_FLASH 1
  231. #define CFG_ENV_ADDR (PHYS_FLASH + 0x28000) /* Addr of Environment Sector */
  232. #define CFG_ENV_SECT_SIZE 0x8000 /* Total Size of Environment Sector */
  233. /*-----------------------------------------------------------------------
  234. * Cache Configuration
  235. */
  236. #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
  237. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  238. #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  239. #endif
  240. /*-----------------------------------------------------------------------
  241. * HIDx - Hardware Implementation-dependent Registers 2-11
  242. *-----------------------------------------------------------------------
  243. * HID0 also contains cache control - initially enable both caches and
  244. * invalidate contents, then the final state leaves only the instruction
  245. * cache enabled. Note that Power-On and Hard reset invalidate the caches,
  246. * but Soft reset does not.
  247. *
  248. * HID1 has only read-only information - nothing to set.
  249. */
  250. #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|HID0_IFEM|HID0_ABE)
  251. #define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE|HID0_EMCP)
  252. #define CFG_HID2 0
  253. /*-----------------------------------------------------------------------
  254. * RMR - Reset Mode Register
  255. *-----------------------------------------------------------------------
  256. */
  257. #define CFG_RMR 0
  258. /*-----------------------------------------------------------------------
  259. * BCR - Bus Configuration 4-25
  260. *-----------------------------------------------------------------------
  261. */
  262. #define CFG_BCR 0x100c0000
  263. /*-----------------------------------------------------------------------
  264. * SIUMCR - SIU Module Configuration 4-31
  265. *-----------------------------------------------------------------------
  266. */
  267. #define CFG_SIUMCR (SIUMCR_DPPC11 | SIUMCR_L2CPC10 | SIUMCR_APPC10 | \
  268. SIUMCR_CS10PC01 | SIUMCR_BCTLC01)
  269. /*-----------------------------------------------------------------------
  270. * SYPCR - System Protection Control 11-9
  271. * SYPCR can only be written once after reset!
  272. *-----------------------------------------------------------------------
  273. * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  274. */
  275. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_PBME | SYPCR_LBME | \
  276. SYPCR_SWRI | SYPCR_SWP)
  277. /*-----------------------------------------------------------------------
  278. * TMCNTSC - Time Counter Status and Control 4-40
  279. *-----------------------------------------------------------------------
  280. * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  281. * and enable Time Counter
  282. */
  283. #define CFG_TMCNTSC (TMCNTSC_SEC | TMCNTSC_ALR | TMCNTSC_TCF | TMCNTSC_TCE)
  284. /*-----------------------------------------------------------------------
  285. * PISCR - Periodic Interrupt Status and Control 4-42
  286. *-----------------------------------------------------------------------
  287. * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  288. * Periodic timer
  289. */
  290. #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
  291. /*-----------------------------------------------------------------------
  292. * SCCR - System Clock Control 9-8
  293. *-----------------------------------------------------------------------
  294. */
  295. #define CFG_SCCR 0x00000000
  296. /*-----------------------------------------------------------------------
  297. * RCCR - RISC Controller Configuration 13-7
  298. *-----------------------------------------------------------------------
  299. */
  300. #define CFG_RCCR 0
  301. /*
  302. * Init Memory Controller:
  303. */
  304. #define CFG_PSDMR 0x494D2452
  305. #define CFG_LSDMR 0x49492552
  306. /* Flash */
  307. #define CFG_BR0_PRELIM (PHYS_FLASH | BRx_V)
  308. #define CFG_OR0_PRELIM (P2SZ_TO_AM(PHYS_FLASH_SIZE) | \
  309. ORxG_BCTLD | \
  310. ORxG_SCY_5_CLK)
  311. /* DPRAM to the PCI BUS on the protocol board */
  312. #define CFG_BR1_PRELIM (PHYS_DPRAM_PCI | BRx_V)
  313. #define CFG_OR1_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_PCI_SIZE) | \
  314. ORxG_ACS_DIV4)
  315. /* 60x Bus SDRAM */
  316. #define CFG_BR2_PRELIM (PHYS_SDRAM_60X | BRx_MS_SDRAM_P | BRx_V)
  317. #define CFG_OR2_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_60X_SIZE) | \
  318. ORxS_BPD_4 | \
  319. ORxS_ROWST_PBI1_A2 | \
  320. ORxS_NUMR_13 | \
  321. ORxS_IBID)
  322. /* Virtex-FPGA - Register */
  323. #define CFG_BR3_PRELIM (PHYS_VIRTEX_REGISTER | BRx_V)
  324. #define CFG_OR3_PRELIM (ORxS_SIZE_TO_AM(PHYS_VIRTEX_REGISTER_SIZE) | \
  325. ORxG_SCY_1_CLK | \
  326. ORxG_ACS_DIV2 | \
  327. ORxG_CSNT )
  328. /* local bus SDRAM */
  329. #define CFG_BR4_PRELIM (PHYS_SDRAM_LOCAL | BRx_PS_32 | BRx_MS_SDRAM_L | BRx_V)
  330. #define CFG_OR4_PRELIM (ORxS_SIZE_TO_AM(PHYS_SDRAM_LOCAL_SIZE) | \
  331. ORxS_BPD_4 | \
  332. ORxS_ROWST_PBI1_A4 | \
  333. ORxS_NUMR_13)
  334. /* DPRAM to the Sharc-Bus on the protocol board */
  335. #define CFG_BR5_PRELIM (PHYS_DPRAM_SHARC | BRx_V)
  336. #define CFG_OR5_PRELIM (P2SZ_TO_AM(PHYS_DPRAM_SHARC_SIZE) | \
  337. ORxG_ACS_DIV4)
  338. /*
  339. * Internal Definitions
  340. *
  341. * Boot Flags
  342. */
  343. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  344. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  345. #endif /* __CONFIG_H */