lwmon.h 18 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_MPC823 1 /* This is a MPC823E CPU */
  33. #define CONFIG_LWMON 1 /* ...on a LWMON board */
  34. #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
  35. #define CONFIG_LCD 1 /* use LCD controller ... */
  36. #define CONFIG_HLD1045 1 /* ... with a HLD1045 display */
  37. #if 1
  38. #define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
  39. #else
  40. #define CONFIG_8xx_CONS_SCC2
  41. #endif
  42. #define CONFIG_BAUDRATE 115200 /* with watchdog >= 38400 needed */
  43. #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
  44. #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  45. /* pre-boot commands */
  46. #define CONFIG_PREBOOT "setenv bootdelay 15"
  47. #undef CONFIG_BOOTARGS
  48. /* POST support */
  49. #define CONFIG_POST (CFG_POST_CACHE | \
  50. CFG_POST_WATCHDOG | \
  51. CFG_POST_RTC | \
  52. CFG_POST_MEMORY | \
  53. CFG_POST_CPU | \
  54. CFG_POST_UART | \
  55. CFG_POST_ETHER | \
  56. CFG_POST_SPI | \
  57. CFG_POST_USB | \
  58. CFG_POST_SPR)
  59. #define CONFIG_BOOTCOMMAND "run flash_self"
  60. #define CONFIG_EXTRA_ENV_SETTINGS \
  61. "kernel_addr=40040000\0" \
  62. "ramdisk_addr=40100000\0" \
  63. "magic_keys=#3\0" \
  64. "key_magic#=28\0" \
  65. "key_cmd#=setenv addfb setenv bootargs \\$(bootargs) console=tty0\0" \
  66. "key_magic3=24\0" \
  67. "key_cmd3=echo *** Entering Test Mode ***;" \
  68. "setenv add_misc setenv bootargs \\$(bootargs) testmode\0" \
  69. "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath)\0" \
  70. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  71. "addfb=setenv bootargs $(bootargs) console=ttyS1,$(baudrate)\0" \
  72. "addip=setenv bootargs $(bootargs) " \
  73. "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \
  74. "panic=1\0" \
  75. "add_wdt=setenv bootargs $(bootargs) $(wdt_args)\0" \
  76. "flash_nfs=run nfsargs addip add_wdt addfb;" \
  77. "bootm $(kernel_addr)\0" \
  78. "flash_self=run ramargs addip add_wdt addfb;" \
  79. "bootm $(kernel_addr) $(ramdisk_addr)\0" \
  80. "net_nfs=tftp 100000 /tftpboot/pImage.lwmon;" \
  81. "run nfsargs addip add_wdt addfb;bootm\0" \
  82. "rootpath=/opt/eldk/ppc_8xx\0" \
  83. "load=tftp 100000 /tftpboot/u-boot.bin\0" \
  84. "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $(filesize)\0" \
  85. "wdt_args=wdt_8xx=off\0" \
  86. "verify=no"
  87. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  88. #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  89. #define CONFIG_WATCHDOG 1 /* watchdog enabled */
  90. #undef CONFIG_STATUS_LED /* Status LED disabled */
  91. /* enable I2C and select the hardware/software driver */
  92. #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
  93. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  94. #ifdef CONFIG_HARD_I2C
  95. /*
  96. * Hardware (CPM) I2C driver configuration
  97. */
  98. # define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
  99. # define CFG_I2C_SLAVE 0xFE
  100. #endif /* CONFIG_HARD_I2C */
  101. #ifdef CONFIG_SOFT_I2C
  102. /*
  103. * Software (bit-bang) I2C driver configuration
  104. */
  105. #define PB_SCL 0x00000020 /* PB 26 */
  106. #define PB_SDA 0x00000010 /* PB 27 */
  107. #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
  108. #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
  109. #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
  110. #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
  111. #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
  112. else immr->im_cpm.cp_pbdat &= ~PB_SDA
  113. #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
  114. else immr->im_cpm.cp_pbdat &= ~PB_SCL
  115. #define I2C_DELAY udelay(1) /* 1/4 I2C clock duration */
  116. #endif /* CONFIG_SOFT_I2C */
  117. #define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
  118. #ifdef CONFIG_POST
  119. #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
  120. #else
  121. #define CFG_CMD_POST_DIAG 0
  122. #endif
  123. #ifdef CONFIG_8xx_CONS_SCC2 /* Can't use ethernet, then */
  124. #define CONFIG_COMMANDS ( (CONFIG_CMD_DFL & ~CFG_CMD_NET) | \
  125. CFG_CMD_DATE | \
  126. CFG_CMD_I2C | \
  127. CFG_CMD_EEPROM | \
  128. CFG_CMD_IDE | \
  129. CFG_CMD_BSP | \
  130. CFG_CMD_POST_DIAG )
  131. #else
  132. #define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
  133. CFG_CMD_DHCP | \
  134. CFG_CMD_DATE | \
  135. CFG_CMD_I2C | \
  136. CFG_CMD_EEPROM | \
  137. CFG_CMD_IDE | \
  138. CFG_CMD_BSP | \
  139. CFG_CMD_POST_DIAG )
  140. #endif
  141. #define CONFIG_MAC_PARTITION
  142. #define CONFIG_DOS_PARTITION
  143. #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  144. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  145. #include <cmd_confdefs.h>
  146. /*----------------------------------------------------------------------*/
  147. /*
  148. * Miscellaneous configurable options
  149. */
  150. #define CFG_LONGHELP /* undef to save memory */
  151. #define CFG_PROMPT "=> " /* Monitor Command Prompt */
  152. #undef CFG_HUSH_PARSER /* enable "hush" shell */
  153. #ifdef CFG_HUSH_PARSER
  154. #define CFG_PROMPT_HUSH_PS2 "> "
  155. #endif
  156. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  157. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  158. #else
  159. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  160. #endif
  161. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  162. #define CFG_MAXARGS 16 /* max number of command args */
  163. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  164. #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
  165. #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
  166. #define CFG_LOAD_ADDR 0x00100000 /* default load address */
  167. #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
  168. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  169. #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  170. /*
  171. * Low Level Configuration Settings
  172. * (address mappings, register initial values, etc.)
  173. * You should know what you are doing if you make changes here.
  174. */
  175. /*-----------------------------------------------------------------------
  176. * Internal Memory Mapped Register
  177. */
  178. #define CFG_IMMR 0xFFF00000
  179. /*-----------------------------------------------------------------------
  180. * Definitions for initial stack pointer and data area (in DPRAM)
  181. */
  182. #define CFG_INIT_RAM_ADDR CFG_IMMR
  183. #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  184. #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  185. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  186. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  187. /*-----------------------------------------------------------------------
  188. * Start addresses for the final memory configuration
  189. * (Set up by the startup code)
  190. * Please note that CFG_SDRAM_BASE _must_ start at 0
  191. */
  192. #define CFG_SDRAM_BASE 0x00000000
  193. #define CFG_FLASH_BASE 0x40000000
  194. #if defined(DEBUG) || (CONFIG_COMMANDS & CFG_CMD_IDE)
  195. #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  196. #else
  197. #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
  198. #endif
  199. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  200. #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  201. /*
  202. * For booting Linux, the board info and command line data
  203. * have to be in the first 8 MB of memory, since this is
  204. * the maximum mapped by the Linux kernel during initialization.
  205. */
  206. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  207. /*-----------------------------------------------------------------------
  208. * FLASH organization
  209. */
  210. #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  211. #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
  212. #define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
  213. #define CFG_FLASH_WRITE_TOUT 600 /* Timeout for Flash Write (in ms) */
  214. #if 1
  215. /* Put environment in flash which is much faster to boot */
  216. #define CFG_ENV_IS_IN_FLASH 1
  217. #define CFG_ENV_ADDR 0x40040000 /* Address of Environment Sector */
  218. #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
  219. #define CFG_ENV_SECT_SIZE 0x40000 /* we have BIG sectors only :-( */
  220. #else
  221. /* Environment in EEPROM */
  222. #define CFG_ENV_IS_IN_EEPROM 1
  223. #define CFG_ENV_OFFSET 0
  224. #define CFG_ENV_SIZE 2048
  225. #endif
  226. /*-----------------------------------------------------------------------
  227. * I2C/EEPROM Configuration
  228. */
  229. #define CFG_I2C_AUDIO_ADDR 0x28 /* Audio volume control */
  230. #define CFG_I2C_SYSMON_ADDR 0x2E /* LM87 System Monitor */
  231. #define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
  232. #define CFG_I2C_POWER_A_ADDR 0x52 /* PCMCIA/USB power switch, channel A */
  233. #define CFG_I2C_POWER_B_ADDR 0x53 /* PCMCIA/USB power switch, channel B */
  234. #define CFG_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
  235. #define CFG_I2C_PICIO_ADDR 0x57 /* PIC IO Expander */
  236. #define CONFIG_USE_FRAM /* Use FRAM instead of EEPROM */
  237. #ifdef CONFIG_USE_FRAM /* use FRAM */
  238. #define CFG_I2C_EEPROM_ADDR 0x55 /* FRAM FM24CL64 */
  239. #define CFG_I2C_EEPROM_ADDR_LEN 2
  240. #else /* use EEPROM */
  241. #define CFG_I2C_EEPROM_ADDR 0x58 /* EEPROM AT24C164 */
  242. #define CFG_I2C_EEPROM_ADDR_LEN 1
  243. #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
  244. #endif /* CONFIG_USE_FRAM */
  245. #define CFG_EEPROM_PAGE_WRITE_BITS 4
  246. /*-----------------------------------------------------------------------
  247. * Cache Configuration
  248. */
  249. #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  250. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  251. #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  252. #endif
  253. /*-----------------------------------------------------------------------
  254. * SYPCR - System Protection Control 11-9
  255. * SYPCR can only be written once after reset!
  256. *-----------------------------------------------------------------------
  257. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  258. */
  259. #if 0 && defined(CONFIG_WATCHDOG) /* LWMON uses external MAX706TESA WD */
  260. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  261. SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  262. #else
  263. #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  264. #endif
  265. /*-----------------------------------------------------------------------
  266. * SIUMCR - SIU Module Configuration 11-6
  267. *-----------------------------------------------------------------------
  268. * PCMCIA config., multi-function pin tri-state
  269. */
  270. /* EARB, DBGC and DBPC are initialised by the HCW */
  271. /* => 0x000000C0 */
  272. #define CFG_SIUMCR (SIUMCR_GB5E)
  273. /*#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
  274. /*-----------------------------------------------------------------------
  275. * TBSCR - Time Base Status and Control 11-26
  276. *-----------------------------------------------------------------------
  277. * Clear Reference Interrupt Status, Timebase freezing enabled
  278. */
  279. #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  280. /*-----------------------------------------------------------------------
  281. * PISCR - Periodic Interrupt Status and Control 11-31
  282. *-----------------------------------------------------------------------
  283. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  284. */
  285. #define CFG_PISCR (PISCR_PS | PISCR_PITF)
  286. /*-----------------------------------------------------------------------
  287. * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  288. *-----------------------------------------------------------------------
  289. * Reset PLL lock status sticky bit, timer expired status bit and timer
  290. * interrupt status bit, set PLL multiplication factor !
  291. */
  292. /* 0x00405000 */
  293. #define CFG_PLPRCR_MF 4 /* (4+1) * 13.2 = 66 MHz Clock */
  294. #define CFG_PLPRCR \
  295. ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
  296. PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
  297. /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
  298. PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
  299. )
  300. #define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*13200000)
  301. /*-----------------------------------------------------------------------
  302. * SCCR - System Clock and reset Control Register 15-27
  303. *-----------------------------------------------------------------------
  304. * Set clock output, timebase and RTC source and divider,
  305. * power management and some other internal clocks
  306. */
  307. #define SCCR_MASK SCCR_EBDF11
  308. /* 0x01800000 */
  309. #define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
  310. SCCR_RTDIV | SCCR_RTSEL | \
  311. /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
  312. SCCR_EBDF00 | SCCR_DFSYNC00 | \
  313. SCCR_DFBRG00 | SCCR_DFNL000 | \
  314. SCCR_DFNH000 | SCCR_DFLCD100 | \
  315. SCCR_DFALCD01)
  316. /*-----------------------------------------------------------------------
  317. * RTCSC - Real-Time Clock Status and Control Register 11-27
  318. *-----------------------------------------------------------------------
  319. */
  320. /* 0x00C3 => 0x0003 */
  321. #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  322. /*-----------------------------------------------------------------------
  323. * RCCR - RISC Controller Configuration Register 19-4
  324. *-----------------------------------------------------------------------
  325. */
  326. #define CFG_RCCR 0x0000
  327. /*-----------------------------------------------------------------------
  328. * RMDS - RISC Microcode Development Support Control Register
  329. *-----------------------------------------------------------------------
  330. */
  331. #define CFG_RMDS 0
  332. /*-----------------------------------------------------------------------
  333. *
  334. * Interrupt Levels
  335. *-----------------------------------------------------------------------
  336. */
  337. #define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
  338. /*-----------------------------------------------------------------------
  339. * PCMCIA stuff
  340. *-----------------------------------------------------------------------
  341. *
  342. */
  343. #define CFG_PCMCIA_MEM_ADDR (0x50000000)
  344. #define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
  345. #define CFG_PCMCIA_DMA_ADDR (0x54000000)
  346. #define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
  347. #define CFG_PCMCIA_ATTRB_ADDR (0x58000000)
  348. #define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  349. #define CFG_PCMCIA_IO_ADDR (0x5C000000)
  350. #define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
  351. /*-----------------------------------------------------------------------
  352. * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
  353. *-----------------------------------------------------------------------
  354. */
  355. #define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
  356. #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
  357. #undef CONFIG_IDE_LED /* LED for ide not supported */
  358. #undef CONFIG_IDE_RESET /* reset for ide not supported */
  359. #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
  360. #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
  361. #define CFG_ATA_IDE0_OFFSET 0x0000
  362. #define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
  363. /* Offset for data I/O */
  364. #define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
  365. /* Offset for normal register accesses */
  366. #define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
  367. /* Offset for alternate registers */
  368. #define CFG_ATA_ALT_OFFSET 0x0100
  369. /*-----------------------------------------------------------------------
  370. *
  371. *-----------------------------------------------------------------------
  372. *
  373. */
  374. /*#define CFG_DER 0x2002000F*/
  375. #define CFG_DER 0
  376. /*
  377. * Init Memory Controller:
  378. *
  379. * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
  380. */
  381. #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
  382. #define FLASH_BASE1_PRELIM 0x41000000 /* FLASH bank #1 */
  383. /* used to re-map FLASH:
  384. * restrict access enough to keep SRAM working (if any)
  385. * but not too much to meddle with FLASH accesses
  386. */
  387. #define CFG_REMAP_OR_AM 0xFF000000 /* OR addr mask */
  388. #define CFG_PRELIM_OR_AM 0xFF000000 /* OR addr mask */
  389. /* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */
  390. #define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK)
  391. #define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
  392. CFG_OR_TIMING_FLASH)
  393. #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
  394. CFG_OR_TIMING_FLASH)
  395. /* 16 bit, bank valid */
  396. #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
  397. #define CFG_OR1_REMAP CFG_OR0_REMAP
  398. #define CFG_OR1_PRELIM CFG_OR0_PRELIM
  399. #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
  400. /*
  401. * BR3/OR3: SDRAM
  402. *
  403. * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
  404. */
  405. #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
  406. #define SDRAM_PRELIM_OR_AM 0xF0000000 /* map 256 MB (>SDRAM_MAX_SIZE!) */
  407. #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
  408. #define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB SDRAM */
  409. #define CFG_OR3_PRELIM (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
  410. #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
  411. /*
  412. * BR5/OR5: Touch Panel
  413. *
  414. * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
  415. */
  416. #define TOUCHPNL_BASE 0x20000000
  417. #define TOUCHPNL_OR_AM 0xFFFF8000
  418. #define TOUCHPNL_TIMING OR_SCY_0_CLK
  419. #define CFG_OR5_PRELIM (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
  420. TOUCHPNL_TIMING )
  421. #define CFG_BR5_PRELIM ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
  422. #define CFG_MEMORY_75
  423. #undef CFG_MEMORY_7E
  424. #undef CFG_MEMORY_8E
  425. /*
  426. * Memory Periodic Timer Prescaler
  427. */
  428. /* periodic timer for refresh */
  429. #define CFG_MPTPR 0x200
  430. /*
  431. * MAMR settings for SDRAM
  432. */
  433. #define CFG_MAMR_8COL 0x80802114
  434. #define CFG_MAMR_9COL 0x80904114
  435. /*
  436. * MAR setting for SDRAM
  437. */
  438. #define CFG_MAR 0x00000088
  439. /*
  440. * Internal Definitions
  441. *
  442. * Boot Flags
  443. */
  444. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  445. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  446. #endif /* __CONFIG_H */