W7OLMG.h 12 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_405GP 1 /* This is a PPC405GP CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC405 family */
  34. #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
  35. #define CONFIG_W7OLMG 1 /* ...specifically an LMG */
  36. #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
  37. #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  38. #define CONFIG_BAUDRATE 9600
  39. #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
  40. #if 1
  41. #define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
  42. #else
  43. #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
  44. #endif
  45. #undef CONFIG_BOOTARGS
  46. #define CONFIG_LOADADDR F0080000
  47. #define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
  48. #define CONFIG_OVERWRITE_ETHADDR_ONCE
  49. #define CONFIG_IPADDR 192.168.1.1
  50. #define CONFIG_NETMASK 255.255.255.0
  51. #define CONFIG_SERVERIP 192.168.1.2
  52. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  53. #undef CFG_LOADS_BAUD_CHANGE /* disallow baudrate change */
  54. #define CONFIG_MII 1 /* MII PHY management */
  55. #define CONFIG_PHY_ADDR 0 /* PHY address */
  56. #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
  57. #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
  58. #define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */
  59. #define CFG_DTT_MAX_TEMP 70
  60. #define CFG_DTT_LOW_TEMP -30
  61. #define CFG_DTT_HYSTERESIS 3
  62. #define CONFIG_COMMANDS \
  63. (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_IRQ | CFG_CMD_ASKENV | \
  64. CFG_CMD_DHCP | CFG_CMD_BEDBUG | CFG_CMD_DATE | CFG_CMD_I2C | \
  65. CFG_CMD_EEPROM | CFG_CMD_ELF | CFG_CMD_BSP | CFG_CMD_REGINFO | \
  66. CFG_CMD_DTT)
  67. /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  68. #include <cmd_confdefs.h>
  69. #undef CONFIG_WATCHDOG /* watchdog disabled */
  70. #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
  71. #define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
  72. /*
  73. * Miscellaneous configurable options
  74. */
  75. #define CFG_LONGHELP /* undef to save memory */
  76. #define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
  77. #undef CFG_HUSH_PARSER /* No hush parse for U-Boot */
  78. #ifdef CFG_HUSH_PARSER
  79. #define CFG_PROMPT_HUSH_PS2 "> "
  80. #endif
  81. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  82. #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  83. #else
  84. #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  85. #endif
  86. #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  87. #define CFG_MAXARGS 16 /* max number of command args */
  88. #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  89. #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
  90. #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  91. #undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
  92. #define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
  93. #define CFG_BASE_BAUD 384000
  94. /* The following table includes the supported baudrates */
  95. #define CFG_BAUDRATE_TABLE {9600}
  96. #define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
  97. #define CFG_LOAD_ADDR 0x100000 /* default load address */
  98. #define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */
  99. #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  100. /*-----------------------------------------------------------------------
  101. * PCI stuff
  102. *-----------------------------------------------------------------------
  103. */
  104. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  105. #define PCI_HOST_FORCE 1 /* configure as pci host */
  106. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  107. #define CONFIG_PCI /* include pci support */
  108. #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
  109. #define CONFIG_PCI_PNP /* pci plug-and-play */
  110. /* resource configuration */
  111. #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
  112. #define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
  113. #define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
  114. #define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
  115. #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  116. #define CFG_PCI_PTM2LA 0x00000000 /* disabled */
  117. #define CFG_PCI_PTM2MS 0x00000000 /* disabled */
  118. #define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
  119. /*-----------------------------------------------------------------------
  120. * Set up values for external bus controller
  121. * used by cpu_init.c
  122. *-----------------------------------------------------------------------
  123. */
  124. /* use PerWE instead of PCI_INT ( these functions share a pin ) */
  125. #define CONFIG_USE_PERWE 1
  126. /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
  127. #define CFG_TEMP_STACK_OCM 1
  128. /* bank 0 is boot flash */
  129. /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
  130. #define CFG_W7O_EBC_PB0AP 0x03050440
  131. /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
  132. #define CFG_W7O_EBC_PB0CR 0xFFE38000
  133. /* bank 1 is main flash */
  134. /* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
  135. #define CFG_EBC_PB1AP 0x04850240
  136. /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
  137. #define CFG_EBC_PB1CR 0xF00FC000
  138. /* bank 2 is RTC/NVRAM */
  139. /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
  140. #define CFG_EBC_PB2AP 0x03000440
  141. /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
  142. #define CFG_EBC_PB2CR 0xFC018000
  143. /* bank 3 is FPGA 0 */
  144. /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
  145. #define CFG_EBC_PB3AP 0x02000400
  146. /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
  147. #define CFG_EBC_PB3CR 0xFD01A000
  148. /* bank 4 is SAM 8 bit range */
  149. /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
  150. #define CFG_EBC_PB4AP 0x02840380
  151. /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
  152. #define CFG_EBC_PB4CR 0xFE878000
  153. /* bank 5 is SAM 16 bit range */
  154. /* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
  155. #define CFG_EBC_PB5AP 0x05040d80
  156. /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
  157. #define CFG_EBC_PB5CR 0xFD87A000
  158. /* bank 6 is unused */
  159. /* pb6ap = 0 */
  160. #define CFG_EBC_PB6AP 0x00000000
  161. /* pb6cr = 0 */
  162. #define CFG_EBC_PB6CR 0x00000000
  163. /* bank 7 is LED register */
  164. /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
  165. #define CFG_W7O_EBC_PB7AP 0x03050440
  166. /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
  167. #define CFG_W7O_EBC_PB7CR 0xFE01C000
  168. /*-----------------------------------------------------------------------
  169. * Start addresses for the final memory configuration
  170. * (Set up by the startup code)
  171. * Please note that CFG_SDRAM_BASE _must_ start at 0
  172. */
  173. #define CFG_SDRAM_BASE 0x00000000
  174. #define CFG_FLASH_BASE 0xFFFC0000
  175. #define CFG_MONITOR_BASE CFG_FLASH_BASE
  176. #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */
  177. #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  178. /*
  179. * For booting Linux, the board info and command line data
  180. * have to be in the first 8 MB of memory, since this is
  181. * the maximum mapped by the Linux kernel during initialization.
  182. */
  183. #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  184. /*-----------------------------------------------------------------------
  185. * FLASH organization
  186. */
  187. #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
  188. #define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
  189. #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
  190. #define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
  191. #define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */
  192. #if 1 /* Use NVRAM for environment variables */
  193. /*-----------------------------------------------------------------------
  194. * NVRAM organization
  195. */
  196. #define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
  197. #define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
  198. #define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
  199. #define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
  200. /*define CFG_ENV_ADDR \
  201. (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */
  202. #define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR
  203. #else /* Use Boot Flash for environment variables */
  204. /*-----------------------------------------------------------------------
  205. * Flash EEPROM for environment
  206. */
  207. #define CFG_ENV_IS_IN_FLASH 1
  208. #define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
  209. #define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */
  210. #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
  211. #endif
  212. /*-----------------------------------------------------------------------
  213. * I2C EEPROM (ATMEL 24C04N)
  214. */
  215. #define CONFIG_HARD_I2C 1 /* Hardware assisted I2C */
  216. #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
  217. #define CFG_I2C_SLAVE 0x7F
  218. #define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */
  219. #define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  220. #define CFG_EEPROM_PAGE_WRITE_ENABLE
  221. #define CFG_EEPROM_PAGE_WRITE_BITS 3
  222. #define CFG_I2C_MULTI_EEPROMS
  223. /*-----------------------------------------------------------------------
  224. * Definitions for Serial Presence Detect EEPROM address
  225. * (to get SDRAM settings)
  226. */
  227. #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
  228. /*-----------------------------------------------------------------------
  229. * Cache Configuration
  230. */
  231. #define CFG_DCACHE_SIZE 8192 /* For IBM 405 CPUs */
  232. #define CFG_CACHELINE_SIZE 32 /* ... */
  233. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  234. #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above val. */
  235. #endif
  236. /*
  237. * Init Memory Controller:
  238. */
  239. #define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
  240. #define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
  241. /* On Chip Memory location */
  242. #define CFG_OCM_DATA_ADDR 0xF8000000
  243. #define CFG_OCM_DATA_SIZE 0x1000
  244. /*-----------------------------------------------------------------------
  245. * Definitions for initial stack pointer and data area (in RAM)
  246. */
  247. #define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
  248. #define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
  249. #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  250. #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  251. #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  252. /*
  253. * Internal Definitions
  254. *
  255. * Boot Flags
  256. */
  257. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  258. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  259. #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  260. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  261. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  262. #endif
  263. /*
  264. * FPGA(s) configuration
  265. */
  266. #define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
  267. #define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */
  268. #define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
  269. #define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
  270. #define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
  271. #endif /* __CONFIG_H */